JPS59129448A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPS59129448A JPS59129448A JP58004995A JP499583A JPS59129448A JP S59129448 A JPS59129448 A JP S59129448A JP 58004995 A JP58004995 A JP 58004995A JP 499583 A JP499583 A JP 499583A JP S59129448 A JPS59129448 A JP S59129448A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- face part
- lead terminal
- substrate
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子を内部に収納する半導体パッケージ
の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor package that houses a semiconductor element therein.
従来、半導体素子、特に集積回路素子を収納するだめの
半導体パッケージは第１図に示すように、セラミック、
ガラス等の電気絶縁材料から成る絶縁基体ｌと蓋体２及
び前記絶縁基体ｌの外表面に従来周知のメタライズ法に
より形成された、半導体素子４と外部回路とを電気的に
接続するだめの外部リード端子３とにより構成されてお
り、その内部に半導体素子４が収納され、気密封止され
て半導体装置となる。Conventionally, semiconductor packages for accommodating semiconductor devices, especially integrated circuit devices, have been made of ceramic,
An insulating base l made of an electrically insulating material such as glass, a lid body 2, and an exterior of a chamber for electrically connecting the semiconductor element 4 and an external circuit, which are formed on the outer surface of the insulating base l by a conventionally well-known metallization method. A semiconductor element 4 is housed inside the lead terminal 3, and the semiconductor element 4 is hermetically sealed to form a semiconductor device.
この従来の半導体パッケージは、その内部に半に、外部
リード端子３の底面部３ａが当接するように載置され、
次にこれらを約３５０℃の温度に加熱された炉中に投入
して前記半田を溶融させ、導電部５ａと外部リード端子
底面部３ａとを半田接合することによって外部回路基板
５上に取着される。This conventional semiconductor package is placed so that the bottom part 3a of the external lead terminal 3 is in contact with the inside of the package, and
Next, these are put into a furnace heated to a temperature of about 350° C. to melt the solder, and the conductive part 5a and the external lead terminal bottom part 3a are soldered and attached to the external circuit board 5. be done.
しかし乍ら、この従来の半導体パッケージはその熱膨張
係数が一般に外部回路基板と大きく相違しており、該半
導体パッケージを外部回路基板上に半田付けする場合、
外部回路基板が半田溶融の熱によって半導体パッケージ
より大きく膨張し、その結果、外部回路基板上の導電部
の位置が大きく変動して半導体パッケージの外部リード
端子底内部との当接が維持できなくなるという欠点を有
していた。そのためこの従来の半導体パッケージでは外
部回路基板への取着が極めて困難で、内部に収納した半
導体素子を外部回路に良好に接続できないという欠点を
有していた。However, the coefficient of thermal expansion of this conventional semiconductor package is generally significantly different from that of an external circuit board, and when the semiconductor package is soldered onto an external circuit board,
The external circuit board expands more than the semiconductor package due to the heat of melting the solder, and as a result, the position of the conductive part on the external circuit board changes significantly, making it impossible to maintain contact with the inside of the bottom of the external lead terminal of the semiconductor package. It had drawbacks. Therefore, this conventional semiconductor package has the disadvantage that it is extremely difficult to attach it to an external circuit board, and that the semiconductor element housed inside cannot be well connected to an external circuit.
まだこの従来の半導体パッケージは外部リード端子の金
属層の層厚が極めて薄いため半導体パッケージを外部回
路基板上に半田付けした場合、半導体パッケージと外部
回路基板とが密着することとなり、取着工程后に行なわ
れる洗浄工程によっても両部材の狭い間隙内に入り込ん
だ汚物特に、半田中に含まれる低絶縁抵抗のフラックス
を除去することがヤきず、その結果、残留したフラック
ス等により半導体パッケージの外部リード端子間が短絡
し、半導体装置として実用に供しなくなるという欠点も
有していた。However, in this conventional semiconductor package, the metal layer of the external lead terminal is extremely thin, so when the semiconductor package is soldered onto the external circuit board, the semiconductor package and the external circuit board come into close contact, which causes problems after the mounting process. Even in the cleaning process carried out during the cleaning process, it is not possible to remove the dirt that has entered the narrow gap between the two components, especially the flux with low insulation resistance contained in the solder, and as a result, the external leads of the semiconductor package are It also had the disadvantage that the terminals were short-circuited, making it unusable as a semiconductor device.
本発明は上記欠点に鑑み案出されたもので、その目的は
外部回路基板との接合が確実で、内部に収納した半導体
素子を外部回路に確実に接続することができ、かつ外部
回路基板との間に端子短絡等の電気的悪影響を与える汚
物を完全に洗浄除去し得るようにした半導体パッケージ
を提供することにある。The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to ensure reliable bonding with an external circuit board, to reliably connect a semiconductor element housed inside to an external circuit, and to provide a method for connecting an external circuit board to an external circuit board. It is an object of the present invention to provide a semiconductor package in which contaminants that cause an adverse electrical effect such as a terminal short circuit can be completely cleaned and removed during the process.
本発明は絶縁基体及び無体から成る絶縁容器と、該容器
内に収納される半導体素子を外部回路に接続する外部リ
ード端子とから成る半導体パッケージにおいて、前記外
部リード端子は絶縁基体の−Ｅ面部から側面部を介して
底面部に達するまで延長されて訃り、かつ該外部リード
端子と絶縁基体の少なくとも側面との間に間隙が形成さ
れていることを特徴とするものである。The present invention provides a semiconductor package comprising an insulating base, an insulating container made of an inorganic material, and external lead terminals for connecting a semiconductor element housed in the container to an external circuit, wherein the external lead terminals extend from the -E surface of the insulating base. The external lead terminal is extended through the side surface to reach the bottom surface, and a gap is formed between the external lead terminal and at least the side surface of the insulating base.
以下、本発明を第２図に示す実施例に基づき詳細に説明
する。Hereinafter, the present invention will be explained in detail based on the embodiment shown in FIG.
尚、図中、従来品と同一個所には同一符号が付しである
。In the figure, the same parts as in the conventional product are given the same reference numerals.
第２図は本発明の半導体パッケージをガラス封止形半導
体パッケージに適用した実施例を示し、ｌはセラミック
、ガラス等の電気絶縁材料から成る絶縁基体であり、２
は同じく電気絶縁材料から成る蓋体である。この絶縁基
体１と蓋体２とで絶縁容器１０が形成される。FIG. 2 shows an embodiment in which the semiconductor package of the present invention is applied to a glass-sealed semiconductor package, where l is an insulating base made of an electrically insulating material such as ceramic or glass;
is a lid body also made of electrically insulating material. The insulating base 1 and the lid 2 form an insulating container 10.
４が半田等のロウ材を介し取着固定されている。4 is attached and fixed via a brazing material such as solder.
また前記基体ｌにはその上面外周部に導電性材料、例え
ば銅（Ｃｕ）、コバーｉｖ （Ｆｅ −Ｎｉ −Ｃｏ
）等の金属から成る外部リード端子３１がガラスを介し
取着されている。この外部リード端子３１は半導体素子
４の各電極がワイヤ６を介し電気的に接続されておシ、
該外部リード端子３１を外部回路に接続することにより
半導体素子４が外部回路と接続されることになる。In addition, the base 1 has a conductive material on the outer periphery of its upper surface, such as copper (Cu), copper (Fe-Ni-Co), etc.
An external lead terminal 31 made of metal such as ) is attached through glass. Each electrode of the semiconductor element 4 is electrically connected to the external lead terminal 31 via a wire 6.
By connecting the external lead terminals 31 to an external circuit, the semiconductor element 4 is connected to the external circuit.
また前記外部リード端子３１は絶縁基体１の上面部から
側面部を介して底面部に達するまで延長されてお９、か
つ該外部リード端子３１の基体１側面部及び底面部に位
置する部位には基体ｌと一定の間隙７が形成されている
。Further, the external lead terminal 31 extends from the top surface of the insulating base 1 through the side surface until reaching the bottom surface 9, and the portions of the external lead terminal 31 located on the side surface and bottom surface of the base 1 are A constant gap 7 is formed with the base 1.
この間隙７は外部リード端子３１の基体１底而部に位置
する部位３１ａを揺動自在とし、半導体パッケージを外
部回路基板５上に半田付けする場合、外部回路基板５上
の導電部５ａが半田溶融の熱によって位置変動を生じた
としても、該導電部５ａの位置変動に対応させて外部リ
ード端子３１の底内部３１ａを揺動させ、常に外部リー
ド端子３１の底面部３１ａを導電部５ａＫ当接させるこ
とができる。This gap 7 allows a portion 31a of the external lead terminal 31 located at the bottom of the base 1 to swing freely, so that when the semiconductor package is soldered onto the external circuit board 5, the conductive portion 5a on the external circuit board 5 is Even if a positional change occurs due to the heat of melting, the bottom interior 31a of the external lead terminal 31 is swung in response to the positional change of the conductive part 5a, and the bottom part 31a of the external lead terminal 31 is always aligned with the conductive part 5aK. can be brought into contact with
前記絶縁基体１の上部には蓋体２がガラスから成る封止
部材９により取着されており、これＫより絶縁容器１０
の内部が完全に気密に封止される３かくして本発明の半
導体パッケージによれば外部リード端子が絶縁基体の上
面部から側面部を介して底面部に達するまで延長され、
かつ絶縁基体の少なくとも側面との間に間隙を形成して
いることから基体底面部に位置する部位が揺動自在とな
り、半導体パッケージを外部回路基板上に取着する場合
、該外部回路基板上の導電部の位置が変動したとしても
外部リード端子を導電部に常に当接させることができ、
半導体パッケージの外部回路基板への取着が確実で、該
半導体パッケージ内に収納した半導体素子も確実に外部
回路に接続できる。A lid 2 is attached to the upper part of the insulating base 1 by a sealing member 9 made of glass, and from this K, an insulating container 10 is attached.
3.Thus, according to the semiconductor package of the present invention, the external lead terminal extends from the top surface of the insulating base through the side surface until it reaches the bottom surface.
In addition, since a gap is formed between at least the side surface of the insulating substrate, the portion located on the bottom surface of the substrate can swing freely, and when the semiconductor package is mounted on an external circuit board, the portion on the external circuit board Even if the position of the conductive part changes, the external lead terminal can always be in contact with the conductive part,
The semiconductor package can be reliably attached to the external circuit board, and the semiconductor element housed within the semiconductor package can also be reliably connected to the external circuit.
また半導体パッケージの絶縁基体底面部には厚肉の外部
リード端子が必要に応じ基体底面と間隙をもって配され
ることから、半導体パッケージを外部回路基板上に取着
した場合、両者間には一定の大きさの隙間が形成される
こととなり該隙間に入り込んだ汚物は洗浄により完全に
除去することができる。したがって本発明の半導体パッ
ケージでは、汚物によって半導体パッケージのリード端
子間が短絡することは一切なく、半導体装置として常に
正常に作動させることができ、極めて有用である。In addition, thick external lead terminals are placed on the bottom of the insulating base of the semiconductor package with a gap between them and the bottom of the base as necessary, so when the semiconductor package is mounted on an external circuit board, there is a certain gap between the two. A gap of this size is formed, and dirt that has entered the gap can be completely removed by washing. Therefore, in the semiconductor package of the present invention, there is no short circuit between the lead terminals of the semiconductor package due to dirt, and the semiconductor package can always operate normally as a semiconductor device, which is extremely useful.
尚本発明は上述の実施例に限定されるものではなく本発
明の要旨を逸脱しない範囲であれば種々の変更は可能で
ある。It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.
第１図は従来の半導体パッケージの断面図、第２図は本
発明の一実施例を示す断面図である。
１・・・絶縁基体、２・・・蓋体、３１・・・外部゛リ
ード端子、７・・・間隙
第１図
第２図
２０ｒFIG. 1 is a sectional view of a conventional semiconductor package, and FIG. 2 is a sectional view showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating base body, 2... Lid body, 31... External lead terminal, 7... Gap Fig. 1 Fig. 2 20r
Claims (1)
される半導体素子を外部回路に接続する外部リード端子
とから成る半導体パッケージにおいて、前記外部リード
端子は絶縁基体の上面部から側面部を介して底面部に達
するまで延畏されておシ、かつ該外部リード端子と絶縁
基体の少なくとも側面との間に間隙が形成されているこ
とを特徴とする半導体パッケージ。In a semiconductor package consisting of an insulating container consisting of an insulating base and a lid, and external lead terminals for connecting a semiconductor element housed in the container to an external circuit, the external lead terminals extend from the top surface to the side surface of the insulating base. What is claimed is: 1. A semiconductor package, characterized in that the external lead terminal is extended until it reaches a bottom surface through the external lead terminal, and a gap is formed between the external lead terminal and at least a side surface of the insulating base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58004995A JPS59129448A (en) | 1983-01-14 | 1983-01-14 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58004995A JPS59129448A (en) | 1983-01-14 | 1983-01-14 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59129448A true JPS59129448A (en) | 1984-07-25 |
Family
ID=11599174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58004995A Pending JPS59129448A (en) | 1983-01-14 | 1983-01-14 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59129448A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61220447A (en) * | 1985-03-27 | 1986-09-30 | Hitachi Ltd | Semiconductor package |
| US5952717A (en) * | 1994-12-29 | 1999-09-14 | Sony Corporation | Semiconductor device and method for producing the same |
-
1983
- 1983-01-14 JP JP58004995A patent/JPS59129448A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61220447A (en) * | 1985-03-27 | 1986-09-30 | Hitachi Ltd | Semiconductor package |
| US5952717A (en) * | 1994-12-29 | 1999-09-14 | Sony Corporation | Semiconductor device and method for producing the same |
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