JPS6332264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic semiconductor chip carrier in a package with low electrical and thermal resistance.

In typical ceramic packages for semiconductor devices, such as those best known in the prior art, the electrical path from the semiconductor chip to the terminals on the outer periphery of the package is a conductor printed and baked using molybdenum or tungsten paste. It is made of. This type of electrical path is used because it closely matches the coefficient of thermal expansion of the ceramic material and does not decompose under the high temperatures required to bake the ceramic material. When creating an electric circuit in this way, the cross section of the material of the electric path becomes extremely small. The material of this electrical path itself has a relatively low conductivity, resulting in a relatively high electrical resistance of this electrical path, in the region of 125 milliohms. These prior art devices also
Thermal resistance is also relatively high, making it difficult to remove the heat generated in the semiconductor chips and electrical circuitry within the package. With this kind of semiconductor package,
It would be desirable to create a semiconductor package with relatively low thermal and electrical resistance that holds a semiconductor chip in a hermetically sealed condition.

In accordance with the present invention, it is possible to provide a package for advanced large scale integrated circuit (LSI) and very large scale integrated circuit (VLSI) semiconductor devices, etc., which has lower electrical and thermal resistance than prior art devices. can. Instead of the electrical paths of prior art ceramic semiconductor chip carriers, in the present invention the electrical paths are made of copper or a metal with copper on its surface or an alloy with copper on its surface.
This electrical path is described in U.S. Patent No. 3,744,120 [Burgess
], No. 3766634 [Babcock et al.], No. 3854892 [Burgess et al.], No. 3911553 [Burgess et al.], No.
No. 3,994,430 [Cusano et al.] and No. 4,129,243 [Cusano et al.]. Following the methods described in these patents,
The metal component is bonded directly to the ceramic material at elevated temperature in a controlled reactive atmosphere without the need for non-electroplating, vacuum deposition or intermediate metals. In this method, a metal component, such as copper or a metal with copper on its surface, is placed in contact with an insulating substrate such as alumina, beryllia, or other ceramic, and then the metal component and insulating substrate are placed at a temperature slightly lower than the melting point of the metal. Heat at temperature. Heating under a reactive atmosphere, such as an oxidizing atmosphere, for a sufficient period of time creates a copper-copper oxide eutectic which, when cooled, bonds the copper to the insulating substrate. Using this method, an electrical path similar to the conventional one with an electrical resistance of about 5 milliohms is obtained, which reduces the electrical resistance by a factor of about 25. Additionally, the method of attaching circuits to ceramic substrates as described in the patent allows heat sinks to be attached to windows in the ceramic substrate, allowing integrated circuit chips to be attached by brazing, soldering, glass or polymer bonding. It can be directly bonded to the heat sink by, for example, a heat sink, thereby avoiding the thermal resistance of ceramic.

In order to match the thermal expansion coefficients of the semiconductor chip and the heat sink, the heat sink is made of an alloy whose coefficient of thermal expansion matches that of silicon, or a metal such as molybdenum coated with copper. Alternatively, an intermediate metal or ceramic spacer may be used between the semiconductor chip and the heat sink. These methods allow semiconductor devices, especially LSI and
We can provide packages for VLSI.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an exploded view of a ceramic chip carrier package which is an embodiment of the present invention. As shown in FIG. 1, the ceramic chip carrier package consists of a ceramic substrate 1 having a semiconductor chip and a lead frame 3 bonded to the bottom surface of the substrate.
Contains. The lead frame 3 has conductive terminals (terminals 4) extending beyond the ceramic substrate 1 in correspondence with pads on the semiconductor chip. An insulating frame (plastic frame 5) is arranged along the outer edge of the ceramic substrate. This insulating frame (plastic frame) is fixed to a ceramic substrate 1 and a lead frame 3.

2 and 3 show the members shown in FIG. 1 in an assembled state. The lead frame 3 is made of copper or a metal with copper on its surface and is bonded to the ceramic substrate 1 in the manner described above. The terminals 4 of the lead frame 3 are bent and run along the outer surface of the plastic frame 5, extending around the bottom of the plastic frame and into a groove 7 in the plastic frame 5. The terminal portion 4 extending beyond the ceramic substrate 1 is adapted to be easily bent and serves as a contact point with the element to be coupled. The coupling elements are sockets or printed circuit boards that contact the terminals along the sides of the plastic frame 5 or below the plastic frame 5 at the bends 6.

As a result, even if the circuit board moves relative to the ceramic member due to, for example, a difference in coefficient of thermal expansion, this movement will not cause the problem of disconnection at the connection point, and a sliding contact between the connected elements can be achieved. It becomes possible to have both.

Semiconductor chip 9 is bonded to ceramic substrate 1 by any suitable standard adhesive 11 well known in the art. Pads 13 on semiconductor chip 9 are connected to predetermined leads on lead frame 3 by suitable wires 15. The semiconductor chip 9 is hermetically sealed in the ceramic cap 17 using a glass-filled sealing compound 19. The ceramic cap 17 is sealed to the lead frame 3 and the ceramic substrate 1 by a glass-filled sealing compound 19. This ceramic cap 17 constitutes an airtight sealing means. A pouring filler material 21 is placed between the plastic frame 5 and the ceramic cap 17. The pour filler is made of epoxy, polyurethane or other material that acts as a filler between the plastic frame 5 and the ceramic cap 17. This filling material 21
is used because the ceramic cap 17 is not always placed in the correct position during manufacturing. A standard molded product is used for the ceramic substrate 1. The lead frame 3 is made of copper whose coefficient of thermal expansion matches that of ceramic, or of metal having copper on its surface. Copper is very flexible, bends easily, and has little strength, so the plastic frame 5
The terminal 4 can be formed according to the shape of the figure. This allows the final package to be fitted into a suitable socket, such as that shown in U.S. Pat. It is also possible to fix it.

Although the invention has been described with respect to specific preferred embodiments, many variations and modifications thereof will become readily apparent to those skilled in the art. Therefore, the scope of the claims of the present patent application should be interpreted as broadly as possible to include such modifications and changes in light of the prior art.

[Brief explanation of the drawing]

FIG. 1 is an exploded view showing a ceramic semiconductor package according to an embodiment of the present invention, FIG. 2 is a perspective view showing a package formed by assembling the members shown in FIG. 1, and FIG. FIG. 3 is a cross-sectional view of the package taken along arrow 3-3. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 3... Lead frame, 4... Conductive terminal (terminal), 5... Insulating frame (plastic frame), 9... Semiconductor chip, 15...
... wire, 17 ... hermetic sealing means (ceramic cap).

Claims (1)

[Scope of Claims] 1 (a) a ceramic substrate; (b) a lead frame having copper on the surface and directly bonded to the surface of the substrate; (c) a lead frame fixed to the lead frame and the substrate, an insulating frame located at an outer edge; (d) a conductive terminal integral with the lead frame extending beyond the substrate and along the insulating frame and perpendicular to the surface of the substrate; (e) a conductive terminal integral with the lead frame; a semiconductor chip adhered to a substrate; (f) a wire connecting the chip to a predetermined lead on the lead frame; (g) a semiconductor chip adhered to the substrate and connecting the chip, the lead wire and the wire therein; A semiconductor chip carrier comprising an airtight sealing means. 2. The carrier of claim 1, wherein said substrate is made of a composition selected from the group consisting of alumina and beryllia. 3. The carrier of claim 1, wherein the terminal is adapted to be easily bent.