JPH041501B2 - - Google Patents

Info

Publication number
JPH041501B2
JPH041501B2 JP57042179A JP4217982A JPH041501B2 JP H041501 B2 JPH041501 B2 JP H041501B2 JP 57042179 A JP57042179 A JP 57042179A JP 4217982 A JP4217982 A JP 4217982A JP H041501 B2 JPH041501 B2 JP H041501B2
Authority
JP
Japan
Prior art keywords
conductive pattern
semiconductor element
semiconductor device
frame
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57042179A
Other languages
Japanese (ja)
Other versions
JPS58159355A (en
Inventor
Eiji Hagimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4217982A priority Critical patent/JPS58159355A/en
Publication of JPS58159355A publication Critical patent/JPS58159355A/en
Publication of JPH041501B2 publication Critical patent/JPH041501B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法にかかり、とく
に絶縁基体上に導電性のパターンを設けた基板に
半導体素子を搭載し組立てる方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of mounting and assembling a semiconductor element on a substrate having a conductive pattern on an insulating substrate.

従来、半導体装置用パツケージには、あらかじ
め外部回路との電気的結合を計るため外部リード
をあらかじめ設けておくことが便宜とされてい
た。それら、外部リードの諸寸法はテユアルイン
ライン形式(以下、DIP形式と称す。)で代表さ
れる様に2.54mmのピツチで、例えば15.24mm(600
ミル)の例をなす様規格化され、互換性、汎用性
を確保している。
Conventionally, it has been considered convenient to provide a package for a semiconductor device with external leads in advance in order to measure the electrical connection with an external circuit. The dimensions of these external leads are 2.54 mm pitch, as represented by dual in-line type (hereinafter referred to as DIP type), and for example, 15.24 mm (600 mm).
It has been standardized to ensure compatibility and versatility.

しかし、近年電子機器の小型化、軽量化、薄形
化の要求が高まり、その機器に使用される回路部
品、例えば抵抗、コンデンサー、トランジスター
等の部品においては、外部リードを有さぬ小型の
リードレスタイプのチツプ部品が多用されるよう
になつてきている。半導体集積回路部品において
も同様であり、小型のリードレスタイプのいわゆ
るチツプキヤリアーが使われる様になつてきてい
る。これは、プリント基板への実装形態を同じに
することによりそれらのリードレスタイプのチツ
プ部品を溶融半田を用いて簡単に実装できるから
である。したがつて、実装工数の低減に大きく貢
献することができ、特に外部リードを要しない。
薄形化を要求される。時計、卓上電子計算器等の
分野では、大規模に採用されている。
However, in recent years there has been an increasing demand for smaller, lighter, and thinner electronic devices, and circuit components used in these devices, such as resistors, capacitors, and transistors, have become smaller, with no external leads. Less type chip parts are increasingly being used. The same holds true for semiconductor integrated circuit components, and small leadless type so-called chip carriers have come into use. This is because these leadless type chip components can be easily mounted using molten solder by making the mounting form on the printed circuit board the same. Therefore, it can greatly contribute to reducing the number of mounting steps, and no external lead is required.
Requires thinner design. It has been widely adopted in fields such as watches and desktop electronic calculators.

これらの分野では、半導体装置用パツケージと
して、絶縁基体そのものがその構成部品として用
いられ、いわゆるチツプオンボードと称される半
導体装置を構成する。チツプオンボード形式で
は、その用途が明確かつ限定されており、リード
レスタイプでも十分使用に耐えるものであるが、
これをそのまま一般の半導体装置用の形式とは採
用し難い。なぜなら、小型化、薄形化の為に汎用
性、互換性を犠牲にしたからである。前記DIP形
式の如く、規格化された外部リードを有する半導
体装置の有用性はその需要量から無視できないの
である。
In these fields, the insulating substrate itself is used as a component of a package for a semiconductor device, forming a so-called chip-on-board semiconductor device. Chip-on-board formats have clear and limited uses, and even leadless types can be used satisfactorily.
It is difficult to adopt this format as it is for general semiconductor devices. This is because versatility and compatibility were sacrificed in order to become smaller and thinner. The usefulness of semiconductor devices having standardized external leads, such as the above-mentioned DIP type, cannot be ignored due to the amount of semiconductor devices in demand.

本発明は前記リードレスタイプの半導体装置の
利点を活かしつつ、かつ、それが汎用性、互換性
をも持たしめる半導体装置の製造方法を提供する
ものである。
The present invention provides a method for manufacturing a semiconductor device that takes advantage of the advantages of the leadless type semiconductor device and also provides versatility and compatibility.

本発明は、導体パターンを有する絶縁基体上に
半導体素子を搭載し組立てる半導体装置の製造方
法において、矩形形状で、一主面に導電パターン
を有し、中央部に前記一主面から他の主面に向う
凹部が形成され、前記凹部の外側に前記両主面を
貫通する貫通孔が形成された絶縁基体と、前記絶
縁基体の相対向する両側縁の一部に接続される接
触部と、前記接触部を介して前記絶縁基体を複数
個同一平面上で同じ向きに所定間隔をもつて一列
に連結する一対のフレームとが合成樹脂積層板に
より一体的に形成されたフレーム付き基板を設
け、前記フレーム付き基板の前記凹部に半導体素
子をマウントし半導体素子と前記導電パターンと
を電気的に接続する工程と、次に、前記フレーム
付き基板の前記貫通孔を除いた前記半導体素子及
び前記半導体素子と導電パターンとの接続部を樹
脂封止する工程と、しかる後に、前記フレーム付
き基板の前記貫通孔に外部リードを挿入し、ろう
材を介して前記導電パターンと電気的に接続する
工程とを含むことを特徴とする。この様にするこ
とにより、リードレスタイプの半導体装置組立の
容易性を維持し、かつ汎用性を確保し得る。以
下、本発明を実施例を用いて詳細に説明する。
The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element is mounted and assembled on an insulating substrate having a conductive pattern, which has a rectangular shape, has a conductive pattern on one main surface, and has a conductive pattern formed on one main surface in the center. an insulating base in which a recess facing the surface is formed and a through hole penetrating both main surfaces is formed on the outside of the recess, and a contact part connected to a part of opposing both side edges of the insulating base; providing a frame-equipped substrate integrally formed with a synthetic resin laminate and a pair of frames connecting a plurality of the insulating substrates in a row on the same plane with a predetermined interval in the same direction via the contact portion; a step of mounting a semiconductor element in the recess of the frame-equipped substrate and electrically connecting the semiconductor element and the conductive pattern, and then the semiconductor element and the semiconductor element except for the through-hole of the frame-equipped substrate. and a step of resin-sealing a connection portion between the conductive pattern and the conductive pattern, and then a step of inserting an external lead into the through hole of the frame-equipped substrate and electrically connecting with the conductive pattern via a brazing material. It is characterized by containing. By doing so, ease of assembling a leadless type semiconductor device can be maintained and versatility can be ensured. Hereinafter, the present invention will be explained in detail using Examples.

第1図乃至第2図は本発明の実施例に係る製造
方法によつて製造された半導体装置を示す断面図
である。
1 and 2 are cross-sectional views showing a semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention.

ガラス繊維を含有するエポキシ樹脂基板等を絶
縁基体とする場合の製造方法について説明する。
A manufacturing method using an epoxy resin substrate containing glass fiber as an insulating substrate will be described.

絶縁基体1には、紙フエノール、ガラスエポキ
シ、ガラスポリイミド、ガラストリアジン等の合
成樹脂積層板を用いる。かかる基体の表裏面に
Cu箔を接着し、所要の孔加工、活性化処理Cuメ
ツキの工程を順次経て、必要に応じてスルーホー
ルメツキを施した後、フオト・エツチングなどの
公知の手段によつて不要部分のCu箔部分を除去
する。また、必要部分にはその後Auメツキを施
してもよい。この様にして導電パターン2が形成
される。これらは通常1個1個の個片にすること
なく、多連としておくことが、後の組立工程にお
ける取扱上有利であり、量産性を向上させる。次
に半導体素子3を熱硬化性の導電性ペースト、例
えば銀ペーストをスクリーン印刷法や、デイスペ
ンサーによつて塗布した層4の上に搭載する。し
かる後に基体を加熱すればペーストは硬化し半導
体素子が固着されることになる。導電性ペースト
のほか、絶縁基体側表面が金属化されていれば
Sn―Pb系、Au―Si,Au―Sn等の低融点ロー材
を用いることもできる。この点は、従来の半導体
装置のマウント法と同様である。
As the insulating substrate 1, a laminate of synthetic resin such as paper phenol, glass epoxy, glass polyimide, glass triazine, etc. is used. on the front and back surfaces of such a substrate.
After bonding the Cu foil, passing through the necessary hole processing and activation Cu plating steps, and applying through-hole plating as necessary, remove the unnecessary portions of the Cu foil by known means such as photo etching. remove parts. Further, necessary portions may be plated with Au afterwards. In this way, conductive pattern 2 is formed. Usually, these are not made into individual pieces, but are made into multiple pieces, which is advantageous in terms of handling in the subsequent assembly process, and improves mass productivity. Next, the semiconductor element 3 is mounted on the layer 4 on which a thermosetting conductive paste, for example a silver paste, is applied by screen printing or a dispenser. If the substrate is then heated, the paste will harden and the semiconductor element will be fixed. In addition to conductive paste, if the surface of the insulating base is metallized,
Low melting point brazing materials such as Sn--Pb, Au--Si, and Au--Sn can also be used. This point is similar to the conventional mounting method for semiconductor devices.

次に、半導体素子3と絶縁基体上の導電パター
ン2とを電気的に接続する。本実施例ではワイヤ
ーボンデイング法を例示した。ワイヤーとしては
Au,Alの種類を問わない。
Next, the semiconductor element 3 and the conductive pattern 2 on the insulating substrate are electrically connected. In this example, a wire bonding method was exemplified. As a wire
Regardless of the type of Au or Al.

次に、樹脂枠5を接着し、その内側キヤビテイ
部に、熱硬化性樹脂6を充填せしめる。この樹脂
枠はなくてもよく、熱硬化性樹脂が必要以上に流
れ出るのを防止できれば足りる。熱硬化性樹脂と
してはシリコン系、エポキシ系のものが耐湿性、
耐熱性の点ですぐれている。樹脂材料が熱硬化す
れば半導体装置として一定の形態を有しており、
このままでも製品とし得る。以上の工程は、第5
図に示すフレーム13を介して連結させておき、
連として処理することができ、これは従来の樹脂
封止型半導体装置の製造法に類似し、同様の組立
法を適用し得るので、組立工数はかなり低くする
ことができ、かつ大量生産に適している。
Next, the resin frame 5 is bonded and its inner cavity is filled with thermosetting resin 6. This resin frame is not necessary, and it is sufficient to prevent the thermosetting resin from flowing out more than necessary. Silicon-based and epoxy-based thermosetting resins are moisture resistant,
It has excellent heat resistance. Once the resin material is thermoset, it has a certain shape as a semiconductor device,
It can be used as a product as is. The above process is the fifth
Connected via the frame 13 shown in the figure,
This is similar to the manufacturing method of conventional resin-encapsulated semiconductor devices, and the same assembly method can be applied, so the assembly man-hours can be considerably reduced and it is suitable for mass production. ing.

連として処理してあれば、これを個々の部品と
して個片とする工程を付加するのみでリードレス
タイプの半導体装置の製品とすることができる。
次に、絶縁基体上に設けた外部接続端子部分に外
部リードとして、コバールやFe―Ni合金にAuメ
ツキ、Snメツキを施したもの8を低融点ロー材
7で接着する。第1図乃至第2図の実施例におい
ては、絶縁基体に貫通孔を設けて、外部リード8
を挿入した場合を例示している。貫通孔を設け
ず、導電性のパターン上に低融点ロー材を介して
接続してよいことは勿論である。
If they are processed as a series, a leadless type semiconductor device product can be obtained by simply adding a step of cutting them into individual parts.
Next, an external lead 8 made of Kovar or Fe--Ni alloy plated with Au or Sn is bonded to the external connection terminal portion provided on the insulating base using a low-melting brazing material 7. In the embodiment shown in FIGS. 1 and 2, a through hole is provided in the insulating base and the external lead 8 is
This example shows the case where . Of course, the connection may be made via a low melting brazing material on the conductive pattern without providing a through hole.

この外部リードの取付工程は、個片ごとに処理
してもよいが、連として処理する方が便宜であ
る。半導体装置としての電気的特性検査において
も連として処理することが可能で、より量産性を
高らしめるからである。この様に本発明に係る半
導体装置の製造方法においてはフレーム13によ
つて連を構成した部材を取扱う場合、最も効果の
あるものである。
This step of attaching the external leads may be carried out individually, but it is more convenient to carry out the process as a series. This is because it is possible to perform continuous processing even in electrical characteristic testing of semiconductor devices, which further improves mass productivity. As described above, the method of manufacturing a semiconductor device according to the present invention is most effective when dealing with members connected by the frame 13.

即ち、あらかじめ外部リードを絶縁基体に取付
けておけば、連としての処理が複雑になりすぎ大
量生産時の工数低減が図れないのである。この
点、42合金等の金属導体を基体とする樹脂封止型
半導体装置が樹脂封止後、外部リードとなるべき
金属導体を残して、折曲げるなどの加工を施すこ
とができるのと大きく相違する。これは基体が絶
縁材料から構成されており、導電体が外力に耐え
られる程の機械的強度を有していない為である。
またフレーム13を有しているところから外部リ
ードの導出は絶縁基体の側面からではなく、実施
例において例示した如く、絶縁基体に対しほぼ直
角方向に導出することが有利である。外部リード
の自動挿入機が利用できるからである。
That is, if the external leads are attached to the insulating base in advance, the process of assembling them becomes too complicated and it is not possible to reduce the number of man-hours during mass production. This point is significantly different from resin-sealed semiconductor devices, which have a metal conductor such as 42 alloy as a base, which can be processed by bending, leaving the metal conductor that will become the external lead after resin sealing. do. This is because the base is made of an insulating material and the conductor does not have enough mechanical strength to withstand external forces.
Furthermore, it is advantageous for the external leads to be led out from the frame 13 not from the side surface of the insulating base, but in a direction substantially perpendicular to the insulating base, as exemplified in the embodiment. This is because an automatic external lead insertion machine can be used.

第5図において、フレーム13の導電パターン
を有する電気絶縁基体1が複数個連結している。
すなわちフレーム状13との接触部を除いて打ち
抜き又はルーター加工等により各電気絶縁基体の
個片が切断しやすくなるように囲りを取り除いて
ある。
In FIG. 5, a plurality of electrically insulating substrates 1 having conductive patterns of frames 13 are connected.
That is, except for the contact portion with the frame 13, the surrounding area is removed by punching or router processing to facilitate cutting into individual pieces of each electrically insulating substrate.

次に絶縁基体1′としてセラミツクスを導電パ
ターン2′としてW.Mo―Mn等の高融点金属層を
用いた場合について説明する。これは参考例にお
ける第3図において図示するもので所定のメタラ
イズパターンをスクリーン印刷したグリーンシー
トを熱と圧力を利用して傾斜部を有する如く、キ
ヤビテイ9を設けて焼成する。メタライズパター
ンの所定の場所には必要に応じ、Niメツキ、Au
メツキを施す。この様にしてつくられた基板に、
通常の半導体装置と同様マウント、ボンデング
し、封止する。参考例においては、グレーズした
セラミツクリツド10を用いている。これで気密
封止型の半導体装置が完成するが、これにも封止
後外部リードを取付ける工程を付加する。この様
な工程によればマウントボンデイング封止の各作
業工程における基板の取扱いが容易で量産性を確
保することができるのみならず、外部リードを一
定の規格に基づいて並べれば、いわゆる通常のプ
ラグインタイプの半導体装置となり、気密封止型
故、高信頼であるにもかかわらず、非常に安価な
製造コストとなる。市場競争力において優位な地
位を持つことができることになる。
Next, a case will be described in which ceramic is used as the insulating base 1' and a high melting point metal layer such as W.Mo--Mn is used as the conductive pattern 2'. This is shown in FIG. 3 as a reference example, in which a green sheet having a predetermined metallized pattern screen-printed thereon is provided with a cavity 9 so as to have an inclined portion using heat and pressure, and then fired. Ni plating and Au plating are applied to designated areas of the metallized pattern as necessary.
Apply plating. On the board made in this way,
Mount, bond, and seal like normal semiconductor devices. In the reference example, a glazed ceramic glass 10 is used. This completes the hermetically sealed semiconductor device, but a step of attaching external leads after sealing is also added to this. Such a process not only makes it easy to handle the board in each process of mount bonding and sealing, ensuring mass production, but also allows for the production of so-called normal plugs by arranging the external leads according to a certain standard. Since it is an in-type semiconductor device and is hermetically sealed, it is highly reliable and has a very low manufacturing cost. This will allow them to have an advantageous position in terms of market competitiveness.

第4図は本発明に係る別の実施例で、封止用の
樹脂6で半導体素子3及びワイヤーを保護した
後、外部リード8を取付けた後、さらに別の樹脂
11をもつて全体を成形する工程により作られた
半導体装置を示す。この封止には、キヤステイン
グのみならずトランスフア成形も利用できる。こ
の様な構造にすれば半導体装置としての耐湿性を
向上させることができる。
FIG. 4 shows another embodiment of the present invention, in which the semiconductor element 3 and wires are protected with a sealing resin 6, external leads 8 are attached, and then the whole is molded with another resin 11. This figure shows a semiconductor device manufactured by the process. For this sealing, not only casting but also transfer molding can be used. With such a structure, the moisture resistance of the semiconductor device can be improved.

樹脂層6は必ずしも必要ではなく、省略するこ
とが可能である。即ち、基板1に半導体装置3を
マウントボンテングした後に、外部リードを取付
けることでもよいのである。構造が簡単になるの
みならず通常の樹脂封止型半導体装置で使用され
るトランスフア成形によつてさらに量産性を高め
ることができる。
The resin layer 6 is not necessarily necessary and can be omitted. That is, the external leads may be attached after mounting the semiconductor device 3 on the substrate 1. Not only is the structure simplified, but mass productivity can be further improved by using transfer molding, which is used in ordinary resin-sealed semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明に係る製造方法によつて製造
された、フエイスアツプタイプの半導体装置の断
面図である。外部リードはDIP形式でも格子状の
プラグインタイプであつてもよい。第2図は本発
明の実施例に係る製造方法によつて製造されたフ
エイスダウンタイプの半導体装置の断面図であ
る。外部リードの規格については第1図と同様で
ある。第3図は本発明に関連する技術に係る製造
方法によつて製造されたセラミツクスを絶縁基体
とする参考例の半導体装置の断面図である。第4
図は本発明に係る製造方法によつて製造されたト
ランスフア成形された半導体装置の断面図であ
る。第5図はフレームによつて連となつているこ
とを示す斜視図である。 ここに1,1′…絶縁基体、2,2′…導電パタ
ーン、3…半導体素子、4…マウント材、5…樹
脂枠、6…樹脂材料、7…外部リード接続用ロー
材、8…外部リード、9…キヤビテイ部、10…
気密封止用リツド、11…成形用樹脂材料、12
…金属板、13…フレームである。
FIG. 1 is a sectional view of a face-up type semiconductor device manufactured by the manufacturing method according to the present invention. The external leads may be in DIP format or grid plug-in type. FIG. 2 is a sectional view of a face-down type semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention. The specifications of the external leads are the same as in FIG. FIG. 3 is a cross-sectional view of a semiconductor device of a reference example whose insulating substrate is made of ceramics manufactured by a manufacturing method according to a technique related to the present invention. Fourth
The figure is a sectional view of a transfer-molded semiconductor device manufactured by the manufacturing method according to the present invention. FIG. 5 is a perspective view showing that they are connected by a frame. Here, 1, 1'... Insulating base, 2, 2'... Conductive pattern, 3... Semiconductor element, 4... Mounting material, 5... Resin frame, 6... Resin material, 7... Brazing material for external lead connection, 8... External Lead, 9...Cavity part, 10...
Hermetic sealing lid, 11... Resin material for molding, 12
...metal plate, 13...frame.

Claims (1)

【特許請求の範囲】 1 導体パターンを有する絶縁基体上に半導体素
子を搭載し組立てる半導体装置の製造方法におい
て、矩形形状で、一主面に導体パターンを有し、
中央部に前記一主面から他の主面に向う凹部が形
成され、前記凹部の外側に前記両主面を貫通する
貫通孔が形成された絶縁基体と、 前記絶縁基体の相対向する両側縁の一部に接続
される接触部と、 前記接触部を介して前記絶縁基体を複数個同一
平面上で同じ向きに所定間隔をもつて一列に連結
する一対のフレームとが合成樹脂積層板により一
体的に形成されたフレーム付き基板を設け、前記
フレーム付き基板の前記凹部に半導体素子をマウ
ントし半導体素子と前記導電パターンとを電気的
に接続する工程と、次に、前記フレーム付き基板
の前記貫通孔を除いた前記半導体素子及び前記半
導体素子と導電パターンとの接続部を樹脂封止す
る工程と、しかる後に、前記フレーム付き基板の
前記貫通孔に外部リードを挿入し、ろう材を介し
て前記導電パターンと電気的に接続する工程とを
含むことを特徴とする半導体装置の製造方法。
[Claims] 1. A method for manufacturing a semiconductor device in which a semiconductor element is mounted and assembled on an insulating substrate having a conductive pattern, which has a rectangular shape and has a conductive pattern on one main surface;
an insulating base having a recess extending from the one main surface to the other main surface in the center thereof and a through hole penetrating both the main faces outside the recess; and opposing opposite side edges of the insulating base. A contact portion connected to a part of the contact portion, and a pair of frames that connect a plurality of the insulating substrates in a row on the same plane with a predetermined interval in the same direction via the contact portion are integrated by a synthetic resin laminate. a step of mounting a semiconductor element in the recess of the frame-equipped substrate and electrically connecting the semiconductor element and the conductive pattern; A step of sealing the semiconductor element excluding the hole and the connecting portion between the semiconductor element and the conductive pattern with resin, and then inserting an external lead into the through hole of the frame-equipped substrate and inserting the external lead through the brazing material. A method for manufacturing a semiconductor device, the method comprising the step of electrically connecting a conductive pattern.
JP4217982A 1982-03-17 1982-03-17 Manufacture of semiconductor device Granted JPS58159355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4217982A JPS58159355A (en) 1982-03-17 1982-03-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4217982A JPS58159355A (en) 1982-03-17 1982-03-17 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58159355A JPS58159355A (en) 1983-09-21
JPH041501B2 true JPH041501B2 (en) 1992-01-13

Family

ID=12628757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4217982A Granted JPS58159355A (en) 1982-03-17 1982-03-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58159355A (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038842A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Semiconductor device
JPS6059756A (en) * 1983-09-12 1985-04-06 Ibiden Co Ltd Plug-in package and manufacture thereof
JPS6095943A (en) * 1983-10-31 1985-05-29 Ibiden Co Ltd Plug-in package and manufacture thereof
JPS6095944A (en) * 1983-10-31 1985-05-29 Ibiden Co Ltd Plug-in package and manufacture thereof
JPS60101998A (en) * 1983-11-07 1985-06-06 イビデン株式会社 Plug-in package and method of producing same
JPS60241244A (en) * 1984-05-16 1985-11-30 Hitachi Micro Comput Eng Ltd Semiconductor device, manufacture thereof, and implement to manufacture therefor
JPS6194359U (en) * 1984-11-27 1986-06-18
FR2575331B1 (en) * 1984-12-21 1987-06-05 Labo Electronique Physique HOUSING FOR ELECTRONIC COMPONENT
US4661192A (en) * 1985-08-22 1987-04-28 Motorola, Inc. Low cost integrated circuit bonding process
JPS62194655A (en) * 1985-11-20 1987-08-27 アンプ―アクゾ コーポレイション Electronic device connection package and manufacture of the same
JPS62248244A (en) * 1986-04-21 1987-10-29 Hitachi Cable Ltd Lead frame for pga
JPH0821672B2 (en) * 1987-07-04 1996-03-04 株式会社堀場製作所 Method for producing sheet-type electrode for measuring ion concentration
US5255430A (en) * 1992-10-08 1993-10-26 Atmel Corporation Method of assembling a module for a smart card
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5926618Y2 (en) * 1979-12-11 1984-08-02 パイオニア株式会社 Through-hole board

Also Published As

Publication number Publication date
JPS58159355A (en) 1983-09-21

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