JPH0773117B2 - Semiconductor package - di - Google Patents

Semiconductor package - di

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Publication number
JPH0773117B2
JPH0773117B2 JP61280225A JP28022586A JPH0773117B2 JP H0773117 B2 JPH0773117 B2 JP H0773117B2 JP 61280225 A JP61280225 A JP 61280225A JP 28022586 A JP28022586 A JP 28022586A JP H0773117 B2 JPH0773117 B2 JP H0773117B2
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Prior art keywords
stem
wiring
semiconductor chip
wiring board
end
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Expired - Fee Related
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JP61280225A
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JPS63133553A (en
Inventor
政道 進藤
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株式会社東芝
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Priority to JP61280225A priority Critical patent/JPH0773117B2/en
Publication of JPS63133553A publication Critical patent/JPS63133553A/en
Publication of JPH0773117B2 publication Critical patent/JPH0773117B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、特にLSIのように端子数が多ピンの外囲器に使用して最適な半導体パッケージに関する。 DETAILED DESCRIPTION OF THE INVENTION [OBJECT OF THE INVENTION] (INDUSTRIAL FIELD) The present invention relates particularly optimal semiconductor package using the number of terminals in the envelope of the multi-pin as LSI.

(従来の技術) ピン挿入型半導体パッケージとしては、その代表がDIP The (prior art) pin insertion type semiconductor package, the representative DIP
(デュアル・インライン・パッケージ)であるが、この Is a (dual in-line package), this
DIPではピン数に限度があり、せいぜい60ピン程度までが現実的であり、これ以上は一般に実現不能であった。 There is a limit to the number of pins in DIP, a realistic until most 60 pins about which more were generally unfeasible.
これ以上の多ピンに対応するためには、パッケージの下面から剣山状に多数のピンを突出させた、ピン挿入形の To accommodate more multi pin is protruded a large number of pins from the lower surface of the package to the pin holder shape, the pin insertion type of
PGA(ピン・グリッド・アレイ)が一般に用いられていた。 PGA (pin grid array) has been used generally.

このPGAには、セラミック基板にメタライズを施し、多層に積層して構成した、いわゆるセラミック形PGAや、 The PGA, metalized on the ceramic substrate, constructed by laminating a multilayer, or a so-called ceramic shaped PGA,
このセラミック形PGAの価格の低減をはかるため、この基板部分の配線をプリント基板に置換えた、いわゆるプラスチック形PGAがあった。 Order to reduce the price of the ceramic shaped PGA, replaced the wiring of the substrate portion on the printed circuit board, there is a so-called plastic type PGA.

(発明が解決しようとする問題点) しかしながら、上記セラミック形PGAはセラミック形積層パッケージであるため、一般に製造方法が比較的繁雑であるばかりでなく、かなり高価なものになってしまう。 (To be Solved by the Invention Problems) However, since the ceramic shaped PGA is a ceramic-type laminated package, generally well manufacturing process is relatively complicated, become fairly expensive. 更に配線として一般にタングステン等を主体とした材料を使用するためこの配線抵抗が高く、セラミックであるため容量が大きいばかりでなく、放熱性も中程度であった。 More generally in order to use the material mainly composed of tungsten or the like high wiring resistance as a wiring, not only a large capacity for a ceramic, was moderate heat radiation property.

また、プラスチック形PGAは、上記セラミック形PGAと比較して安価に製造することができるものの、半導体チップの実装の際の該チップの保護のために、有機物による樹脂封止(シール)を行う必要があるため、封止物から応力が加わってしまったり、また樹脂の特質から、原理的に外気との遮断が不完全となって完全な気密封止を行うことができないため、上記セラミック形PGAと比較すると信頼性に劣ってしまうばかりでなく、内部に実装できる半導体チップの大きさに限度があるといった問題点があった。 Also, plastic shaped PGA, although it can be manufactured at low cost as compared with the ceramic shaped PGA, for the protection of the chip during a semiconductor chip mounting, necessary to perform resin sealing (seal) by organic matter some reason, because or worse stress is applied from the sealing material, and from the nature of the resin, is cut off with the theoretically outside air can not be a complete airtight sealing becomes incomplete, the ceramic shaped PGA is not only would poor reliability when compared with, there is a problem that there is a limit to the size of the semiconductor chip can be mounted therein.

本発明は上記に鑑み、パッケージとしてのコストダウンを図るとともに、大型の半導体チップに対応することができ、しかも多ピン化を確保するとともに、特性を改善し、更に確実に気密封止できるものを提供することを目的としてなされたものでる。 In view of the above, while achieving the cost of a package may correspond to the large semiconductor chip, yet while securing the number of pins, to improve the properties, what further reliably be hermetically sealed out those was made for the purpose of providing.

〔発明の構成〕 [Configuration of the Invention

(問題点を解決するための手段) 本発明は上記目的を達成するため、内部に多数の穿孔を有する金属製のステムと、表面に所定形状に配線がパターニングされ前記穿孔に対応する位置にスルーホールが形成された前記ステムに上面に重合する配線基板と、前記配線の一端と内部の電極とが電気的に接続された半導体チップと、前記穿孔内に貫設され頭部を前記スルーホール内に挿通させ接合物質を介して前記配線の他端と電気的に接続されるとともに前記ステムの下方に突出されたリードピンと、前記配線基板及び半導体チップを覆い該配線基板及び半導体チップを気密封止した金属製のシェルとからなるものである。 Since the present invention (means for solving the problem) is to achieve the above object, through the interior and a metal stem having a plurality of perforations, lines in a predetermined shape on the surface is patterned corresponding to the puncturing positions a wiring substrate to polymerize the top surface to the stem hole is formed, the one end and the internal electrode wiring and the semiconductor chip that is electrically connected, said head being formed through the borehole the through hole wherein the lead pin that protrudes below the stem, hermetically sealing the wiring substrate and the semiconductor chip covers the wiring board and the semiconductor chip with the other end electrically connected to the wiring through the insertion is not bonded material it is made of a metal-made shell.

(作用) 而して、高価なセラミック形積層パッケージとすることを防止して、価格の低減を図るとともに、半導体チップ及び配線基板の確実な気密封止を確保し、しかも配線基板は従来のものをそのまま使用できるようにしたものである。 (Act) to Thus, it is possible to prevent an expensive ceramic shaped stack package, along with reduced cost, to ensure reliable hermetic sealing of the semiconductor chip and the wiring board, moreover wiring board of conventional the one in which was to be used as it is.

(実施例) 図面は本発明の一実施例を示すもので、鉄又は42アロイ等の鉄合金製で平板状のステム1の略中央には矩形状の開口1aが形成されているとともに、周囲には上下に連通した、下記のリードピン3を挿着するための直径1mm程度の穿孔1b,1b…が、図示では外周から三列にわたって多数穿設されて、更にこの周囲には段部から外方に延出する外周部1cが形成されている。 (Example) The drawings show one embodiment of the present invention, along with the approximate center of the flat plate-like stem 1 made of iron alloy such as iron or 42 alloy has a rectangular opening 1a is formed, around the communicating up and down, out of the perforations 1b having a diameter of about 1mm for inserting the lead pins 3 below, 1b ... it is, is drilled a number over three rows from the outer circumference in the illustrated further stepped portion for this ambient the outer peripheral portion 1c extending is formed towards.

上記ステム1の開口1a内には銅製等の放熱性の良い放熱部材2が封入固着されている。 The inside opening 1a of the stem 1 may heat radiating member 2 having the heat radiation of the copper or the like is sealed fixed. このように、放熱部材2 Thus, the heat radiating member 2
を配設し、この上面に下記のように半導体チップ5を載置することにより、熱伝導性の向上を図るようにすることができる。 It was provided by placing the semiconductor chip 5 as described below in the upper surface can be made to improve the thermal conductivity. また、上記ステム1の各穿孔1b内には夫々リードピン3が、下方に突出した状態でその上端においてガラス等の封止材4によって気密封止されて固着されている。 Also, in each perforation 1b of the stem 1 is respectively lead pins 3 are secured hermetically sealed by a sealing material 4 such as glass in its upper end so as to protrude downward.

上記放熱部材2の上面には半導体チップ5が載置され、 The upper surface of the heat radiating member 2 is the semiconductor chip 5 is placed,
半田付け等により固定されている。 It is fixed by soldering or the like. またステム1の上面には中間配線6,6…を配設し、所定の形状と特性が施された中間配線材としての配設基板7が重ね合せて備えられている。 Also on the upper surface of the stem 1 is disposed intermediate wire 6, 6 ..., distribution 設基 plate 7 as an intermediate wiring material of a predetermined shape and properties were subjected are provided with superposed. この配線基板7の大きさは上記ステム1よりも僅かに小さくて、このステム1の上面に配線基板7を載置した際に、この外方にステム1の外周部1cが突出して、ここに下記のシェル10の周囲が気密封止できるようになされている。 The size of the wiring board 7 is slightly smaller than the stem 1, when placing the circuit board 7 to the upper surface of the stem 1, the outward and the outer peripheral portion 1c projecting stem 1, where the periphery of the shell 10 of the following have been made so that it can be hermetically sealed.

なお、この配線基板7は、一般にガラスエポキシやポリイミド等の有機単層又は積層基板で構成されたものであるが、上記ステム1の材質の組合わせにより、アルミナやAlN等のセラミック基板を使用して構成することもできる。 Incidentally, the wiring board 7 is generally but those composed of organic single layer or multilayer substrate, such as glass epoxy or polyimide, by a combination of the material of the stem 1, the use of ceramic substrates such as alumina or AlN It can also be configured Te.

この配設基板7の上記ステム1に穿設した穿孔1b,1b… Perforation 1b bored into the stem 1 of the distribution 設基 plate 7, 1b ...
と対応する位置には,夫々上記中間配線の一端と電気的に接続したスルーホール7a,7a…が形成され、この各通孔7a内に各リードピン3の上端を夫々挿通させとともに、この上端面を半田付け等の接合物質8により接合することにより、この接合物質8を介して、各リードピン3と各中間配線6の一端とを電気的に接続するよう構成されている。 And the corresponding position, each said intermediate wiring electrically connected to one end and through holes 7a, 7a ... are formed, the upper end of each lead pin 3 with is respectively inserted into the respective through holes 7a, the upper surface the by joining by the joining material 8 such as soldering, through the bonding material 8, it is configured to electrically connect the lead pins 3 and one end of the intermediate wires 6.

また、上記半導体チップ5の電極としての各パッドと上記配線基板7の各中間配線6の他端とは夫々ボンディングワイヤ9により電気的に接続され、これによって、半導体チップ4の各パッドと上記各リードピン3とが、夫々電気的に接続するよう構成されている。 Further, the other end of each intermediate wire 6 of the pad and the wiring board 7 as an electrode of the semiconductor chip 5 are electrically connected by respective bonding wires 9, thereby, the pads and the respective semiconductor chips 4 and lead pins 3 are configured to connect each electrically.

更に、上記配線基板7の上面には、立上り部10aとこの立上り部10aから連続して外方に延出した水平部10bが備えられた、例えば金属製の蓋材としてのシェル10が被せられている。 Further, the upper surface of the wiring board 7, a horizontal portion 10b extending outwardly provided continuously with the rising portion 10a from the rising portion 10a, for example, the shell 10 as the metal of the lid is covered ing. そして、この立上り部10aの内面と上記配線基板7の周面とが当接し、更にこの水平部10bと上記ステム1の外周部1cとが重合し、ここが電気溶接等により気密封止されている。 Then, the rising portion 10a of the inner surface and the peripheral surface of the wiring substrate 7 abuts further polymerization and the outer peripheral portion 1c of the horizontal portion 10b and the stem 1, wherein the hermetically sealed by electrically welding there.

このようにして、上記従来のプラスチック形PGAでは、 In this manner, in the conventional plastic shaped PGA,
その特性上、不可能とされていた完全な気密封止を行っているのである。 Its characteristics on, we're doing a complete hermetic seal which has been considered to be impossible.

なお、このステム1とシェル10の気密封止は、シェル10 It should be noted that the hermetic sealing of the stem 1 and the shell 10, shell 10
がアルミナ等のセラミックで構成されていても、ステム1との線膨脹係数を合せることにより、ガラスによる気密封止で行うようにすることもできる。 There also be constituted by a ceramic such as alumina, by combining the linear expansion coefficients of the stem 1, it can also be performed in hermetically sealed by glass.

なお、このパッケージにおいては、外囲器が金属であるために、半導体チップ5を半田等の導電性のある材料で接続すると、半導体チップ5の裏面の電位が外囲器と同じになってしまう。 Incidentally, in this package, since the envelope is metal and connecting the semiconductor chip 5 with a conductive resistant material such as solder, the rear surface potential of the semiconductor chip 5 becomes the same as the envelope .

これを防止するため、半導体チップ5の固定に半導体の組立て工程で一般に使用されている絶縁性の有機物を使用したり、又はシェル10を封止した後、リードピン3を残してステム1及びシェル10の部分を有機樹脂でコーティングすることにより、半導体チップ5の裏面の電位との分離を行うようにすることができる。 To prevent this, or use generally insulating organic material used in the semiconductor assembly process for fixing the semiconductor chip 5, or after sealing the shell 10, the stem 1 and the shell 10, leaving the lead pins 3 the portion by coating with an organic resin, it is possible to perform separation of the back surface potential of the semiconductor chip 5.

〔発明の効果〕 〔Effect of the invention〕

本発明は上記のような構成であるので、セラミック形PG Since the present invention is a structure as described above, the ceramic-type PG
Aやプラシチック形PGAに比較して安価に製造することができるばかりでなく、確実に気密封止を行って、気密性の完全性を図ることができる。 Compared to A and Purashichikku shaped PGA not only can be manufactured at a low cost, reliably performing hermetic sealing, it is possible to integrity airtightness. しかも、セラミック形PG In addition, ceramic-type PG
Aとほぼ同等の大型パッケージへの適応性があるばかりでなく、セラミック形PGAよりやや劣ることがあるものの、プラスチック形PGAとほぼ同等の多ピン化に対応することができる。 A and not only substantially Adaptive to equivalent large package, although sometimes slightly inferior to the ceramic shaped PGA, may correspond to the number of pins of substantially equal to the plastic form PGA.

また、放熱特性を最良となし、しかも配線基板の基材にポリイミドやガラスエポキシ等を使用することにより、 The best and without thermal performance, yet by using the polyimide or glass epoxy or the like to the substrate of the wiring board,
電気容量の減少を図ることができる。 It is possible to decrease the capacitance.

更に、従来のセラミック形PGA、プラスチック形PGAは共に品種に応じてパッケージを起こさなくてはならなかったが、本発明によれば、リードピンの数が同じであれば配線基板を変えるだけこれに対応することができ、従って敏速、かつ安価にこの種のパッケージを提供することができるといった効果がある。 Moreover, conventional ceramic shaped PGA, a plastic shaped PGA had to undergo package according to both varieties, according to the present invention, corresponding to the number of lead pins changing the wiring substrate when the same it can be, therefore quickly and inexpensively is advantage of the ability to provide such a package.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

図面は本発明の一実施例を示し、第1図は一部を切断した斜視図、第2図は縦断面図である。 The drawings illustrate an embodiment of the present invention, a perspective view FIG. 1 is cut partially, FIG. 2 is a longitudinal sectional view. 1……ステム、3……リードピン、5……半導体チップ、6……中間配線、7……配線基板、8……接合物質、9……ボンディングワイヤ、10……シェル。 1 ...... stem, 3 ...... lead pin, 5 ...... semiconductor chip, 6 ...... intermediate wiring, 7 ...... wiring board, 8 ...... bonding material 9 ...... bonding wire, 10 ...... shell.

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】内部に多数の穿孔を有する金属製のステムと、表面に所定形状に配線がパターニングされ前記穿孔に対応する位置にスルーホールが形成された前記ステムに上面に重合する配線基板と、前記配線の一端と内部の電極とが電気的に接続された半導体チップと、前記穿孔内に貫設され頭部を前記スルーホール内に挿通させ接合物質を介して前記配線の他端と電気的に接続されるとともに前記ステムの下方に突出されたリードピンと、前記配線基板及び半導体チップを覆い該配線基板及び半導体チップを気密封止した金属製のシェルとからなることを特徴とする半導体パッケージ。 And 1. A metal stem having a multiplicity of perforations therein, and a wiring board which polymerize upper surface to the stem through hole is formed at a position corresponding to the wiring are patterned the perforations in a predetermined shape on the surface a semiconductor chip having one end and the inside of the electrode of the wiring is electrically connected, the electrical and the other end of the wire through the bonding material of the head is pierced in said piercing is inserted into the through hole semiconductor package characterized by comprising the lead pin that protrudes below the stem, the wiring substrate and the semiconductor chip covers the wiring board and the semiconductor chip hermetically sealed metallic shells together is connected .
JP61280225A 1986-11-25 1986-11-25 Semiconductor package - di Expired - Fee Related JPH0773117B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61280225A JPH0773117B2 (en) 1986-11-25 1986-11-25 Semiconductor package - di

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP61280225A JPH0773117B2 (en) 1986-11-25 1986-11-25 Semiconductor package - di
EP87114577A EP0272390A3 (en) 1986-11-25 1987-10-06 Packages for a semiconductor device
KR8713294A KR900007301B1 (en) 1986-11-25 1987-11-25 Semiconductor package

Publications (2)

Publication Number Publication Date
JPS63133553A JPS63133553A (en) 1988-06-06
JPH0773117B2 true JPH0773117B2 (en) 1995-08-02

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JP61280225A Expired - Fee Related JPH0773117B2 (en) 1986-11-25 1986-11-25 Semiconductor package - di

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EP (1) EP0272390A3 (en)
JP (1) JPH0773117B2 (en)
KR (1) KR900007301B1 (en)

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Publication number Priority date Publication date Assignee Title
JPH079953B2 (en) * 1988-04-13 1995-02-01 株式会社東芝 A method of manufacturing a semiconductor device
JPH0243756A (en) * 1988-08-03 1990-02-14 Toshiba Components Co Ltd Semiconductor device
US4916523A (en) * 1988-09-19 1990-04-10 Advanced Micro Devices, Inc. Electrical connections via unidirectional conductive elastomer for pin carrier outside lead bond
DE3923533A1 (en) * 1989-07-15 1991-01-24 Diehl Gmbh & Co Arrangement of an integrated circuit on a schaltungstraeger
US5103292A (en) * 1989-11-29 1992-04-07 Olin Corporation Metal pin grid array package
US5247423A (en) * 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
US5991156A (en) * 1993-12-20 1999-11-23 Stmicroelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
FR2793990B1 (en) * 1999-05-19 2001-07-27 Sagem Electronics housing plate and method of manufacturing such a housing
JP2005064157A (en) * 2003-08-08 2005-03-10 Alps Electric Co Ltd Electronic circuit module
DE10352705A1 (en) * 2003-11-12 2005-06-23 Diehl Bgt Defence Gmbh & Co. Kg Circuit arrangement, especially for use in space, has element, especially vacuum-tight housing on base element and at least one heat-generating component connected to housing to dissipate heat losses

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Publication number Priority date Publication date Assignee Title
US3662230A (en) * 1968-06-25 1972-05-09 Texas Instruments Inc A semiconductor interconnecting system using conductive patterns bonded to thin flexible insulating films
JPS5236824B2 (en) * 1973-10-15 1977-09-19
JPS5113611A (en) * 1974-07-19 1976-02-03 Asahi Chemical Ind Hiryobotono uchikomisochi
JPS6348062Y2 (en) * 1983-08-12 1988-12-12

Also Published As

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JPS63133553A (en) 1988-06-06
EP0272390A2 (en) 1988-06-29
EP0272390A3 (en) 1988-12-07
KR900007301B1 (en) 1990-10-08

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