JPH0773117B2 - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH0773117B2
JPH0773117B2 JP61280225A JP28022586A JPH0773117B2 JP H0773117 B2 JPH0773117 B2 JP H0773117B2 JP 61280225 A JP61280225 A JP 61280225A JP 28022586 A JP28022586 A JP 28022586A JP H0773117 B2 JPH0773117 B2 JP H0773117B2
Authority
JP
Japan
Prior art keywords
wiring
stem
semiconductor chip
wiring board
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61280225A
Other languages
Japanese (ja)
Other versions
JPS63133553A (en
Inventor
政道 進藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61280225A priority Critical patent/JPH0773117B2/en
Priority to EP87114577A priority patent/EP0272390A3/en
Priority to KR1019870013294A priority patent/KR900007301B1/en
Publication of JPS63133553A publication Critical patent/JPS63133553A/en
Publication of JPH0773117B2 publication Critical patent/JPH0773117B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、特にLSIのように端子数が多ピンの外囲器に
使用して最適な半導体パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to an optimum semiconductor package to be used for an envelope having a large number of terminals, such as an LSI.

（従来の技術） ピン挿入型半導体パッケージとしては、その代表がDIP
（デュアル・インライン・パッケージ）であるが、この
DIPではピン数に限度があり、せいぜい60ピン程度まで
が現実的であり、これ以上は一般に実現不能であった。
これ以上の多ピンに対応するためには、パッケージの下
面から剣山状に多数のピンを突出させた、ピン挿入形の
PGA（ピン・グリッド・アレイ）が一般に用いられてい
た。(Prior art) A typical pin-insertion type semiconductor package is DIP.
(Dual inline package)
With DIP, there is a limit to the number of pins, and up to about 60 pins is realistic, and it was generally impossible to achieve more than this.
In order to support more pins than this, a pin insertion type with a large number of pins protruding from the bottom surface of the package
PGA (pin grid array) was commonly used.

このPGAには、セラミック基板にメタライズを施し、多
層に積層して構成した、いわゆるセラミック形PGAや、
このセラミック形PGAの価格の低減をはかるため、この
基板部分の配線をプリント基板に置換えた、いわゆるプ
ラスチック形PGAがあった。This PGA is a so-called ceramic type PGA, which is made by metalizing a ceramic substrate and stacking it in multiple layers,
In order to reduce the price of this ceramic type PGA, there was a so-called plastic type PGA in which the wiring of this substrate part was replaced with a printed circuit board.

（発明が解決しようとする問題点） しかしながら、上記セラミック形PGAはセラミック形積
層パッケージであるため、一般に製造方法が比較的繁雑
であるばかりでなく、かなり高価なものになってしま
う。更に配線として一般にタングステン等を主体とした
材料を使用するためこの配線抵抗が高く、セラミックで
あるため容量が大きいばかりでなく、放熱性も中程度で
あった。(Problems to be Solved by the Invention) However, since the above-mentioned ceramic type PGA is a ceramic type laminated package, in general, the manufacturing method is not only relatively complicated but also considerably expensive. Further, since a material mainly containing tungsten or the like is generally used for the wiring, this wiring resistance is high, and since it is a ceramic, not only the capacity is large, but also the heat dissipation is medium.

また、プラスチック形PGAは、上記セラミック形PGAと比
較して安価に製造することができるものの、半導体チッ
プの実装の際の該チップの保護のために、有機物による
樹脂封止（シール）を行う必要があるため、封止物から
応力が加わってしまったり、また樹脂の特質から、原理
的に外気との遮断が不完全となって完全な気密封止を行
うことができないため、上記セラミック形PGAと比較す
ると信頼性に劣ってしまうばかりでなく、内部に実装で
きる半導体チップの大きさに限度があるといった問題点
があった。Further, although the plastic PGA can be manufactured at a lower cost than the ceramic PGA, it is necessary to perform resin sealing (sealing) with an organic substance in order to protect the semiconductor chip when mounting it. Therefore, stress will be applied from the sealed product, and due to the nature of the resin, in principle, the insulation from the outside air will be incomplete and it will not be possible to perform a complete hermetic seal. There is a problem that not only the reliability is inferior, but also the size of the semiconductor chip that can be mounted inside is limited as compared with the above.

本発明は上記に鑑み、パッケージとしてのコストダウン
を図るとともに、大型の半導体チップに対応することが
でき、しかも多ピン化を確保するとともに、特性を改善
し、更に確実に気密封止できるものを提供することを目
的としてなされたものでる。In view of the above, the present invention aims to reduce the cost as a package, to accommodate a large-sized semiconductor chip, and to secure a large number of pins, to improve the characteristics, and to further ensure airtight sealing. It was made for the purpose of providing.

〔発明の構成〕[Structure of Invention]

（問題点を解決するための手段） 本発明は上記目的を達成するため、内部に多数の穿孔を
有する金属製のステムと、表面に所定形状に配線がパタ
ーニングされ前記穿孔に対応する位置にスルーホールが
形成された前記ステムに上面に重合する配線基板と、前
記配線の一端と内部の電極とが電気的に接続された半導
体チップと、前記穿孔内に貫設され頭部を前記スルーホ
ール内に挿通させ接合物質を介して前記配線の他端と電
気的に接続されるとともに前記ステムの下方に突出され
たリードピンと、前記配線基板及び半導体チップを覆い
該配線基板及び半導体チップを気密封止した金属製のシ
ェルとからなるものである。(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention has a metal stem having a large number of holes inside, and a wiring is patterned in a predetermined shape on the surface, and a through hole is provided at a position corresponding to the holes. A wiring board that is superposed on the upper surface of the stem in which the hole is formed, a semiconductor chip in which one end of the wiring and an internal electrode are electrically connected, and a head that is provided in the through hole and has a head in the through hole. The wiring board and the semiconductor chip with the lead pin electrically connected to the other end of the wiring through a bonding substance and protruding below the stem and the wiring board and the semiconductor chip. It is made of a metal shell.

（作用） 而して、高価なセラミック形積層パッケージとすること
を防止して、価格の低減を図るとともに、半導体チップ
及び配線基板の確実な気密封止を確保し、しかも配線基
板は従来のものをそのまま使用できるようにしたもので
ある。(Operation) Therefore, it is possible to prevent the price from becoming an expensive ceramic type laminated package, to reduce the price, and to ensure the reliable hermetic sealing of the semiconductor chip and the wiring board. It can be used as it is.

（実施例） 図面は本発明の一実施例を示すもので、鉄又は42アロイ
等の鉄合金製で平板状のステム１の略中央には矩形状の
開口1aが形成されているとともに、周囲には上下に連通
した、下記のリードピン３を挿着するための直径1mm程
度の穿孔1b,1b…が、図示では外周から三列にわたって
多数穿設されて、更にこの周囲には段部から外方に延出
する外周部1cが形成されている。(Embodiment) The drawings show an embodiment of the present invention, in which a rectangular opening 1a is formed in the substantially center of a plate-shaped stem 1 made of iron or an iron alloy such as 42 alloy, and the surrounding In the drawing, a large number of perforations 1b, 1b having a diameter of about 1 mm for inserting the following lead pins 3 which are communicated with each other in the upper and lower direction are formed in three rows from the outer periphery in the figure, and further around this, from the step portion to the outside. An outer peripheral portion 1c extending inward is formed.

上記ステム１の開口1a内には銅製等の放熱性の良い放熱
部材２が封入固着されている。このように、放熱部材２
を配設し、この上面に下記のように半導体チップ５を載
置することにより、熱伝導性の向上を図るようにするこ
とができる。また、上記ステム１の各穿孔1b内には夫々
リードピン３が、下方に突出した状態でその上端におい
てガラス等の封止材４によって気密封止されて固着され
ている。In the opening 1a of the stem 1, a heat dissipation member 2 made of copper or the like having good heat dissipation is sealed and fixed. In this way, the heat dissipation member 2
Is arranged, and the semiconductor chip 5 is mounted on the upper surface thereof as described below, so that the thermal conductivity can be improved. Further, the lead pin 3 is fixed in each of the perforations 1b of the stem 1 in a state of protruding downward by hermetically sealing with a sealing material 4 such as glass at the upper end thereof.

上記放熱部材２の上面には半導体チップ５が載置され、
半田付け等により固定されている。またステム１の上面
には中間配線6,6…を配設し、所定の形状と特性が施さ
れた中間配線材としての配設基板７が重ね合せて備えら
れている。この配線基板７の大きさは上記ステム１より
も僅かに小さくて、このステム１の上面に配線基板７を
載置した際に、この外方にステム１の外周部1cが突出し
て、ここに下記のシェル10の周囲が気密封止できるよう
になされている。A semiconductor chip 5 is placed on the upper surface of the heat dissipation member 2,
It is fixed by soldering. Further, intermediate wirings 6, 6 ... Are arranged on the upper surface of the stem 1, and an arrangement substrate 7 as an intermediate wiring material having a predetermined shape and characteristics is provided in an overlapping manner. The size of the wiring board 7 is slightly smaller than that of the stem 1, and when the wiring board 7 is placed on the upper surface of the stem 1, the outer peripheral portion 1c of the stem 1 projects to the outside of the wiring board 7. The periphery of the shell 10 described below can be hermetically sealed.

なお、この配線基板７は、一般にガラスエポキシやポリ
イミド等の有機単層又は積層基板で構成されたものであ
るが、上記ステム１の材質の組合わせにより、アルミナ
やAlN等のセラミック基板を使用して構成することもで
きる。The wiring board 7 is generally composed of an organic single-layer or laminated board such as glass epoxy or polyimide, but a ceramic board such as alumina or AlN is used depending on the combination of the materials of the stem 1. It can also be configured.

この配設基板７の上記ステム１に穿設した穿孔1b,1b…
と対応する位置には，夫々上記中間配線の一端と電気的
に接続したスルーホール7a,7a…が形成され、この各通
孔7a内に各リードピン３の上端を夫々挿通させととも
に、この上端面を半田付け等の接合物質８により接合す
ることにより、この接合物質８を介して、各リードピン
３と各中間配線６の一端とを電気的に接続するよう構成
されている。Perforations 1b, 1b formed in the stem 1 of the mounting substrate 7 ...
Through holes 7a, 7a ... Which are electrically connected to one end of the intermediate wiring are respectively formed at positions corresponding to, and the upper ends of the lead pins 3 are inserted into the through holes 7a. Are bonded by a bonding material 8 such as soldering, so that each lead pin 3 and one end of each intermediate wiring 6 are electrically connected via this bonding material 8.

また、上記半導体チップ５の電極としての各パッドと上
記配線基板７の各中間配線６の他端とは夫々ボンディン
グワイヤ９により電気的に接続され、これによって、半
導体チップ４の各パッドと上記各リードピン３とが、夫
々電気的に接続するよう構成されている。Further, each pad as an electrode of the semiconductor chip 5 and the other end of each intermediate wiring 6 of the wiring board 7 are electrically connected by a bonding wire 9, respectively, whereby each pad of the semiconductor chip 4 and each of the above The lead pins 3 are configured to be electrically connected to each other.

更に、上記配線基板７の上面には、立上り部10aとこの
立上り部10aから連続して外方に延出した水平部10bが備
えられた、例えば金属製の蓋材としてのシェル10が被せ
られている。そして、この立上り部10aの内面と上記配
線基板７の周面とが当接し、更にこの水平部10bと上記
ステム１の外周部1cとが重合し、ここが電気溶接等によ
り気密封止されている。Further, the upper surface of the wiring board 7 is covered with a shell 10 as a lid member made of, for example, a metal, which is provided with a rising portion 10a and a horizontal portion 10b continuously extending outward from the rising portion 10a. ing. Then, the inner surface of the rising portion 10a and the peripheral surface of the wiring board 7 are brought into contact with each other, and further, the horizontal portion 10b and the outer peripheral portion 1c of the stem 1 are polymerized, which is hermetically sealed by electric welding or the like. There is.

このようにして、上記従来のプラスチック形PGAでは、
その特性上、不可能とされていた完全な気密封止を行っ
ているのである。In this way, in the above conventional plastic type PGA,
Due to its characteristics, it is completely impossible to hermetically seal.

なお、このステム１とシェル10の気密封止は、シェル10
がアルミナ等のセラミックで構成されていても、ステム
１との線膨脹係数を合せることにより、ガラスによる気
密封止で行うようにすることもできる。The stem 1 and the shell 10 are hermetically sealed by the shell 10
Although it is made of ceramics such as alumina, it can be hermetically sealed with glass by matching the linear expansion coefficient with the stem 1.

なお、このパッケージにおいては、外囲器が金属である
ために、半導体チップ５を半田等の導電性のある材料で
接続すると、半導体チップ５の裏面の電位が外囲器と同
じになってしまう。In this package, since the envelope is made of metal, if the semiconductor chip 5 is connected by a conductive material such as solder, the potential of the back surface of the semiconductor chip 5 becomes the same as that of the envelope. .

これを防止するため、半導体チップ５の固定に半導体の
組立て工程で一般に使用されている絶縁性の有機物を使
用したり、又はシェル10を封止した後、リードピン３を
残してステム１及びシェル10の部分を有機樹脂でコーテ
ィングすることにより、半導体チップ５の裏面の電位と
の分離を行うようにすることができる。To prevent this, an insulating organic material that is generally used in the semiconductor assembly process is used to fix the semiconductor chip 5, or after the shell 10 is sealed, the lead pin 3 is left and the stem 1 and the shell 10 are left. By coating the portion with the organic resin, it is possible to separate from the electric potential of the back surface of the semiconductor chip 5.

〔発明の効果〕〔The invention's effect〕

本発明は上記のような構成であるので、セラミック形PG
Aやプラシチック形PGAに比較して安価に製造することが
できるばかりでなく、確実に気密封止を行って、気密性
の完全性を図ることができる。しかも、セラミック形PG
Aとほぼ同等の大型パッケージへの適応性があるばかり
でなく、セラミック形PGAよりやや劣ることがあるもの
の、プラスチック形PGAとほぼ同等の多ピン化に対応す
ることができる。Since the present invention is configured as described above, the ceramic type PG
Not only can it be manufactured at a lower cost than A or plastic type PGA, but it can also be hermetically sealed to ensure the completeness of hermeticity. Moreover, ceramic type PG
Not only is it adaptable to a large package similar to A, but it is also slightly inferior to ceramic PGA, but it can handle the same number of pins as plastic PGA.

また、放熱特性を最良となし、しかも配線基板の基材に
ポリイミドやガラスエポキシ等を使用することにより、
電気容量の減少を図ることができる。In addition, it has the best heat dissipation characteristics, and by using polyimide or glass epoxy as the base material of the wiring board,
The electric capacity can be reduced.

更に、従来のセラミック形PGA、プラスチック形PGAは共
に品種に応じてパッケージを起こさなくてはならなかっ
たが、本発明によれば、リードピンの数が同じであれば
配線基板を変えるだけこれに対応することができ、従っ
て敏速、かつ安価にこの種のパッケージを提供すること
ができるといった効果がある。Further, both the conventional ceramic type PGA and the plastic type PGA had to be packaged according to the product type, but according to the present invention, if the number of lead pins is the same, the wiring board is changed. Therefore, it is possible to provide such a package promptly and inexpensively.

【図面の簡単な説明】[Brief description of drawings]

図面は本発明の一実施例を示し、第１図は一部を切断し
た斜視図、第２図は縦断面図である。 １……ステム、３……リードピン、５……半導体チッ
プ、６……中間配線、７……配線基板、８……接合物
質、９……ボンディングワイヤ、10……シェル。The drawings show one embodiment of the present invention. FIG. 1 is a partially cutaway perspective view, and FIG. 2 is a longitudinal sectional view. 1 ... Stem, 3 ... Lead pin, 5 ... Semiconductor chip, 6 ... Intermediate wiring, 7 ... Wiring board, 8 ... Bonding material, 9 ... Bonding wire, 10 ... Shell.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】内部に多数の穿孔を有する金属製のステム
と、表面に所定形状に配線がパターニングされ前記穿孔
に対応する位置にスルーホールが形成された前記ステム
に上面に重合する配線基板と、前記配線の一端と内部の
電極とが電気的に接続された半導体チップと、前記穿孔
内に貫設され頭部を前記スルーホール内に挿通させ接合
物質を介して前記配線の他端と電気的に接続されるとと
もに前記ステムの下方に突出されたリードピンと、前記
配線基板及び半導体チップを覆い該配線基板及び半導体
チップを気密封止した金属製のシェルとからなることを
特徴とする半導体パッケージ。1. A stem made of metal having a large number of perforations therein, and a wiring board which is superposed on the upper surface of the stem in which wiring is patterned into a predetermined shape on the surface and through holes are formed at positions corresponding to the perforations. , A semiconductor chip in which one end of the wiring and an internal electrode are electrically connected, and the other end of the wiring is electrically connected to the other end of the wiring through a bonding material that penetrates the head and is inserted into the through hole. Package including a lead pin that is electrically connected to each other and protrudes below the stem, and a metal shell that covers the wiring board and the semiconductor chip and hermetically seals the wiring board and the semiconductor chip. .
JP61280225A 1986-11-25 1986-11-25 Semiconductor package Expired - Fee Related JPH0773117B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP61280225A JPH0773117B2 (en) 1986-11-25 1986-11-25 Semiconductor package
EP87114577A EP0272390A3 (en) 1986-11-25 1987-10-06 Packages for a semiconductor device
KR1019870013294A KR900007301B1 (en) 1986-11-25 1987-11-25 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61280225A JPH0773117B2 (en) 1986-11-25 1986-11-25 Semiconductor package

Publications (2)

Publication Number Publication Date
JPS63133553A JPS63133553A (en) 1988-06-06
JPH0773117B2 true JPH0773117B2 (en) 1995-08-02

Family

ID=17622054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61280225A Expired - Fee Related JPH0773117B2 (en) 1986-11-25 1986-11-25 Semiconductor package

Country Status (3)

Country Link
EP (1) EP0272390A3 (en)
JP (1) JPH0773117B2 (en)
KR (1) KR900007301B1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH079953B2 (en) * 1988-04-13 1995-02-01 株式会社東芝 Method for manufacturing semiconductor device
JPH0243756A (en) * 1988-08-03 1990-02-14 Toshiba Components Co Ltd Semiconductor device
US4916523A (en) * 1988-09-19 1990-04-10 Advanced Micro Devices, Inc. Electrical connections via unidirectional conductive elastomer for pin carrier outside lead bond
DE3923533A1 (en) * 1989-07-15 1991-01-24 Diehl Gmbh & Co ARRANGEMENT OF AN INTEGRATED CIRCUIT ON A CIRCUIT BOARD
US5103292A (en) * 1989-11-29 1992-04-07 Olin Corporation Metal pin grid array package
US5247423A (en) * 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
US5991156A (en) * 1993-12-20 1999-11-23 Stmicroelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
FR2793990B1 (en) * 1999-05-19 2001-07-27 Sagem ELECTRONIC HOUSING ON PLATE AND METHOD FOR MANUFACTURING SUCH A HOUSING
JP2005064157A (en) * 2003-08-08 2005-03-10 Alps Electric Co Ltd Electronic circuit module
DE10352705A1 (en) * 2003-11-12 2005-06-23 Diehl Bgt Defence Gmbh & Co. Kg Circuit arrangement, especially for use in space, has element, especially vacuum-tight housing on base element and at least one heat-generating component connected to housing to dissipate heat losses

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3662230A (en) * 1968-06-25 1972-05-09 Texas Instruments Inc A semiconductor interconnecting system using conductive patterns bonded to thin flexible insulating films
JPS5236824B2 (en) * 1973-10-15 1977-09-19
JPS5113611A (en) * 1974-07-19 1976-02-03 Asahi Chemical Ind Hiryobotono uchikomisochi
JPS6032770U (en) * 1983-08-12 1985-03-06 富士通株式会社 Lead frame for circuit board

Also Published As

Publication number Publication date
KR880006773A (en) 1988-07-25
JPS63133553A (en) 1988-06-06
EP0272390A2 (en) 1988-06-29
KR900007301B1 (en) 1990-10-08
EP0272390A3 (en) 1988-12-07

Similar Documents

Publication Publication Date Title
US4975763A (en) Edge-mounted, surface-mount package for semiconductor integrated circuit devices
US5293301A (en) Semiconductor device and lead frame used therein
US3760090A (en) Electronic circuit package and method for making same
US4338621A (en) Hermetic integrated circuit package for high density high power applications
US5763939A (en) Semiconductor device having a perforated base film sheet
US4907067A (en) Thermally efficient power device package
US5563446A (en) Surface mount peripheral leaded and ball grid array package
US4167647A (en) Hybrid microelectronic circuit package
US5293069A (en) Ceramic-glass IC package assembly having multiple conductive layers
EP0084866A2 (en) Semiconductor casing
US5275975A (en) Method of making a relatively flat semiconductor package having a semiconductor chip encapsulated in molded material
US20100270667A1 (en) Semiconductor package with multiple chips and substrate in metal cap
US4115837A (en) LSI Chip package and method
JPH1082698A (en) Temperature sensor having resistance bulb
JPH0773117B2 (en) Semiconductor package
JP2001085602A (en) Multi-chip semiconductor module and manufacturing method thereof
JPH05326735A (en) Semiconductor device and manufacture thereof
US6166435A (en) Flip-chip ball grid array package with a heat slug
JP4886104B2 (en) Power semiconductor packaging package with ball grid array
USRE37416E1 (en) Method for manufacturing a modular semiconductor power device
EP0517967B1 (en) High current hermetic package
US4931906A (en) Hermetically sealed, surface mountable component and carrier for semiconductor devices
JPH0794669A (en) Semiconductor package module
JPH0917910A (en) Semiconductor device and its manufacture, inspection method and mounting board
USRE29325E (en) Hermetic power package

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees