JPS577147A - Mounting construction of semiconductor device - Google Patents
Mounting construction of semiconductor deviceInfo
- Publication number
- JPS577147A JPS577147A JP8161180A JP8161180A JPS577147A JP S577147 A JPS577147 A JP S577147A JP 8161180 A JP8161180 A JP 8161180A JP 8161180 A JP8161180 A JP 8161180A JP S577147 A JPS577147 A JP S577147A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- resin
- bump
- high density
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To enable a high density interconnection with a less occupation area for mounting by burrying a chip with a bump into a recess of an insulation circuit substrate with a resin with the face up in such a manner as to be flush in the surface with the substrate. CONSTITUTION:An IC body 4 is housed in a housing section 2 of a substrate 1 made of a resin and ceramics with the face up and burried with the resin 6. A bump 5 is exposed by lapping along with a smooth surface of the substrate 1. Then, a metal thin film 7 is deposited while a through hole 3 is made conductive and a wiring is formed with a resist pattern 8. Finally, covering with Au or the like 9 provents the oxidation of the metal film 7 and improves the junction property. This enables full utilization of the surface of the substrate thereby affording a high density wiring with a less occupation area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8161180A JPS577147A (en) | 1980-06-17 | 1980-06-17 | Mounting construction of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8161180A JPS577147A (en) | 1980-06-17 | 1980-06-17 | Mounting construction of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS577147A true JPS577147A (en) | 1982-01-14 |
Family
ID=13751109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8161180A Pending JPS577147A (en) | 1980-06-17 | 1980-06-17 | Mounting construction of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS577147A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4931853A (en) * | 1986-05-20 | 1990-06-05 | Kabushiki Kaisha Toshiba | IC card and method of manufacturing the same |
US4950623A (en) * | 1988-08-02 | 1990-08-21 | Microelectronics Center Of North Carolina | Method of building solder bumps |
US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
US5875100A (en) * | 1996-05-31 | 1999-02-23 | Nec Corporation | High-density mounting method and structure for electronic circuit board |
WO2000017924A2 (en) * | 1998-09-21 | 2000-03-30 | Telefonaktiebolaget Lm Ericsson | Method and device for buried chips |
JP2001345560A (en) * | 2000-02-09 | 2001-12-14 | Ngk Spark Plug Co Ltd | Wiring board, and its manufacturing method, and electronic component |
JP2002290006A (en) * | 2001-03-27 | 2002-10-04 | Ibiden Co Ltd | Method of manufacturing substrate with built-in parts |
US7928001B2 (en) | 2006-10-02 | 2011-04-19 | Renesas Electronics Corporation | Electronic device and method of manufacturing the same |
US8354340B2 (en) | 2006-10-02 | 2013-01-15 | Renesas Electronics Corporation | Electronic device and method of manufacturing the same |
US8685796B2 (en) | 2006-10-02 | 2014-04-01 | Renesas Electronics Corporation | Electronic device and method of manufacturing the same |
-
1980
- 1980-06-17 JP JP8161180A patent/JPS577147A/en active Pending
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4997791A (en) * | 1986-05-20 | 1991-03-05 | Kabushiki Kaisha Toshiba | IC card and method of manufacturing the same |
US4931853A (en) * | 1986-05-20 | 1990-06-05 | Kabushiki Kaisha Toshiba | IC card and method of manufacturing the same |
US4950623A (en) * | 1988-08-02 | 1990-08-21 | Microelectronics Center Of North Carolina | Method of building solder bumps |
US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
US5374893A (en) * | 1992-03-04 | 1994-12-20 | Mcnc | Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon |
US5381946A (en) * | 1992-03-04 | 1995-01-17 | Mcnc | Method of forming differing volume solder bumps |
US5875100A (en) * | 1996-05-31 | 1999-02-23 | Nec Corporation | High-density mounting method and structure for electronic circuit board |
WO2000017924A2 (en) * | 1998-09-21 | 2000-03-30 | Telefonaktiebolaget Lm Ericsson | Method and device for buried chips |
WO2000017924A3 (en) * | 1998-09-21 | 2000-08-17 | Ericsson Telefon Ab L M | Method and device for buried chips |
JP4685251B2 (en) * | 2000-02-09 | 2011-05-18 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
JP2001345560A (en) * | 2000-02-09 | 2001-12-14 | Ngk Spark Plug Co Ltd | Wiring board, and its manufacturing method, and electronic component |
JP2002290006A (en) * | 2001-03-27 | 2002-10-04 | Ibiden Co Ltd | Method of manufacturing substrate with built-in parts |
US7928001B2 (en) | 2006-10-02 | 2011-04-19 | Renesas Electronics Corporation | Electronic device and method of manufacturing the same |
US8354340B2 (en) | 2006-10-02 | 2013-01-15 | Renesas Electronics Corporation | Electronic device and method of manufacturing the same |
US8633591B2 (en) | 2006-10-02 | 2014-01-21 | Renesas Electronics Corporation | Electronic device |
US8685796B2 (en) | 2006-10-02 | 2014-04-01 | Renesas Electronics Corporation | Electronic device and method of manufacturing the same |
US8823174B2 (en) | 2006-10-02 | 2014-09-02 | Renesas Electronics Corporation | Electronic device |
US8975750B2 (en) | 2006-10-02 | 2015-03-10 | Renesas Electronics Corporation | Electronic device |
US9406602B2 (en) | 2006-10-02 | 2016-08-02 | Renesas Electronics Corporation | Electronic device |
US20160307875A1 (en) | 2006-10-02 | 2016-10-20 | Renesas Electronics Corporation | Electronic device |
US9847325B2 (en) | 2006-10-02 | 2017-12-19 | Renesas Electronics Corporation | Electronic device |
US10224318B2 (en) | 2006-10-02 | 2019-03-05 | Renesas Electronics Corporation | Electronic device |
US10580763B2 (en) | 2006-10-02 | 2020-03-03 | Renesas Electronics Corporation | Electronic device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6484726A (en) | Semiconductor integrated circuit device | |
JPS577147A (en) | Mounting construction of semiconductor device | |
IE822564L (en) | Fabrication a semiconductor device having a phosphosilicate glass layer | |
JPS55111151A (en) | Integrated circuit device | |
JPS5571052A (en) | Substrate for semiconductor device | |
JPS57107059A (en) | Semiconductor package | |
EP0347792A3 (en) | Multi-layer wirings on a semiconductor device and fabrication method | |
JPS5268388A (en) | Semiconductor integrated circuit | |
JPS5732655A (en) | Semiconductor integrated circuit device | |
JPS55117254A (en) | Fabrication of electronic device | |
JPS6416698A (en) | Semiconductor device and manufacture thereof | |
JPS52127184A (en) | Semiconductor integrated circuit | |
JPS5318962A (en) | Semiconductor package | |
JPS5318960A (en) | Bonding method | |
JPS556862A (en) | Mounting structure of ic for electronic timepiece | |
JPS5526612A (en) | Manufacturing of carrier tape useful for ic | |
JPS56155556A (en) | Semiconductor device | |
JPS57132341A (en) | Multilayer wiring structure in semiconductor device | |
JPS56146256A (en) | Hybrid ic device | |
JPS5227391A (en) | Contact forming method of semiconductor device | |
JPS5736859A (en) | Integrated circuit device | |
JPS6484646A (en) | Manufacture of semiconductor package | |
JPS5355962A (en) | Semiconductor integrated circuit | |
JPS57208162A (en) | Semiconductor integrated circuit | |
JPS551604A (en) | Magnetic bubble memory device |