JPS577147A - Mounting construction of semiconductor device - Google Patents

Mounting construction of semiconductor device

Info

Publication number
JPS577147A
JPS577147A JP8161180A JP8161180A JPS577147A JP S577147 A JPS577147 A JP S577147A JP 8161180 A JP8161180 A JP 8161180A JP 8161180 A JP8161180 A JP 8161180A JP S577147 A JPS577147 A JP S577147A
Authority
JP
Japan
Prior art keywords
substrate
resin
bump
high density
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8161180A
Other languages
Japanese (ja)
Inventor
Yukichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP8161180A priority Critical patent/JPS577147A/en
Publication of JPS577147A publication Critical patent/JPS577147A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable a high density interconnection with a less occupation area for mounting by burrying a chip with a bump into a recess of an insulation circuit substrate with a resin with the face up in such a manner as to be flush in the surface with the substrate. CONSTITUTION:An IC body 4 is housed in a housing section 2 of a substrate 1 made of a resin and ceramics with the face up and burried with the resin 6. A bump 5 is exposed by lapping along with a smooth surface of the substrate 1. Then, a metal thin film 7 is deposited while a through hole 3 is made conductive and a wiring is formed with a resist pattern 8. Finally, covering with Au or the like 9 provents the oxidation of the metal film 7 and improves the junction property. This enables full utilization of the surface of the substrate thereby affording a high density wiring with a less occupation area.
JP8161180A 1980-06-17 1980-06-17 Mounting construction of semiconductor device Pending JPS577147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8161180A JPS577147A (en) 1980-06-17 1980-06-17 Mounting construction of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8161180A JPS577147A (en) 1980-06-17 1980-06-17 Mounting construction of semiconductor device

Publications (1)

Publication Number Publication Date
JPS577147A true JPS577147A (en) 1982-01-14

Family

ID=13751109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8161180A Pending JPS577147A (en) 1980-06-17 1980-06-17 Mounting construction of semiconductor device

Country Status (1)

Country Link
JP (1) JPS577147A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931853A (en) * 1986-05-20 1990-06-05 Kabushiki Kaisha Toshiba IC card and method of manufacturing the same
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5875100A (en) * 1996-05-31 1999-02-23 Nec Corporation High-density mounting method and structure for electronic circuit board
WO2000017924A3 (en) * 1998-09-21 2000-08-17 Ericsson Telefon Ab L M Method and device for buried chips
JP2001345560A (en) * 2000-02-09 2001-12-14 Ngk Spark Plug Co Ltd Wiring board, and its manufacturing method, and electronic component
JP2002290006A (en) * 2001-03-27 2002-10-04 Ibiden Co Ltd Manufacturing method of component embedded board
US7928001B2 (en) 2006-10-02 2011-04-19 Renesas Electronics Corporation Electronic device and method of manufacturing the same
US8354340B2 (en) 2006-10-02 2013-01-15 Renesas Electronics Corporation Electronic device and method of manufacturing the same
US8685796B2 (en) 2006-10-02 2014-04-01 Renesas Electronics Corporation Electronic device and method of manufacturing the same

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931853A (en) * 1986-05-20 1990-06-05 Kabushiki Kaisha Toshiba IC card and method of manufacturing the same
US4997791A (en) * 1986-05-20 1991-03-05 Kabushiki Kaisha Toshiba IC card and method of manufacturing the same
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5374893A (en) * 1992-03-04 1994-12-20 Mcnc Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5381946A (en) * 1992-03-04 1995-01-17 Mcnc Method of forming differing volume solder bumps
US5875100A (en) * 1996-05-31 1999-02-23 Nec Corporation High-density mounting method and structure for electronic circuit board
WO2000017924A3 (en) * 1998-09-21 2000-08-17 Ericsson Telefon Ab L M Method and device for buried chips
EP1116268A2 (en) * 1998-09-21 2001-07-18 Telefonaktiebolaget Lm Ericsson Method and device for buried chips
JP2001345560A (en) * 2000-02-09 2001-12-14 Ngk Spark Plug Co Ltd Wiring board, and its manufacturing method, and electronic component
JP2002290006A (en) * 2001-03-27 2002-10-04 Ibiden Co Ltd Manufacturing method of component embedded board
US7928001B2 (en) 2006-10-02 2011-04-19 Renesas Electronics Corporation Electronic device and method of manufacturing the same
US8354340B2 (en) 2006-10-02 2013-01-15 Renesas Electronics Corporation Electronic device and method of manufacturing the same
US8633591B2 (en) 2006-10-02 2014-01-21 Renesas Electronics Corporation Electronic device
US8685796B2 (en) 2006-10-02 2014-04-01 Renesas Electronics Corporation Electronic device and method of manufacturing the same
US8823174B2 (en) 2006-10-02 2014-09-02 Renesas Electronics Corporation Electronic device
US8975750B2 (en) 2006-10-02 2015-03-10 Renesas Electronics Corporation Electronic device
US9406602B2 (en) 2006-10-02 2016-08-02 Renesas Electronics Corporation Electronic device
US20160307875A1 (en) 2006-10-02 2016-10-20 Renesas Electronics Corporation Electronic device
US9847325B2 (en) 2006-10-02 2017-12-19 Renesas Electronics Corporation Electronic device
US10224318B2 (en) 2006-10-02 2019-03-05 Renesas Electronics Corporation Electronic device
US10580763B2 (en) 2006-10-02 2020-03-03 Renesas Electronics Corporation Electronic device

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