JPS5318960A - Bonding method - Google Patents

Bonding method

Info

Publication number
JPS5318960A
JPS5318960A JP9369376A JP9369376A JPS5318960A JP S5318960 A JPS5318960 A JP S5318960A JP 9369376 A JP9369376 A JP 9369376A JP 9369376 A JP9369376 A JP 9369376A JP S5318960 A JPS5318960 A JP S5318960A
Authority
JP
Japan
Prior art keywords
bonding method
sand
junction
reliability
improvement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9369376A
Other languages
Japanese (ja)
Inventor
Yoshiharu Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP9369376A priority Critical patent/JPS5318960A/en
Publication of JPS5318960A publication Critical patent/JPS5318960A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To achieve the improvement in the reliability of junction sand the reduction in cost by providing more than 1 layer of elastic material layers on the substrate secured with semiconductor chips.
JP9369376A 1976-08-06 1976-08-06 Bonding method Pending JPS5318960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9369376A JPS5318960A (en) 1976-08-06 1976-08-06 Bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9369376A JPS5318960A (en) 1976-08-06 1976-08-06 Bonding method

Publications (1)

Publication Number Publication Date
JPS5318960A true JPS5318960A (en) 1978-02-21

Family

ID=14089472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9369376A Pending JPS5318960A (en) 1976-08-06 1976-08-06 Bonding method

Country Status (1)

Country Link
JP (1) JPS5318960A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552229A (en) * 1978-10-11 1980-04-16 Nec Corp Manufacture of semiconductor device
JPH0159282U (en) * 1987-10-09 1989-04-13
JPH0329452U (en) * 1989-07-31 1991-03-25

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552229A (en) * 1978-10-11 1980-04-16 Nec Corp Manufacture of semiconductor device
JPS6130737B2 (en) * 1978-10-11 1986-07-15 Nippon Electric Co
JPH0159282U (en) * 1987-10-09 1989-04-13
JPH0513729Y2 (en) * 1987-10-09 1993-04-12
JPH0329452U (en) * 1989-07-31 1991-03-25

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