JPS55165657A - Multi-chip package - Google Patents
Multi-chip packageInfo
- Publication number
- JPS55165657A JPS55165657A JP7337779A JP7337779A JPS55165657A JP S55165657 A JPS55165657 A JP S55165657A JP 7337779 A JP7337779 A JP 7337779A JP 7337779 A JP7337779 A JP 7337779A JP S55165657 A JPS55165657 A JP S55165657A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- chips
- carriers
- circuit board
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
PURPOSE:To enhance the heat radiating property of a multi-chip package and facilitate the replacement of an IC, by composing the package of a heat sink and a multilayer circuit board, laying a plurality of chip carriers through the board and directly connecting the chips to the heat sink. CONSTITUTION:A multi-chip package is composed of a heat sink 3 and a multilayer circuit board 1 bonded thereon. Electrode wirings, the number of which corresponds to that of IC chips 2 which are mounted on the surface of the board 1, are provided on the surface and protected with an insulating film. Chip carriers 4 are then provided so that they correspond to the wirings and extend into the heat sink 3 through the circuit board 1. The lower ends of the carriers are secured on the heat sink 3 by using grease 8 of high conductivity. The IC chips 2 are secured on the upper ends of the carriers 4. The terminals 6 of the chips are connected to those 7 of the circuit board 1 by wires 5. Since the chips 2 are located on the carriers 4 directly connected to the heat sink 3, the heat radiating property of the package is improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7337779A JPS55165657A (en) | 1979-06-11 | 1979-06-11 | Multi-chip package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7337779A JPS55165657A (en) | 1979-06-11 | 1979-06-11 | Multi-chip package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55165657A true JPS55165657A (en) | 1980-12-24 |
JPS625341B2 JPS625341B2 (en) | 1987-02-04 |
Family
ID=13516424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7337779A Granted JPS55165657A (en) | 1979-06-11 | 1979-06-11 | Multi-chip package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55165657A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947746A (en) * | 1982-09-10 | 1984-03-17 | Mitsubishi Electric Corp | Hybrid integrated circuit device |
US6023413A (en) * | 1997-02-03 | 2000-02-08 | Nec Corporation | Cooling structure for multi-chip module |
EP1407641A2 (en) * | 2001-06-28 | 2004-04-14 | Conexant Systems, Inc. | Structure and method for fabrication of a leadless multi-die carrier |
JP2009170493A (en) * | 2008-01-11 | 2009-07-30 | Hitachi Kokusai Electric Inc | Wiring board |
WO2015025447A1 (en) * | 2013-08-23 | 2015-02-26 | 富士電機株式会社 | Semiconductor devices |
JP2020190436A (en) * | 2019-05-20 | 2020-11-26 | 三菱電機株式会社 | Electronic device electrical characteristics evaluation jig |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5381957A (en) * | 1976-12-27 | 1978-07-19 | Fujitsu Ltd | Multilyer ceramic board with heat sink |
JPS5384169A (en) * | 1976-12-30 | 1978-07-25 | Fujitsu Ltd | Pattern inspecting device |
JPS546573A (en) * | 1977-06-16 | 1979-01-18 | Seiko Epson Corp | Electronic wristwatch |
-
1979
- 1979-06-11 JP JP7337779A patent/JPS55165657A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5381957A (en) * | 1976-12-27 | 1978-07-19 | Fujitsu Ltd | Multilyer ceramic board with heat sink |
JPS5384169A (en) * | 1976-12-30 | 1978-07-25 | Fujitsu Ltd | Pattern inspecting device |
JPS546573A (en) * | 1977-06-16 | 1979-01-18 | Seiko Epson Corp | Electronic wristwatch |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947746A (en) * | 1982-09-10 | 1984-03-17 | Mitsubishi Electric Corp | Hybrid integrated circuit device |
US6023413A (en) * | 1997-02-03 | 2000-02-08 | Nec Corporation | Cooling structure for multi-chip module |
EP1407641A2 (en) * | 2001-06-28 | 2004-04-14 | Conexant Systems, Inc. | Structure and method for fabrication of a leadless multi-die carrier |
EP1407641A4 (en) * | 2001-06-28 | 2010-05-12 | Skyworks Solutions Inc | Structure and method for fabrication of a leadless multi-die carrier |
JP2009170493A (en) * | 2008-01-11 | 2009-07-30 | Hitachi Kokusai Electric Inc | Wiring board |
WO2015025447A1 (en) * | 2013-08-23 | 2015-02-26 | 富士電機株式会社 | Semiconductor devices |
JPWO2015025447A1 (en) * | 2013-08-23 | 2017-03-02 | 富士電機株式会社 | Semiconductor device |
US9842786B2 (en) | 2013-08-23 | 2017-12-12 | Fuji Electric Co., Ltd. | Semiconductor device |
JP2020190436A (en) * | 2019-05-20 | 2020-11-26 | 三菱電機株式会社 | Electronic device electrical characteristics evaluation jig |
Also Published As
Publication number | Publication date |
---|---|
JPS625341B2 (en) | 1987-02-04 |
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