KR890702249A - Method for manufacturing semiconductor device package and device therefor - Google Patents

Method for manufacturing semiconductor device package and device therefor

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Publication number
KR890702249A
KR890702249A KR1019890701193A KR890701193A KR890702249A KR 890702249 A KR890702249 A KR 890702249A KR 1019890701193 A KR1019890701193 A KR 1019890701193A KR 890701193 A KR890701193 A KR 890701193A KR 890702249 A KR890702249 A KR 890702249A
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South Korea
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die
conductive
conductive layer
package according
layer
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KR1019890701193A
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Korean (ko)
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KR920008256B1 (en
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존롱
에스.시도로브스키 라첼
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콘래드 델 오카
엘에스 아이 로직 코포레이션
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Publication of KR890702249A publication Critical patent/KR890702249A/en
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Publication of KR920008256B1 publication Critical patent/KR920008256B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음No content

Description

반도체 장치 패키지의 제조방법 및 그 장치Method for manufacturing semiconductor device package and device therefor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따라 만들어진 반도체 조립체의 부분 단면도이다. 제 2 도는 제 1 도의 부분 조립체에다 반도체 다이를 부착시킨 것을 나타내는 것이다. 제 3 도는 조립체의 전도 리드핑거에다 다이의 와이어를 접합시킨 것을 나타내는 것이다.1 is a partial cross-sectional view of a semiconductor assembly made in accordance with the present invention. 2 shows the attachment of a semiconductor die to the subassembly of FIG. 3 shows bonding the die wire to the conductive lead finger of the assembly.

Claims (18)

패턴된 절연층과 그 절연층에 결합된 전도층을 포함하는 테이프 ; 테이프의 한쪽 표면에 고착된 반도체 다이 ; 전도층에 결합된 절연소자 ; 전도층에다 반도체 다이를 전기적으로 결합시키는 장치 ; 전도층에 결합되어 있고 반도체 다이와 전기 결합장치 들레에 위치되어 있는 본체 프레임 ; 그리고 프레임 위에 배치되어 있고 그리고 전기 결합장치와 다이 위의 프레임 내에 있는 캡슐제 본체로 구성되어 있는 것을 특징으로 하는 반도체 장치 패키지.A tape comprising a patterned insulating layer and a conductive layer bonded to the insulating layer; A semiconductor die fixed to one surface of the tape; An insulation element coupled to the conductive layer; An apparatus for electrically coupling a semiconductor die to a conductive layer; A body frame coupled to the conductive layer and located in the semiconductor die and the electrical coupling device; And a capsule body disposed over the frame and in the frame over the die and the electrical coupling device. 제 1 항에 있어서, 패턴된 절연층과 전도층 사이에 배치되어 있는 전도필름을 포함하고 있는 것을 특징으로 하는 패키지.The package according to claim 1, further comprising a conductive film disposed between the patterned insulating layer and the conductive layer. 제 2 항에 있어서, 전도필름은 구리가 튕겨져서 형성되어 있는 것을 특징으로 하는 패키지.The package according to claim 2, wherein the conductive film is formed by jumping of copper. 제 1 항에 있어서, 절연층은 유연한 물질로 만들어져 있는 것을 특징으로 하는 패키지.The package of claim 1 wherein the insulation layer is made of a flexible material. 제 3 항에 있어서, 절연층은 켑톤으로 만들어져 있는 것을 특징으로 하는 패키지.4. A package according to claim 3, wherein the insulating layer is made of dapton. 제 1 항에 있어서, 전도층은 금으로 된 플레이트로 만들어져 있는 것을 특징으로 하는 패키지.The package according to claim 1, wherein the conductive layer is made of a plate made of gold. 제 1 항에 있어서, 전도층의 뒷면에 결합된 절연요소를 포함하고 있는 것을 특징으로 하는 패키지.The package of claim 1 comprising an insulating element bonded to the back side of the conductive layer. 제 1 항에 있어서, 결합장치는 접합 와이어를 구성하고 있는 것을 특징으로 하는 패키지.The package according to claim 1, wherein the coupling device constitutes a joining wire. 제 7 항에 있어서, 다이와 접합 와이어 상에 배치되어 있는 실리콘 겔을 포함하고 있는 것을 특징으로 하는 패키지.8. A package according to claim 7, comprising a silicone gel disposed on the die and the bonding wire. 제 1 항에 있어서, 접합 와이어에 결합된 접합리드핑거, 그리고 외부 전도 리드에 연결되게 접합리드핑거에 결합된 전도핀을 포함하고 있는 것을 특징으로 하는 패키지.2. A package according to claim 1, comprising a bond lead finger coupled to the bond wire and a conductive pin coupled to the bond lead finger connected to the external conducting lead. 제 1 항에 있어서, 전기 결합장치는 전도 범프를 구성하고 있는 것을 특징으로 하는 패키지.The package according to claim 1, wherein the electrical coupling device constitutes a conductive bump. 제10항에 있어서, 절연요소는 이면요소이고, 그리고 본체 프레임은 전도 리드를 둘러싸고 있는 이면 요소에 연결되어 있는 것을 특징으로 하는 패키지.11. A package according to claim 10, wherein the insulating element is a backing element and the body frame is connected to a backing element surrounding the conducting lead. 제 1 항에 있어서, 본체 프레임은 패턴된 절연층의 두께보다 더 큰 높이를 가지는 것을 특징으로 하는 패키지.The package of claim 1 wherein the body frame has a height greater than the thickness of the patterned insulating layer. 절연층에 전도필름을 튕겨서 팬턴된 와이어를 접합시키는 테이프를 형성시키고 ; 전도 리드의 패턴을 만들기 위해 절연층과 전드 필름을 에칭시키며 ; 전도 필름에다 패턴된 데포지션시키고 ; 와이어를 접합시킬 수 있는 테이프에다 반도체 다이를 부착시키며 ; 다이와 전도층 사이에 전기 연결체를 형성시키고 ; 전도층의 이면에 절연요소를 결합시키며 ; 다이와 전기 연결체 위에 보호용 절연 피복물을 데포지션시키고 ; 절연요소와 전도층의 상단 표면에 본체 프레임을 부착시켜 다이, 전기 연결체 및 피복물을 감싸며 ; 그리고 본체 프레임, 피복물, 다이 및 전기 연결체를 절연물로 캡슐시키는 단계로 구성되어 있는 것을 특징으로 하는 반도체 장치 패키지의 제조 방법.Bounce the conductive film on the insulating layer to form a tape for bonding the panned wires; Etching the insulating layer and the transfer film to form a pattern of the conductive leads; Patterned deposition on the conductive film; Attaching the semiconductor die to a tape capable of bonding the wires; Forming an electrical connection between the die and the conductive layer; Bonding an insulating element to the backside of the conductive layer; Depositing a protective insulating coating over the die and electrical connections; Attaching the body frame to the top surface of the insulating element and the conductive layer to enclose the die, electrical connections and coating; And encapsulating the body frame, coating, die, and electrical connector with an insulator. 제 14 항에 있어서, 다이는 다이 부착에폭시에 의해 테이프에 부착되고 그리고 1시간 이하동안 약 150℃의 온도에서 경화되어지는 것을 특징으로 하는 방법.The method of claim 14, wherein the die is attached to the tape by die attach epoxy and is cured at a temperature of about 150 ° C. for up to one hour. 제 14 항에 있어서, 전기 연결체를 형성시키는 단계는 패턴된 전도층의 전도 리드에다 다이 패드 사이의 와이어를 열음파적으로 접합시키는 것에 의해 형성되는 것을 특징으로 하는 방법.15. The method of claim 14, wherein forming an electrical connector is formed by thermoacoustically bonding wires between die pads to conductive leads of a patterned conductive layer. 제 14 항에 있어서, 보호피복물을 데포지션 시키는 단계는 실리콘 겔이 다이와 전기 연결체 위에 흐르게 하고 그리고 겔 피복물을 경화시키는 것으로 구성되어 있는 것을 특징으로 하는 방법.15. The method of claim 14, wherein depositing the protective coating consists of causing a silicone gel to flow over the die and the electrical connector and to cure the gel coating. 제 14 항에 있어서, 본체 프레임이 전도 리드상의 절연요소에 흘러서 부착되게 하는 단계를 포함하고 있는 것을 특징으로 하는 방법.15. The method of claim 14, comprising the step of allowing the body frame to flow and attach to an insulating element on the conductive lead. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890701193A 1987-10-30 1988-10-26 Method and means of fabricating a semiconductor device package KR920008256B1 (en)

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US11522887A 1987-10-30 1987-10-30
US115,228 1987-10-30
PCT/US1988/003790 WO1989004552A1 (en) 1987-10-30 1988-10-26 Method and means of fabricating a semiconductor device package

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EP0344259A1 (en) 1989-12-06
KR920008256B1 (en) 1992-09-25

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