JP2664259B2 - Semiconductor device package and method of manufacturing the same - Google Patents

Semiconductor device package and method of manufacturing the same

Info

Publication number
JP2664259B2
JP2664259B2 JP1500158A JP50015888A JP2664259B2 JP 2664259 B2 JP2664259 B2 JP 2664259B2 JP 1500158 A JP1500158 A JP 1500158A JP 50015888 A JP50015888 A JP 50015888A JP 2664259 B2 JP2664259 B2 JP 2664259B2
Authority
JP
Japan
Prior art keywords
die
semiconductor device
conductive layer
device package
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1500158A
Other languages
Japanese (ja)
Other versions
JPH03503342A (en
Inventor
ロング，ジョン
シドロフスキイ，ラシェル，エス．
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ERU ESU AI ROJITSUKU CORP
Original Assignee
ERU ESU AI ROJITSUKU CORP
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Filing date
Publication date
Application filed by ERU ESU AI ROJITSUKU CORP filed Critical ERU ESU AI ROJITSUKU CORP
Publication of JPH03503342A publication Critical patent/JPH03503342A/en
Application granted granted Critical
Publication of JP2664259B2 publication Critical patent/JP2664259B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【発明の詳細な説明】 発明の分野 本発明は、半導体装置パッケージを製造する方法及び
装置に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a method and an apparatus for manufacturing a semiconductor device package.

発明の背景 従来の半導体装置パッケージは、サンドイッチ成形形
態で製造されており、半導体装置は封止されて、ダイの
両側にパッケージを形成していた。成形処理後にパッケ
ージを冷却すると、より大きな成形パッケージはカール
する傾向があり、それにより欠陥性乃至は使用不能の装
置とされる。また、パッケージに、半導体装置の要素へ
湿気が浸透することを可能とするような小さな開口乃至
は亀裂があると、半導体ダイの剥離が発生することがあ
り、それにより該装置を欠陥性のものとするか、又は該
装置の動作寿命を減少させる場合がある。更に、パッケ
ージを構築する為にモールド即ち成形を使用すること
は、パッケージの高さ及び面積を著しく増加させること
となる。BACKGROUND OF THE INVENTION Conventional semiconductor device packages are manufactured in a sandwich molded form, and the semiconductor device is sealed to form packages on both sides of a die. As the package cools after the molding process, larger molded packages tend to curl, thereby rendering the device defective or unusable. Also, if there are small openings or cracks in the package that allow moisture to penetrate into the elements of the semiconductor device, peeling of the semiconductor die may occur, thereby rendering the device defective. Or reduce the operating life of the device. In addition, the use of molds to build the package significantly increases the height and area of the package.

複合パッケージ組立体は、剛性リードフレーム及び薄
い可撓性テープ状構成体で形成される。該テープ状構成
体は、リードフレームのリードへ接続されているリード
フィンガーで構成されている。ボンドワイヤを包含する
半導体組立体は、リードフレーム、テープ状構成体、ボ
ンドワイヤ及び導電性リードを有する半導体装置を取り
囲む為に多数の成形ステップを必要とする２セクション
モールドを使用して、封止させる。The composite package assembly is formed of a rigid lead frame and a thin flexible tape-like structure. The tape-like structure is composed of lead fingers connected to the leads of a lead frame. The semiconductor assembly containing the bond wires is encapsulated using a two-section mold that requires multiple molding steps to surround the semiconductor device having the lead frame, tape-like structure, bond wires and conductive leads. Let it.

半導体業界において標準的である従来の半導体モール
ドパッケージは、最大160本の導電性リードを受け付け
ることが可能であり、それは、典型的に、中心間におい
て50乃至25ミリインチの間の間隔があけられている。リ
ード数が増加すると、リードへ接続するボンドワイヤの
数も増加する。ボンドワイヤの数が増加すると、パッケ
ージが大型化する。Conventional semiconductor mold packages, which are standard in the semiconductor industry, are capable of accepting up to 160 conductive leads, which are typically spaced between 50 and 25 milli inches center-to-center. I have. As the number of leads increases, the number of bond wires connected to the leads also increases. As the number of bond wires increases, the size of the package increases.

半導体業界の主要目的は、より多くの導電性リードを
有しているが一層小型のパッケージとした半導体装置を
製造することである。パッケージが一層小型であると、
一層多くのダイパッドを有する半導体ダイを使用するこ
とが可能であり、それは半導体組立体のリードの間隔が
一層近接したものであることを必要とする。その結果、
動作の信頼性を改善すると共に、一層高速の回路動作速
度を実現することが可能である。The primary objective of the semiconductor industry is to manufacture semiconductor devices having more conductive leads, but in smaller packages. If the package is smaller,
It is possible to use a semiconductor die having more die pads, which requires that the leads of the semiconductor assembly be closer together. as a result,
It is possible to improve the operation reliability and to realize a higher circuit operation speed.

発明の要約 本発明の目的とするところは、プラスチックパッケー
ジ本体を形成する為のモールドプロセスに対する必要性
を取り除いた新規で且つ改良した半導体パッケージを提
供することである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a new and improved semiconductor package that eliminates the need for a molding process to form a plastic package body.

本発明の別の目的とするところは、ワイヤボンディン
グを除去することの可能な半導体パッケージを提供する
ことである。It is another object of the present invention to provide a semiconductor package capable of eliminating wire bonding.

別の目的とするところは、比較的多数の導電性リード
及び外部ピンを提供する半導体パッケージを提供するこ
とである。Another object is to provide a semiconductor package that provides a relatively large number of conductive leads and external pins.

本発明の更に別の目的とするところは、湿気からの高
度の保護を可能とする半導体パッケージを提供すること
である。It is yet another object of the present invention to provide a semiconductor package that allows a high degree of protection from moisture.

本発明によれば、テープはパターン化した絶縁層及び
該絶縁層へ接続されている導電層から形成されている。
半導体ダイを該テープの１表面上のパッドへ取り付け且
つ該導電層のリードへ電気的に接続する。絶縁性被覆を
該ダイ及びワイヤーリード上に付与する。ダイ取り付け
パッドに対向する表面において、絶縁性テープ要素を導
電層へ付着させる。パッケージフレーム乃至は本体フレ
ームを半導体ダイ及び電気的接続部及びリードを取り巻
くテープへ接続させる。該本体フレームは、本体フレー
ム頂部、ダイ及び導電性ワイヤー及びリード上に付与し
た封止物質を閉じ込めるべく作用する。According to the invention, the tape is formed from a patterned insulating layer and a conductive layer connected to the insulating layer.
Semiconductor dies are attached to pads on one surface of the tape and electrically connected to leads of the conductive layer. An insulating coating is applied over the die and wire leads. At the surface opposite the die attach pad, an insulating tape element is attached to the conductive layer. The package frame or body frame is connected to the semiconductor die and the electrical connection and the tape surrounding the leads. The body frame acts to confine the encapsulating material applied on top of the body frame, die and conductive wires and leads.

１実施例において、ワイヤーリードの変わりに導電性
バンプを電気的接続用に使用する。ダブボンディングを
使用して、該ダイ上に形成されているバンプと導電層と
を接続させる。その結果、半導体装置パッケージは、一
層小型となり、且つ増加した数のリード及び外部ピンを
受け付けることが可能である。In one embodiment, conductive bumps are used for electrical connections instead of wire leads. Dub bonding is used to connect the bumps formed on the die to the conductive layers. As a result, the semiconductor device package becomes smaller and can receive an increased number of leads and external pins.

図面の説明 本発明を図面を参照してより詳細に説明する。Description of the drawings The invention will be described in more detail with reference to the drawings.

第１図は部分的に本発明に基づいて構成された半導体
組立体の断面側面図、 第２図は第１図の部分的組立体への半導体ダイの取り
付けを図示しており、 第３図は該組立体の導電性リードフィンガーへのダイ
のワイヤボンディングを例示しており、 第４図は半導体ダイ及びボンドワイヤー上への保護被
覆の付与を示しており、 第５図は本発明に基づいて整合した背面テープへ取付
ける為に反転させた部分的組立体を示しており、 第６図は該組立体へのフレーム本体の一体化を示して
おり、 第７図は本発明に基づいて構成された半導体装置パッ
ケージの断面図であり、 第８図は本発明に基づいて構成された半導体装置パッ
ケージを図示した部分的に開放した平面図であり、第８
図のＡ−Ａ線は第５図及び第１図乃至第７図及び第９図
の断面を取った切断線を表しており、 第９図は導電性バンプによって半導体ダイをパターン
化した導電層へ一体化させ且つ電気的に接続させる為に
テープ自動化ボンディング（TAB）を使用する半導体装
置パッケージの断面図であり、 第10図は本発明の半導体装置パッケージの分解図であ
る。1 is a cross-sectional side view of a semiconductor assembly partially constructed in accordance with the present invention; FIG. 2 illustrates the attachment of a semiconductor die to the partial assembly of FIG. 1; FIG. 4 illustrates the wire bonding of the die to the conductive lead fingers of the assembly, FIG. 4 shows the application of a protective coating on the semiconductor die and bond wires, and FIG. 6 shows the partial assembly inverted for attachment to the aligned backing tape, FIG. 6 shows the integration of the frame body into the assembly, and FIG. 7 is constructed in accordance with the present invention. FIG. 8 is a cross-sectional view of a semiconductor device package according to the present invention, and FIG. 8 is a partially open plan view showing a semiconductor device package configured according to the present invention.
The line AA in the figure represents a cut line taken through the cross section of FIGS. 5, 1 to 7 and 9, and FIG. 9 is a conductive layer obtained by patterning a semiconductor die with conductive bumps. FIG. 10 is a cross-sectional view of a semiconductor device package that uses tape automated bonding (TAB) to integrate and electrically connect the semiconductor device package. FIG. 10 is an exploded view of the semiconductor device package of the present invention.

図面全体にわたって、同様の数字は同様の要素を示し
ている。Like numbers refer to like elements throughout the drawings.

発明の詳細な説明 第１図を参照すると、本発明の実施において、ダイ支
持用基板としてのワイヤーホンド可能なテープ10は、例
えばデュポン社の商標名であるカプトン（Kapton）から
なるパターン化した絶縁層12、及び該カプトン層へ一体
化された金鍍金層14から形成されている。該金鍍金層
は、例えば、約30乃至40ミクロンの厚さである。米国特
許第4,711,330号に開示される如く、カプトン絶縁層12
をエッチし且つパターン化してダウンボンディング用の
空洞13を形成する。米国特許第4,771,330号に開示され
る如く、金鍍金層14もパターン化して絶縁層12の「ウエ
ッジ」部下側にギャップ23を形成する。DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, in the practice of the present invention, a wirebondable tape 10 as a substrate for supporting a die is a patterned insulation made of, for example, Kapton, a trademark of DuPont. It is formed from a layer 12 and a gold plating layer 14 integrated into the Kapton layer. The gold plating layer is, for example, about 30 to 40 microns thick. As disclosed in U.S. Pat.No. 4,711,330, Kapton insulating layer 12
Is etched and patterned to form cavities 13 for down bonding. The gold plating layer 14 is also patterned to form a gap 23 below the “wedge” of the insulating layer 12, as disclosed in US Pat. No. 4,771,330.

パターン化したワイヤボンド可能なテープ10を基台18
内に位置させて、テープ10に平坦性を与える。アミコン
（Amicon）990C（アミコン社の商標）等のダイ取り付け
用エポキシー22を、ワイヤーボンド可能なテープ10の１
表面上に形成したダイ取り付けパッド20上に付与する。
次いで、第２図に示した如く、半導体ダイ24を整合させ
且つダイ取り付けエポキシー上に配置させる。該ダイを
取付けたユニットを、約１時間の最大硬化時間の間約15
0℃の最大硬化温度で硬化させる為に炉内にいれる。Base 18 on patterned wire-bondable tape 10
To provide the tape 10 with flatness. Die-attaching epoxy 22, such as Amicon 990C (trademark of Amicon), can be used for wire bonding tape 10-1.
Applied on die attach pad 20 formed on the surface.
The semiconductor die 24 is then aligned and placed on the die attach epoxy, as shown in FIG. The unit to which the die was attached was removed for approximately 15 hours for a maximum cure time of approximately 1 hour.
Place in oven to cure at 0 ° C maximum curing temperature.

硬化したダイを取付けたユニットを、例えば米国特許
第4,790,897号に開示される如く、真空ヒーターブロッ
ク上に配置させて、該ユニットを堅実に且つ約200℃の
温度で保持する。次いで、該ユニットを、第３図に示し
た如く、熱音波的に即ちサーモソニックボンディングに
よって金ワイヤー26とワイヤーボンドさせて、ダイ24と
リードフィンガー乃至はパターン化した金属14の導電要
素との間に電気的接続を形成する。例えばダウコーニン
グ社のQ1−4939等の基材に対して硬化剤を１対10の混合
比を有するシリコーンゲル28を、最初に角部から初めて
次いで該ゲルを該ダイの中央部に付与することにより、
該ダイ上にダイ被覆として付与する。該ゲルを流動させ
て、該ダイ及びワイヤーを被覆させ（第４図参照）る
が、米国特許第4,711,330号に開示する如く、所定の区
域内に閉じ込める。次いで、該ダイを被着したユニット
を約１時間の間約150℃で炉内において硬化させる。The unit with the cured die attached is placed on a vacuum heater block, as disclosed, for example, in US Pat. No. 4,790,897, and the unit is held solid and at a temperature of about 200 ° C. The unit is then thermobonded, as shown in FIG. 3, to a gold wire 26 by thermosonic bonding, i.e., by thermosonic bonding, between the die 24 and the lead fingers or conductive elements of the patterned metal 14. To form an electrical connection. Applying a silicone gel 28 having a 1:10 mixing ratio of curing agent to a substrate such as Dow Corning Q1-4939, first from the corners and then to the center of the die By
Applied as a die coating on the die. The gel is allowed to flow to coat the die and wire (see FIG. 4), but is confined within a defined area as disclosed in US Pat. No. 4,711,330. The unit with the die attached is then cured in an oven at about 150 ° C. for about 1 hour.

ダイ被覆の硬化の後に、該ユニットを反転させ且つ、
第５図に示した如く、整合台30内に位置させる。基台18
は、ダイ、ワイヤ及びダイ被覆が損傷することから保護
する為に使用している。１表面上に接着剤34を有する絶
縁性テープ要素32を、ワイヤーボンド可能なテープ10の
一部である導電層14の下部表面乃至は背面上に固定させ
る。約100〜150℃の範囲内の温度でホットプレート上に
おいて予熱させた金属ブロック36を、約１乃至1.5分の
間テープ要素32と接触させて、接着剤34を流動させ且つ
導電性要素14の背面へ付着させ、一方テープ10を整合状
態に維持する。後の硬化プロセス期間中に接着剤34が台
30へ引っ付くことがないことを確保する為に、台30をよ
り広い窓を持った台（不図示）と置換させる。硬化を達
成する為に、該ユニットを、テープ10のダイ側乃至は上
部表面を下側に向けて約150℃で約0.5時間の間、炉内に
配置させる。After curing the die coating, invert the unit and
As shown in FIG. 5, it is located in the alignment table 30. Base 18
Are used to protect the die, wire and die coating from damage. An insulative tape element 32 having an adhesive 34 on one surface is secured to the lower or back surface of the conductive layer 14, which is part of the wire bondable tape 10. A metal block 36, preheated on a hot plate at a temperature in the range of about 100-150 ° C., is brought into contact with the tape element 32 for about 1-1.5 minutes to allow the adhesive 34 to flow and Adhere to the back while keeping the tape 10 in alignment. During the later curing process adhesive 34
To ensure that it does not get stuck on 30, replace table 30 with a table with a wider window (not shown). To achieve curing, the unit is placed in an oven at about 150 ° C. for about 0.5 hour with the die or top surface of tape 10 facing down.

本発明によれば、好適には例えばフィリップスケミカ
ル社の商標であるライトン（Ryton）等のポリマー物質
からなるパッケージフレーム乃至は本体フレーム40を、
例えばRT−4B（RJRポリマー社の商標）等のＢ−ステー
ジ接着剤とすることが可能なエポキシー接着剤42によっ
て該硬化させたユニットへ一体化させる。該ユニット
を、第６図に示した如く、ダイを上に向けたままで、台
乃至はトレイ44内に挿入する。インサート46を該ユニッ
トの上に位置させ、且つ整合台48を該インサートの上に
位置させる。該ユニットを120〜150℃の間の温度に維持
する一方、本体フレーム40を整合台48内に配置させ、従
って接着剤42は、金鍍金層14及びテープ要素32と接触す
る。第６図に示した如く、ブロック50によりフレームの
上部周辺部へ軽い力を付与する。該圧力は約15〜30秒の
間該フレームへ付与される。次いで、取付けたフレーム
を有する該ユニットを約１時間の間約150℃で硬化させ
る。In accordance with the present invention, a package or body frame 40, preferably made of a polymeric material such as Ryton, a trademark of Philips Chemicals,
The cured unit is integrated with an epoxy-adhesive 42, which can be a B-stage adhesive such as RT-4B (a trademark of RJR Polymers). The unit is inserted into the table or tray 44 with the die facing up, as shown in FIG. The insert 46 is positioned above the unit and the alignment table 48 is positioned above the insert. Maintaining the unit at a temperature between 120-150 ° C., while positioning the body frame 40 in the alignment table 48, the adhesive 42 is in contact with the gold plating layer 14 and the tape element 32. As shown in FIG. 6, the block 50 applies a light force to the upper peripheral portion of the frame. The pressure is applied to the frame for about 15-30 seconds. The unit with the attached frame is then cured at about 150 ° C. for about 1 hour.

該本体フレームを有するユニットが硬化した後に、例
えばハイソル（Hysol）CNB405−12（ハイソル社の商
標）等の電子グレードエポキシー物質52を使用して該装
置を封止し、一方該ユニットの温度を約50〜70℃に維持
する。該エポキシーを、例えば、回転運動における供給
針によって、周辺部乃至は本体内側角部から初めてダイ
区域の中心へ移動して、供給する。該エポキシーを均一
に流動させ、従って実質的に平坦な表面が得られ且つ空
気の泡が除去される。該エポキシーは、第７図に示した
如く、本体フレームの上部及び該フレーム内に閉じ込め
られている要素を効果的に封止する。次いで、該エポキ
シー封止物を、130℃乃至150℃の間の温度で２〜４時間
の間、該ユニットを炉内に配置させることによって硬化
させる。After the unit having the body frame is cured, the device is sealed using an electronic grade epoxy material 52, such as, for example, Hysol CNB405-12 (trademark of Hisol), while the temperature of the unit is reduced to about Maintain at 50-70 ° C. The epoxy is dispensed, for example by means of a supply needle in a rotary movement, from the periphery or the inner corner of the body to the center of the die area. The epoxy flows uniformly, thus providing a substantially flat surface and removing air bubbles. The epoxy effectively seals the top of the body frame and the elements contained within the frame, as shown in FIG. The epoxy seal is then cured by placing the unit in a furnace at a temperature between 130 ° C and 150 ° C for 2-4 hours.

第８図の平面図において、本発明の新規な半導体装置
パッケージ、パターン化したカプトン層12に対する本体
フレーム40の関係を示してある。スプロケット孔56がワ
イヤボンド可能なテープ10に設けてあり、該テープの自
動化処理の助けとなっている。ボンドワイヤー58は、ボ
ンドワイヤー26を外側リードフィンガーへ結合してお
り、上述した米国特許に記載される如く、外部接続部乃
至はピン60への電気的接続を可能としている。FIG. 8 is a plan view showing the relationship between the novel semiconductor device package of the present invention and the main body frame 40 relative to the patterned Kapton layer 12. Sprocket holes 56 are provided in the wirebondable tape 10 to aid in the automation of the tape. Bond wire 58 couples bond wire 26 to the outer lead fingers and allows for electrical connection to external connections or pins 60, as described in the aforementioned U.S. Patents.

本発明の別の実施例において、ボンドワイヤー26の代
わりに導電性バンプ54を使用して、第９図に示した如
く、ダイパッド20から導電層14へ導電性経路を与えてい
る。金、銅、又は半田等から構成することが可能なバン
プを形成し且つ当該技術において公知のテープ自動化ボ
ンディング（TAB）プロセスによって一体化させる。該
バンプを使用することは、ボンドワイヤーの為に必要と
される空間を減少させる。ボンドワイヤーを除去する効
果として、本組立体は一層小型のパッケージを与えてお
り且つ比較的高いリード数とすることを可能としてい
る。何故ならば、従来技術における如くモールドした包
囲体による物理的な空間制限がないからである。In another embodiment of the present invention, conductive bumps 54 are used in place of bond wires 26 to provide a conductive path from die pad 20 to conductive layer 14, as shown in FIG. Bumps, which may be comprised of gold, copper, solder, or the like, are formed and integrated by a tape automated bonding (TAB) process known in the art. Using the bumps reduces the space required for bond wires. As an effect of removing the bond wires, the present assembly provides a smaller package and allows for a relatively high lead count. This is because there is no physical space limitation due to the molded enclosure as in the prior art.

第10図を参照とすると、本発明の半導体装置パッケー
ジの分解図が、垂直寸法を持っており、例えば約60ミリ
インチとすることが可能である本体フレーム40、及びエ
ポキシー封止本体52をそれらがワイヤーボンド可能なテ
ープに関連して示している。該組立体は、半導体要素を
取り巻くモールドしたパッケージを包含しておらず、ま
た、電気的に導電性の経路の一部である導電性のパター
ン化したリードフレームを組み込んではいない。本発明
の本体フレーム乃至はパッケージフレームは、半導体装
置の周りにパッケージをモールドする為の必要性を取り
除いており且つプラスチック乃至は非導電性物質から形
成することが可能である。該本体フレームは、半導体装
置の構成要素に所望の保護を与えるエポキシー封止本体
を収納する為に使用されている。Referring to FIG. 10, an exploded view of a semiconductor device package of the present invention includes a body frame 40 having a vertical dimension, which can be, for example, about 60 milliinches, and an epoxy-sealed body 52. Shown in connection with wire bondable tape. The assembly does not include a molded package surrounding the semiconductor element and does not incorporate a conductive patterned lead frame that is part of an electrically conductive path. The body frame or package frame of the present invention eliminates the need to mold the package around the semiconductor device and can be formed from plastic or a non-conductive material. The body frame is used to house an epoxy-sealed body that provides desired protection to components of the semiconductor device.

ここにおける説明は単一のユニットの処理に関するも
のであるが、本プロセスは複数個のユニットを同時的に
処理する為に適用可能であることを理解すべきである。
また、本発明は、ここに特定した物質及びパラメータに
制限されるべきものではなく、本発明の範囲内において
修正を行うことが可能である。Although the description herein relates to processing of a single unit, it should be understood that the process is applicable for processing multiple units simultaneously.
Also, the invention is not to be limited to the substances and parameters specified herein, but modifications may be made within the scope of the invention.

本パッケージ構成を実施する為の半導体装置パッケー
ジ及び方法についての新規な構成について開示した。本
新規なプラスチックパッケージは、モールドした包囲体
に対する必要性を取り除いており、著しく高さ及び全体
的な面積が減少されており、且つ改善した電気的性能及
び信頼性を実現している。間に導電性膜を有する導電性
層から例えばカプトンである絶縁性区域の剥離の問題は
事実上存在しない。湿気の侵入は効果的に最小とされて
いる。また、ダイ表面腐食の問題もない。A novel configuration of a semiconductor device package and a method for implementing the present package configuration has been disclosed. The new plastic package eliminates the need for a molded enclosure, has significantly reduced height and overall area, and provides improved electrical performance and reliability. The problem of delamination of the insulating area, for example Kapton, from the conductive layer with the conductive film in between is virtually nonexistent. Moisture ingress is effectively minimized. Also, there is no problem of die surface corrosion.

フロントページの続き (56)参考文献 特開 平２−502323（ＪＰ，Ａ) 特開 平１−503184（ＪＰ，Ａ) 特開 昭57−159052（ＪＰ，Ａ) 欧州公開4787（ＥＰ，Ａ１)Continuation of the front page (56) References JP-A-2-502323 (JP, A) JP-A-1-503184 (JP, A) JP-A-57-159052 (JP, A) European publication 4787 (EP, A1)

Claims (15)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】パターン化した絶縁層及び導電層を具備し
ており前記導電層が前記絶縁層の１表面へ一体化されて
いるダイ支持用基板、前記導電層の１表面へ固定した半
導体ダイ、前記パターン化した絶縁層とは反対側におい
て前記導電層へ一体化させた絶縁性要素、前記半導体ダ
イを前記導電層へ電気的に結合させる手段、前記導電層
へ一体化されており且つ前記半導体ダイ及び前記電気的
結合手段を取り囲んでいる本体フレーム、前記フレーム
上且つ前記ダイ及び前記電気的結合手段上で前記フレー
ム内に配置させた封止本体、を有する半導体装置パッケ
ージ。1. A die supporting substrate comprising a patterned insulating layer and a conductive layer, wherein the conductive layer is integrated with one surface of the insulating layer, and a semiconductor die fixed to one surface of the conductive layer. An insulating element integrated with the conductive layer on the side opposite the patterned insulating layer, means for electrically coupling the semiconductor die to the conductive layer, integrated with the conductive layer, and A semiconductor device package comprising: a body frame surrounding a semiconductor die and said electrical coupling means; and a sealing body disposed within said frame on said frame and on said die and said electrical coupling means. 【請求項２】特許請求の範囲第１項において、前記絶縁
層が可撓性物質から形成されている半導体装置パッケー
ジ。2. The semiconductor device package according to claim 1, wherein said insulating layer is formed of a flexible material. 【請求項３】特許請求の範囲第１項において、前記絶縁
層がカプトンから形成されている半導体装置パッケー
ジ。3. The semiconductor device package according to claim 1, wherein said insulating layer is formed of Kapton. 【請求項４】特許請求の範囲第１項において、前記導電
層が金鍍金から形成されている半導体装置パッケージ。4. The semiconductor device package according to claim 1, wherein said conductive layer is formed by gold plating. 【請求項５】特許請求の範囲第４項において、前記ダイ
及び前記ボンドワイヤー上に配設したシリコーンゲルを
有する半導体装置パッケージ。5. The semiconductor device package according to claim 4, further comprising a silicone gel disposed on said die and said bond wire. 【請求項６】特許請求の範囲第１項において、前記結合
手段がボンドワイヤーを有する半導体装置パッケージ。6. The semiconductor device package according to claim 1, wherein said coupling means has a bond wire. 【請求項７】特許請求の範囲第１項において、前記ボン
ドワイヤーへ結合されているリードフィンガー、及び外
部導電性リードへの接続の為に前記リードフィンガーへ
結合されている導電性ピンを有する半導体装置パッケー
ジ。7. The semiconductor of claim 1, wherein the semiconductor has a lead finger coupled to the bond wire and a conductive pin coupled to the lead finger for connection to an external conductive lead. Equipment package. 【請求項８】特許請求の範囲第１項において、前記電気
的結合手段が導電性バンプを有している半導体装置パッ
ケージ。8. The semiconductor device package according to claim 1, wherein said electric coupling means has conductive bumps. 【請求項９】特許請求の範囲第７項において、前記絶縁
性要素が背面要素であり、且つ前記本体フレームが前記
導電性リードを取り巻く前記背面要素へ接続されている
半導体装置パッケージ。9. The semiconductor device package according to claim 7, wherein said insulating element is a back element, and said main body frame is connected to said back element surrounding said conductive lead. 【請求項１０】特許請求の範囲第１項において、前記本
体フレームは前記パターン化した絶縁層の厚さよりも大
きな高さを有する半導体装置パッケージ。10. The semiconductor device package according to claim 1, wherein said main body frame has a height larger than a thickness of said patterned insulating layer. 【請求項１１】絶縁層をエッチングして所定のパターン
を画定し且つ前記絶縁層上にパターン化した導電層を付
着させることによって絶縁層を具備するパターン化した
ダイ支持用基板を形成し、前記ダイ支持用基板へ半導体
ダイを取り付け、前記ダイと前記導電層の間に電気的接
続部を形成し、前記導電層の背面へ絶縁要素を取り付
け、前記ダイ及び電気的接続部上に保護用絶縁被覆を付
着させ、前記ダイと電気的接続部と被覆とを取り巻いて
前記導電層及び絶縁要素の上部表面へ本体フレームを取
り付け、前記本体フレームと被覆とダイと電気的接続部
とを絶縁物質で封止する、上記各ステップを有する半導
体装置パッケージの製造方法。11. A patterned die support substrate comprising an insulating layer by etching the insulating layer to define a predetermined pattern and depositing a patterned conductive layer on the insulating layer. Attach a semiconductor die to a die support substrate, form an electrical connection between the die and the conductive layer, attach an insulating element to the back of the conductive layer, and provide a protective insulation over the die and the electrical connection. A coating is applied, and a body frame is attached to the upper surface of the conductive layer and the insulating element surrounding the die, the electrical connection and the coating, and the body frame, the coating, the die and the electrical connection are made of an insulating material. A method of manufacturing a semiconductor device package having the above steps for sealing. 【請求項１２】特許請求の範囲第11項において、前記ダ
イをダイ取り付けエポキシーによって前記テープへ取り
付け且つ１時間以内の間150℃の温度で硬化させる方
法。12. The method of claim 11, wherein said die is attached to said tape by a die attach epoxy and cured at a temperature of 150 ° C. for no more than one hour. 【請求項１３】特許請求の範囲第11項において、前記ダ
イと前記導電層の間に電気的接続部を形成する前記ステ
ップが、ボンディングワイヤの一端を前記ダイへ且つ他
端を前記パターン化した導電層の導電性リードへサーモ
ソニックボンディングによっでボンディングさせる方
法。13. The method of claim 11, wherein the step of forming an electrical connection between the die and the conductive layer comprises the step of patterning one end of a bonding wire to the die and the other end thereof. A method of bonding to a conductive lead of a conductive layer by thermosonic bonding. 【請求項１４】特許請求の範囲第11項において、前記保
護用被覆を付着するステップが、前記ダイ及び電気的接
続部上を流動すべくシリコーンゲルを付与し且つ該ゲル
被覆を硬化させることを包含する方法。14. The method of claim 11, wherein the step of applying the protective coating comprises applying a silicone gel to flow over the die and the electrical connection and curing the gel coating. How to include. 【請求項１５】特許請求の範囲第11項において、本体フ
レーム接着剤を前記導電性リード上の前記絶縁性要素へ
流動させるステップを有する方法。15. The method of claim 11, further comprising the step of flowing a body frame adhesive to said insulating element on said conductive leads.
JP1500158A 1987-10-30 1988-10-26 Semiconductor device package and method of manufacturing the same Expired - Lifetime JP2664259B2 (en)

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US115,228 1987-10-30

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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
FR2651923B1 (en) * 1989-09-14 1994-06-17 Peugeot INTEGRATED POWER CIRCUIT.
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5831836A (en) * 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
JP3461204B2 (en) * 1993-09-14 2003-10-27 株式会社東芝 Multi-chip module
KR0139694B1 (en) * 1994-05-11 1998-06-01 문정환 Method of manufacturing semiconductor using solder ball and manufacture method
FR2738077B1 (en) * 1995-08-23 1997-09-19 Schlumberger Ind Sa ELECTRONIC MICRO-BOX FOR ELECTRONIC MEMORY CARD AND EMBODIMENT PROCESS
JP3435271B2 (en) * 1995-11-30 2003-08-11 三菱電機株式会社 Semiconductor device
DE19602436B4 (en) * 1996-01-24 2006-09-14 Infineon Technologies Ag Method for mounting a frame on a carrier material and device for carrying out the method
AR015977A1 (en) 1997-10-23 2001-05-30 Genencor Int PROTEASA VARIANTS MULTIPLY SUBSTITUTED WITH ALTERED NET LOAD FOR USE IN DETERGENTS
US6835550B1 (en) 1998-04-15 2004-12-28 Genencor International, Inc. Mutant proteins having lower allergenic response in humans and methods for constructing, identifying and producing such proteins
FR2798000B1 (en) * 1999-08-27 2002-04-05 St Microelectronics Sa METHOD FOR PACKAGING A CHIP WITH PARTICULARLY OPTICAL SENSORS AND SEMICONDUCTOR DEVICE OR PACKAGE CONTAINING SUCH A CHIP
CA2472723C (en) 2002-01-16 2013-12-17 Genencor International, Inc. Multiply-substituted protease variants
DK1483581T3 (en) 2002-02-26 2008-03-17 Genencor Int Population-based assessments and agents for ranking the relative immunogenicity of proteins
EP2500423B1 (en) 2003-02-26 2015-06-17 Danisco US Inc. Amylases producing an altered immunogenic response and methods of making and using the same
US7985569B2 (en) 2003-11-19 2011-07-26 Danisco Us Inc. Cellulomonas 69B4 serine protease variants
EP1694847B1 (en) 2003-11-19 2012-06-13 Danisco US Inc. Serine proteases, nucleic acids encoding serine enzymes and vectors and host cells incorporating same
EP1831362B1 (en) 2004-12-30 2011-10-26 Genencor International, Inc. Acid fungal proteases
BR112015025989A8 (en) 2014-11-12 2020-01-14 Intel Corp flexible packaging system solutions for trackable devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3711625A (en) * 1971-03-31 1973-01-16 Microsystems Int Ltd Plastic support means for lead frame ends
FR2205800B1 (en) * 1972-11-09 1976-08-20 Honeywell Bull Soc Ind
US4089733A (en) * 1975-09-12 1978-05-16 Amp Incorporated Method of forming complex shaped metal-plastic composite lead frames for IC packaging
US4216577A (en) * 1975-12-31 1980-08-12 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Portable standardized card adapted to provide access to a system for processing electrical signals and a method of manufacturing such a card
US4218701A (en) * 1978-07-24 1980-08-19 Citizen Watch Co., Ltd. Package for an integrated circuit having a container with support bars
FR2439478A1 (en) * 1978-10-19 1980-05-16 Cii Honeywell Bull FLAT HOUSING FOR DEVICES WITH INTEGRATED CIRCUITS
US4380042A (en) * 1981-02-23 1983-04-12 Angelucci Sr Thomas L Printed circuit lead carrier tape
US4472876A (en) * 1981-08-13 1984-09-25 Minnesota Mining And Manufacturing Company Area-bonding tape
DE3222791A1 (en) * 1982-06-18 1983-12-22 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS
FI72409C (en) * 1984-03-09 1987-05-11 Lohja Ab Oy FOERFARANDE FOER INKAPSLING AV PAO EN BAERREMSA ANORDNADE HALVLEDARKOMPONENTER.

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KR890702249A (en) 1989-12-23
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WO1989004552A1 (en) 1989-05-18
JPH03503342A (en) 1991-07-25

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