JP3455116B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3455116B2 JP3455116B2 JP29449498A JP29449498A JP3455116B2 JP 3455116 B2 JP3455116 B2 JP 3455116B2 JP 29449498 A JP29449498 A JP 29449498A JP 29449498 A JP29449498 A JP 29449498A JP 3455116 B2 JP3455116 B2 JP 3455116B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- semiconductor device
- element mounting
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子及び内
部リードを片面で樹脂封止する半導体装置の製造方法に
関し、特に封止樹脂の底面部位に内部リードの外部実装
面が露出した樹脂封止型半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor element and an internal lead are sealed on one side with a resin, and in particular, a resin seal in which an external mounting surface of the internal lead is exposed at a bottom surface portion of a sealing resin. Type semiconductor device manufacturing method.
【０００２】[0002]
【従来の技術】従来、ＩＣ、ＬＳＩ等の半導体装置の実
装は、外周縁に沿ってＪ型、Ｉ型あるいはガルウイング
型等の形状に成形された複数の内部リードを突出させ、
この内部リードをプリント基板等の上に形成された配線
パターンの接続パッドに半田等を用いて接続していた。
しかし、この方法では、半導体装置から内部リードが外
周に突出する部分が比較的広い面積を占め、半導体装置
の小型化に対応できなかった。そこで、例えば、特開平
８−３１６３７１号公報には、半導体素子、半導体素子
搭載部、内部リード等を樹脂で封止した半導体装置の底
面部位に外部実装面となる内部リードの一部又は全部を
露出したＳＯＮ（Small Outline Non-lead Package）や
ＱＦＮ（Quad Flat Non-lead Package）と呼ばれている
半導体装置が提案されている。この半導体装置を形成す
るための樹脂封止金型は、内部リードと半導体素子搭載
部が同一平面上に配置されたＳＯＮ型の半導体装置の例
について説明すると、例えば図５（Ａ）に示すように、
封止樹脂を充填する空間を形成するキャビティ５１及び
その周囲に形成された上型パーティング面５２Ａを備え
た上型５２と、上型パーティング面５２Ａに対面する平
板状の下型パーティング面５３Ａを備えた下型５３とか
ら構成されている。2. Description of the Related Art Conventionally, when mounting a semiconductor device such as an IC or an LSI, a plurality of internal leads formed in a J-shaped, I-shaped, or gull-wing type along an outer peripheral edge are projected,
This internal lead is connected to a connection pad of a wiring pattern formed on a printed circuit board or the like by using solder or the like.
However, according to this method, the portion where the internal lead projects from the semiconductor device to the outer periphery occupies a relatively large area, and it is not possible to cope with the miniaturization of the semiconductor device. Therefore, for example, in Japanese Unexamined Patent Application Publication No. 8-316371, a part or all of an internal lead to be an external mounting surface is provided on a bottom surface portion of a semiconductor device in which a semiconductor element, a semiconductor element mounting portion, an internal lead and the like are sealed with resin. A semiconductor device called an exposed SON (Small Outline Non-lead Package) or a QFN (Quad Flat Non-lead Package) has been proposed. An example of a SON type semiconductor device in which internal leads and a semiconductor element mounting portion are arranged on the same plane will be described as the resin sealing mold for forming this semiconductor device. For example, as shown in FIG. To
An upper mold 52 having the upper mold parting surface 52A formed in the cavity 51 and the periphery thereof to form a space filled with a sealing resin, flat bottom parting surface facing the upper mold parting surface 52A The lower die 53 is provided with 53A.
【０００３】半導体装置を製造する方法は、まず、半導
体素子搭載部６１とその周辺に配列された内部リード６
２とこれを支持する支持枠６３を備えた導体回路パター
ン６４を複数連接した導体回路ユニットフレーム６５を
準備する。次に、導体回路ユニットフレーム６５の各半
導体素子搭載部６１に半導体素子６６を搭載し、半導体
素子６６のパッド部とそれに対応する内部リード６２の
一方の先端部をボンディングワイヤ６７により接続し
て、電気的導通回路を形成された半導体素子搭載ユニッ
トフレーム６８を形成する。次に、上型５２と、下型５
３との組み合わせからなる片面樹脂封止金型５０内に半
導体素子搭載ユニットフレーム６８を載置し、上型パー
ティング面５２Ａと下型パーティング面５３Ａとで半導
体素子搭載ユニットフレーム６８を押圧固定して、内部
リード６２の下面に形成された外部実装面６２Ａ（図５
（Ｃ）参照）を下方に押し付けた状態で、キャビティ５
１内に封止樹脂５４を注入し、図５（Ｂ）に示すよう
に、外部実装面６２Ａが封止樹脂５４の底面部位に露出
した半導体素子パッケージユニットフレーム６９を形成
する。最後に、樹脂封止工程で形成された半導体素子パ
ッケージユニットフレーム６９の樹脂封止領域から外側
に突出した内部リード６２を切断し、図５（Ｂ）に示す
ように、各半導体素子パッケージユニットフレーム６９
の外周周辺部で半導体装置６０を個々に分離形成する。
この半導体装置６０によれば、外部実装面６２Ａを備え
た内部リード６２は半導体装置６０の外周から殆ど突出
することがなくなり、内部リード６２の下面に形成され
た外部実装面６２Ａは半導体装置６０の封止樹脂５４の
底面部位に露出しているので、半導体装置６０の小型化
が可能になる。また、外部実装面６２Ａにそれぞれ対応
して設けたプリント基板上の接続パッドに半導体装置６
０を位置決めして載置した後、加熱により溶融性の半田
等をリフローすることにより、全ての外部実装面６２Ａ
を接続パッドに同時に接続できるので、半導体装置６０
の実装工程が極めて簡単になる利点がある。In a method of manufacturing a semiconductor device, first, a semiconductor element mounting portion 61 and internal leads 6 arranged around it.
A conductor circuit unit frame 65 in which a plurality of conductor circuit patterns 64 including two and a supporting frame 63 for supporting the two are connected is prepared. Next, the semiconductor element 66 is mounted on each semiconductor element mounting portion 61 of the conductor circuit unit frame 65, and the pad portion of the semiconductor element 66 and one end portion of the corresponding inner lead 62 are connected by the bonding wire 67, A semiconductor element mounting unit frame 68 having an electrically conductive circuit is formed. Next, the upper mold 52 and the lower mold 5
The semiconductor element mounting unit frame 68 is placed on one side resin sealing mold 50, which consist of a combination of 3, upper die par
The semiconductor element mounting unit frame 68 is pressed and fixed by the coating surface 52A and the lower mold parting surface 53A, and the external mounting surface 62A formed on the lower surface of the internal lead 62 (see FIG. 5).
(See (C)), the cavity 5 is pressed downward.
The encapsulating resin 54 is injected into the semiconductor device 1 to form the semiconductor element package unit frame 69 in which the external mounting surface 62A is exposed at the bottom surface portion of the encapsulating resin 54, as shown in FIG. 5B. Finally, the internal leads 62 protruding outward from the resin sealing region of the semiconductor element package unit frame 69 formed in the resin sealing step are cut, and as shown in FIG. 69
The semiconductor devices 60 are individually formed in the periphery of the periphery of the semiconductor device 60.
According to this semiconductor device 60, the inner lead 62 having the outer mounting surface 62A hardly protrudes from the outer circumference of the semiconductor device 60, and the outer mounting surface 62A formed on the lower surface of the inner lead 62 does not protrude from the semiconductor device 60. Since it is exposed at the bottom surface portion of the sealing resin 54, the semiconductor device 60 can be downsized. Further, the semiconductor device 6 is connected to the connection pads on the printed circuit board provided corresponding to the external mounting surfaces 62A, respectively.
After mounting and positioning 0, reflowing the fusible solder etc. by heating, all external mounting surface 62A
Can be simultaneously connected to the connection pad, the semiconductor device 60
There is an advantage that the mounting process of is extremely simple.
【０００４】[0004]
【発明が解決しようとする課題】ところが、ＳＯＮ型や
ＱＦＮ型の半導体装置の片面樹脂封止に用いる片面樹脂
封止金型では、上型パーティング面のパーティング領域
は、キャビティ内にある半導体素子搭載ユニットフレー
ムの部分を除く領域に、一方下型パーティング面のパー
ティング領域は半導体素子搭載ユニットフレームの下面
側の略全域面に圧接する構成となっている。そのため、
未だ解決すべき次のような問題があった。（１）内部リ
ード６２と半導体素子搭載部６１が同一平面上に配置さ
れたＳＯＮ型、ＱＦＮ型の半導体装置６０では、半導体
素子搭載ユニットフレーム６８に圧接する下型パーティ
ング面５３Ａのパーティング領域に対して上型パーティ
ング面５２Ａのパーティング領域が狭くなっている。そ
のため、上型パーティング面５２Ａ及び下型パーティン
グ面５３Ａが半導体素子搭載ユニットフレーム６８の上
面及び下面を圧接すると、図５（Ｃ）に示すように、内
部リード６２の先端部分が矢印Ｄ１の方向に持ち上げら
れてキャビティ５１内のリード先端部６２Ｂと下型パー
ティング面５３Ａとの境界に隙間Ｇ１が生じ、この隙間
Ｇ１に封止樹脂５４が流入することがある。この封止樹
脂５４の流入圧力により、内部リード６２のリード先端
部６２Ｂがさらに押し上げられ、隙間Ｇ１がさらに広が
り、内部リード６２の外部実装面６２Ａに封止樹脂５４
が付着し、内部リード６２の外部実装面６２Ａとプリン
ト基板の接合パッドのボンディング領域が狭くなり半田
接合不良が発生する。However, in a single-sided resin sealing mold used for single-sided resin sealing of a SON type or QFN type semiconductor device, the parting region on the upper parting surface is a semiconductor located inside the cavity. in a region excluding a portion of the element mounting unit frame, whereas par of the lower mold parting surface
The toning region is configured to come into pressure contact with the substantially entire surface of the lower surface side of the semiconductor element mounting unit frame. for that reason,
There were still the following problems to be solved. (1) In the SON type or QFN type semiconductor device 60 in which the inner lead 62 and the semiconductor element mounting portion 61 are arranged on the same plane, in the SON type and QFN type semiconductor device 60, the lower-type party that is pressed against the semiconductor element mounting unit frame 68
Upper die party against parting region of the ring surface 53A
Parting region of the ring surface 52A is narrow. Therefore, the upper mold parting surface 52A and lower mold Partin
When the upper surface and the lower surface of the semiconductor element mounting unit frame 68 are pressed against each other by the ring surface 53A, as shown in FIG. 5 (C), the tip portion of the internal lead 62 is lifted in the direction of arrow D1 and the tip portion of the lead inside the cavity 51 is lifted. 62B and lower mold par
A gap G1 may be formed at the boundary with the coating surface 53A, and the sealing resin 54 may flow into the gap G1. Due to the inflow pressure of the sealing resin 54, the lead tip portion 62B of the internal lead 62 is further pushed up, the gap G1 is further expanded, and the sealing resin 54 is applied to the external mounting surface 62A of the internal lead 62.
And the bonding area between the external mounting surface 62A of the internal lead 62 and the bonding pad of the printed circuit board becomes narrow, resulting in defective solder bonding.
【０００５】（２）また、図６（Ａ）、（Ｂ）、（Ｃ）
に示すように、内部リード７２の第１の平坦部の外部実
装面７２Ａと、これに平行に形成された第２の平坦部の
ボンディング領域面７２Ｃと、第１の平坦部の外部実装
面７２Ａと第２の平坦部のボンディング領域面７２Ｃと
を接続する傾斜部７２Ｄとを備えたＳＯＮ型、ＱＦＮ型
の半導体装置７０においては、支持枠７１に連結されて
いる内部リード７２の先端部と半導体素子７３を搭載す
るための半導体素子搭載部７４の高さが異なる半導体素
子搭載ユニットフレーム７８の場合は、上記（１）で説
明した現象の外に、傾斜部７２Ｄが折り曲げ加工によっ
て成形されるため、第１の平坦部と傾斜部７２Ｄとの境
界部に曲げ加工時の引っ張り応力により、前記第１の平
坦部の板厚が引き込まれた薄肉部と曲面、すなわちＲ部
７２Ｂが形成される。このため、第１の平坦部の平坦度
が損なわれると共に、樹脂封止の際、第１の平坦部と封
止樹脂５４との境界部に位置するＲ部７２Ｂと下型パー
ティング面５３Ａとの間に隙間Ｇ２が生じ、更に封止樹
脂５４が流入して、図６（Ｂ）に示すように、Ｒ部７２
Ｂが矢印Ｄ２の方向に持ち上げられ、第１の平坦部の外
部実装面７２Ａに封止樹脂５４が付着し、（１）と同様
に、第１の平坦部の外部実装面７２Ａとプリント基板の
接合パッドとの間の半田接合不良が発生する。上記半田
接合不良を解消するために、外部実装面を樹脂封止領域
の境界に隣接もしくは樹脂封止領域に設けると共に、外
部実装面に付着した封止樹脂を除去する必要があり、生
産効率の低下、半導体装置の小型化の隘路となってい
た。本発明はかかる事情に鑑みてなされたもので、内部
リードの外部実装面への封止樹脂の流れ出しを防止し、
内部リードの外部実装面とプリント基板の接合パッドの
半田接合不良を防いで実装不良を低減できる半導体装置
の製造方法を提供することを目的とする。また、他の目
的は、所要の外部実装面７２Ａを確保し、外部実装面７
２Ａを半導体素子側に隣接させて半導体装置の小型化を
可能にする半導体装置の製造方法を提供することを目的
とする。(2) Further, FIGS. 6 (A), 6 (B) and 6 (C)
As shown in FIG. 7, the outer mounting surface 72A of the first flat portion of the inner lead 72, the bonding area surface 72C of the second flat portion formed in parallel therewith, and the outer mounting surface 72A of the first flat portion. In the SON type and QFN type semiconductor device 70 including the inclined portion 72D connecting the bonding area surface 72C of the second flat portion and the semiconductor device 70 of the SON type and the QFN type, the tip of the inner lead 72 connected to the support frame 71 and the semiconductor In the case of the semiconductor element mounting unit frame 78 in which the height of the semiconductor element mounting portion 74 for mounting the element 73 is different, in addition to the phenomenon described in (1) above, the inclined portion 72D is formed by bending. , The thin portion and the curved surface, that is, the R portion 72B, in which the plate thickness of the first flat portion is drawn due to the tensile stress during bending, are formed at the boundary portion between the first flat portion and the inclined portion 72D. . Therefore, the flatness of the first flat portion is impaired, when the resin sealing, R portion 72B and the lower mold par located at the boundary between the first flat portion and the sealing resin 54
A gap G2 is formed between the sealing surface 54A and the coating surface 53A, the sealing resin 54 further flows in, and as shown in FIG.
B is lifted in the direction of arrow D2, the sealing resin 54 is attached to the external mounting surface 72A of the first flat portion, and the external mounting surface 72A of the first flat portion and the printed circuit board are attached in the same manner as (1). A solder joint failure with the joint pad occurs. In order to eliminate the solder joint failure, it is necessary to provide the external mounting surface adjacent to the boundary of the resin sealing area or in the resin sealing area and to remove the sealing resin attached to the external mounting surface. It was a bottleneck for the decrease and downsizing of semiconductor devices. The present invention has been made in view of such circumstances, and prevents the sealing resin from flowing out to the external mounting surface of the internal lead,
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can prevent a solder joint failure between an external mounting surface of an inner lead and a joint pad of a printed board and reduce the mounting failure. Another purpose is to secure the required external mounting surface 72A,
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which 2A is adjacent to the semiconductor element side and the size of the semiconductor device can be reduced.
【０００６】[0006]
【課題を解決するための手段】前記目的に沿う本発明に
係る半導体装置の製造方法は、導体回路パターンを複数
連接した導体回路ユニットフレームの外部実装面を除く
裏面側に、弾力性を有する絶縁皮膜層を形成した半導体
素子搭載ユニットフレームを、複数の封止樹脂充填キャ
ビティ及びその周囲に形成された上型パーティング面を
備えた上型と、前記上型パーティング面に対面する下型
パーティング面を備えた下型との組み合わせからなる片
面樹脂封止金型内に載置し、前記上型パーティング面と
下型パーティング面とで前記半導体素子搭載ユニットフ
レームを圧接固定して、前記絶縁皮膜層を介して内部リ
ードを押し付けた状態で、前記封止樹脂充填キャビティ
内に封止樹脂を注入して、前記外部実装面が前記封止樹
脂の底面部位に露出した半導体素子パッケージユニット
フレームを形成する。According to the method of manufacturing a semiconductor device according to the present invention for achieving the above object, there is provided a flexible insulation on a rear surface side of a conductor circuit unit frame in which a plurality of conductor circuit patterns are connected, excluding an outer mounting surface. An upper die having a plurality of sealing resin-filled cavities and an upper die parting surface formed around the cavity and a lower die facing the upper die parting surface
It is placed in a single-sided resin-sealed mold consisting of a combination with a lower mold having a parting surface, and the semiconductor element mounting unit frame is fixed by pressure contact with the upper mold parting surface and the lower mold parting surface. A semiconductor element package in which the external mounting surface is exposed at a bottom surface portion of the sealing resin by injecting a sealing resin into the sealing resin-filled cavity in a state where the internal lead is pressed through the insulating film layer. Form a unit frame.
【０００７】このような製造方法によれば、導体回路ユ
ニットフレームの外部実装面を除く裏面に、弾力性を有
する絶縁皮膜層を形成しているので、内部リード、支持
枠及び半導体素子搭載部の周辺は全て絶縁皮膜層で被覆
される。また、上型パーティング面と下型パーティング
面が半導体素子搭載ユニットフレームの上面及び下面を
圧接すると、半導体素子搭載ユニットフレームの上面は
上型パーティング面に圧接し、絶縁皮膜層が内部リード
及び支持枠に押しつけられて、更に絶縁皮膜層が内部リ
ードと支持枠の周辺に密着する。したがって、封止樹脂
充填キャビティの周囲は全て封じ込まれた状態となり、
封止樹脂充填キャビティの中に注入された封止樹脂が内
部リードと下型パーティング面との間に流入する隙間は
生じない。また、一端部が上方にディプレスされた内部
リードの封止樹脂との境界部に位置する箇所にＲ部が形
成される場合についても、同様に内部リードの一端部
（ディプレス成形部を除く）、支持枠及び半導体素子搭
載部の周辺は全て絶縁皮膜層で被覆され、封止樹脂充填
キャビティ内のＲ部を有する他端部と下型パーティング
面との境界は絶縁皮膜層で被覆されるので、封止樹脂が
内部リードの他端部側に流入する隙間は生じない。According to such a manufacturing method, since the insulating film layer having elasticity is formed on the rear surface of the conductor circuit unit frame excluding the outer mounting surface, the inner leads, the support frame and the semiconductor element mounting portion are formed. The entire periphery is covered with an insulating film layer. Also, the upper mold parting surface and the lower mold parting
When the upper surface and the lower surface of the semiconductor element mounting unit frame are pressed against each other, the upper surface of the semiconductor element mounting unit frame is pressed against the upper parting surface , and the insulating coating layer is pressed against the inner lead and the supporting frame, and the insulating coating layer is further pressed. Adheres to the inner leads and the periphery of the support frame. Therefore, the circumference of the sealing resin filled cavity is completely enclosed,
There is no gap in which the sealing resin injected into the sealing resin filled cavity flows between the inner lead and the lower mold parting surface . Also, in the case where the R portion is formed at the position where the one end is located at the boundary with the sealing resin of the inner lead depressed upward, one end of the inner lead (excluding the depress molding portion) is similarly formed. ), The periphery of the support frame and the semiconductor element mounting portion are all covered with an insulating film layer, and the other end having the R portion in the sealing resin filled cavity and the lower part parting
Since the boundary with the surface is covered with the insulating film layer, there is no gap in which the sealing resin flows into the other end of the internal lead.
【０００８】ここで、片面樹脂封止金型は、前記上型パ
ーティング面と、これに対応し、前記上型パーティング
面より幅狭の凸形状の環状突起を設けた下型パーティン
グ面とを備えてもよい。この場合、上型パーティング面
と下型パーティング面が半導体素子搭載ユニットフレー
ムを圧接すると、環状突起の外側の内部リードが押し下
げられて、封止樹脂充填キャビティ内の内部リードの他
端部がさらに絶縁皮膜層に密着し、封止樹脂が内部リー
ドの他端部側に流入する隙間が生じることはない。ま
た、前記絶縁皮膜層には、前記外部実装面が露出する接
続用開口部を形成してもよい。この場合、接続用開口部
を介して外部実装面を外部接続端子に簡単に接続するこ
とができる。なお、内部リードの外部実装面が露出する
が、内部リード及び支持枠のそれぞれ周辺が絶縁皮膜層
によって覆われるので、封止樹脂充填キャビティの中に
注入された封止樹脂が内部リードと下型パーティング面
との間に流入する隙間は生じない。[0008] Here, one side resin sealing mold, the upper mold Pas
Parting surface and corresponding to the upper mold parting
Lower mold party with a convex annular protrusion narrower than the surface
May be provided. In this case, when the upper mold parting surface and the lower mold parting surface are brought into pressure contact with the semiconductor element mounting unit frame, the inner leads outside the annular protrusion are pushed down, and the inner leads inside the sealing resin-filled cavity are pushed down. The other end portion further adheres to the insulating film layer, and no gap is formed in which the sealing resin flows into the other end portion side of the internal lead. Further, the insulating coating layer may be formed with a connection opening for exposing the external mounting surface. In this case, the external mounting surface can be easily connected to the external connection terminal via the connection opening. Although the external mounting surface of the inner lead is exposed, the periphery of the inner lead and the support frame are covered with the insulating film layer, so that the sealing resin injected into the sealing resin filled cavity is sealed with the inner lead and the lower mold. There is no inflow gap between it and the parting surface .
【０００９】また、外部実装面が露出した接続用開口部
にソルダーボール又はバンプを接続して外部接続端子を
形成してもよい。この場合、内部リードの外部実装面に
確実に半田を載せることができ、半田接合不良を防ぐこ
とができる。更に、前記絶縁皮膜層は、ポリイミド系樹
脂又はポリエチレン系樹脂中にＳｉＣ、酸化珪素、酸化
アルミニュームの酸化物の微粉末を均一に分散させた混
合樹脂から形成してもよい。この場合、絶縁皮膜層は熱
変形温度及び耐熱強度が高いポリイミド系樹脂又はポリ
エチレン系樹脂等の熱硬化性樹脂を使用しているので、
封止樹脂を片面樹脂封止金型に注入したとき、封止樹脂
の成形時の熱によって絶縁皮膜層が溶融して破損するよ
うなことはない。Further, external connection terminals may be formed by connecting solder balls or bumps to the connection openings where the external mounting surface is exposed. In this case, the solder can be surely placed on the outer mounting surface of the inner lead, and the solder joint failure can be prevented. Furthermore, the insulating film layer, SiC in the polyimide-based resin or polyethylene-based resin, silicon oxide, may be formed from a fine powder uniformly dispersed was mixed resin of oxides of aluminum oxide, New arm. In this case, since the insulating film layer uses a thermosetting resin such as a polyimide resin or a polyethylene resin having high heat distortion temperature and heat resistance,
When the sealing resin is injected into the one-sided resin sealing die, the insulating coating layer is not melted and damaged by the heat during the molding of the sealing resin.
【００１０】[0010]
【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図１（Ａ）、（Ｂ）、
（Ｃ）はそれぞれ本発明の第１の実施の形態に係る半導
体装置の製造方法の樹脂封止工程を示す側断面図、同樹
脂封止工程でのリード部分の拡大側断面図、同半導体素
子パッケージ分離工程を示す側断面図、図２（Ａ）、
（Ｂ）、（Ｃ）、（Ｄ）はそれぞれ本発明の第１の実施
の形態に係る半導体装置の製造方法の形状加工工程を示
す平面図、同形状加工工程を示す側断面図、同弾力性皮
膜形成工程を示す側断面図、同半導体素子搭載工程を示
す側断面図、図３（Ａ）、（Ｂ）、（Ｃ）はそれぞれ本
発明の第２の実施の形態に係る半導体装置の製造方法の
樹脂封止工程を示す側断面図、同樹脂封止工程でのリー
ド部分の拡大側断面図、同半導体素子パッケージ分離工
程後の状態を示す側断面図、図４（Ａ）、（Ｂ）、
（Ｃ）はそれぞれ本発明の第３の実施の形態に係る半導
体装置の製造方法の樹脂封止工程を示す側断面図、同樹
脂封止工程でのリード部分の拡大側断面図、同半導体素
子パッケージ分離工程後の状態を示す側断面図である。BEST MODE FOR CARRYING OUT THE INVENTION Next, referring to the attached drawings, an embodiment in which the present invention is embodied will be described to provide an understanding of the present invention. Here, FIG. 1 (A), (B),
FIG. 3C is a side sectional view showing a resin encapsulating step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, an enlarged side sectional view of a lead portion in the resin encapsulating step, and a semiconductor element, respectively. FIG. 2A is a side sectional view showing the package separation process.
(B), (C) and (D) are respectively a plan view showing a shape processing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, a side sectional view showing the same shape processing step, and an elastic force. 3A, 3B, and 3C are cross-sectional views of a semiconductor device according to a second embodiment of the present invention, respectively, showing a conductive film forming step and a semiconductor element mounting step. 4A is a side sectional view showing a resin sealing step of the manufacturing method, an enlarged side sectional view of a lead portion in the resin sealing step, a side sectional view showing a state after the semiconductor element package separating step, FIG. B),
(C) is a side sectional view showing a resin encapsulating step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention, an enlarged side sectional view of a lead portion in the resin encapsulating step, and a semiconductor element, respectively. It is a sectional side view showing a state after a package separation process.
【００１１】図１（Ａ）、（Ｂ）、（Ｃ）、図２
（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）に示すように、本発明
の第１の実施の形態に係る半導体装置の製造方法は、内
部リードと半導体素子搭載部が同一平面上に配置された
ＳＯＮ型、ＱＦＮ型の半導体装置を例に取り上げ、次に
説明する工程の順序で進める。
（１）まず、形状加工工程で、図２（Ａ）、（Ｂ）に示
すように、銅系合金や鉄系合金などの金属条材からエッ
チング加工又はプレス加工によって、半導体素子搭載部
１２と、その周辺に配列された内部リード１１と、これ
を支持する支持枠１３とを備えた導体回路パターン１４
を形成し、その導体回路パターン１４が複数個、一体的
に連接した導体回路ユニットフレーム１５を形成する。
（２）弾力性皮膜形成工程では、図２（Ｃ）に模式図的
に示すように、導体回路ユニットフレーム１５に形成さ
れた内部リード１１の外部実装面１１Ａを除く裏面側
に、弾力性を有する絶縁皮膜層１６を設けた半導体素子
搭載基板フレーム１５Ａを形成する。すなわち、例えば
２０〜１００μｍ程度の厚みの樹脂製テープあるいは樹
脂フィルムからなる絶縁皮膜層１６の内部リード１１の
外部実装面１１Ａに接触する部分に孔を開けておいて、
絶縁皮膜層１６を導体回路ユニットフレーム１５の外部
実装面１１Ａ側に、例えば１０〜３０μｍ程度の厚みの
接着剤で接着し、絶縁皮膜層１６に外部実装面１１Ａが
露出するヴィアホールと呼ばれている接続用開口部１６
Ａを形成する。この絶縁皮膜層１６は、耐熱性の高いポ
リイミド系樹脂又はポリエチレン系樹脂からなる熱硬化
性樹脂中にＳｉＣ、酸化珪素、酸化アルミニューム等の
酸化物の微粉末を均一に分散させた混合樹脂を使用して
いる。なお、絶縁皮膜層１６は、弾力性のあるカバーレ
ジスト層あるいはソルダーレジスト層を用いてもよい。1 (A), (B), (C) and FIG.
As shown in (A), (B), (C), and (D), in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, the internal lead and the semiconductor element mounting portion are on the same plane. Taking the SON type semiconductor device and the QFN type semiconductor device arranged as an example, the steps will be described in the following order. (1) First, in a shaping step, as shown in FIGS. 2A and 2B, a semiconductor element mounting portion 12 is formed by etching or pressing a metal strip material such as a copper-based alloy or an iron-based alloy. , A conductor circuit pattern 14 including inner leads 11 arranged around the inner leads 11 and a support frame 13 supporting the inner leads 11.
And a plurality of the conductor circuit patterns 14 are integrally connected to form a conductor circuit unit frame 15. (2) In the elastic film forming step, as shown schematically in FIG. 2 (C), the inner leads 11 formed on the conductor circuit unit frame 15 are provided with elasticity on the back surface side except the outer mounting surface 11A. The semiconductor element mounting substrate frame 15A provided with the insulating coating layer 16 is formed. That is, for example, a hole is formed in a portion of the insulating coating layer 16 made of a resin tape or a resin film having a thickness of about 20 to 100 μm, which is in contact with the external mounting surface 11A of the inner lead 11.
The insulating coating layer 16 is adhered to the external mounting surface 11A side of the conductor circuit unit frame 15 with an adhesive having a thickness of, for example, about 10 to 30 μm, and is called a via hole in which the external mounting surface 11A is exposed to the insulating coating layer 16. Connection opening 16
Form A. The insulating film layer 16 is a mixed resin in which fine powder of oxide such as SiC, silicon oxide, and aluminum oxide is uniformly dispersed in a thermosetting resin made of polyimide resin or polyethylene resin having high heat resistance. I'm using it. The insulating film layer 16 may be a cover resist layer or a solder resist layer having elasticity.
【００１２】（３）半導体素子搭載工程では、図２
（Ｄ）に示すように、前記弾力性皮膜形成工程で形成さ
れた半導体素子搭載基板フレーム１５Ａの各半導体素子
搭載部１２に半導体素子１７をＡｇペーストなどの接着
剤によって固着・搭載し、半導体素子１７の電極パッド
部と対応する内部リード１１の先端部（一端部）をボン
ディングワイヤ１８によって接続して電気的導通回路を
形成する半導体素子搭載ユニットフレーム１９を構成す
る。
（４）樹脂封止工程では、図１（Ａ）に示すように、半
導体装置１０（図１（Ｃ）参照）を形成するための片面
樹脂封止金型２０を準備する。この片面樹脂封止金型２
０は、上型２０Ａと下型２０Ｂとの組み合わせで構成さ
れている。上型２０Ａは、エポキシ樹脂などの耐熱性の
高い封止樹脂２１を充填する空間を形成する封止樹脂充
填キャビティ２２及びその周囲に形成された上型パーテ
ィング面２３を備えると共に、封止樹脂充填キャビティ
２２の側面部には図示しない樹脂注入口が設けられてい
る。なお、図１（Ａ）に示すように、封止樹脂充填キャ
ビティ２２の上方に樹脂注入口２２Ａを設けることもで
きる。下型２０Ｂは、上型パーティング面２３に対面
し、半導体素子搭載ユニットフレーム１９に当接する下
型パーティング面２４を備えている。この状態で、半導
体素子搭載ユニットフレーム１９を片面樹脂封止金型２
０内に載置し、上型パーティング面２３と下型パーティ
ング面２４とで半導体素子搭載ユニットフレーム１９を
圧接固定する。(3) In the semiconductor element mounting process, as shown in FIG.
As shown in (D), the semiconductor element 17 is fixed and mounted on each semiconductor element mounting portion 12 of the semiconductor element mounting substrate frame 15A formed in the elastic film forming step by an adhesive such as Ag paste. A tip end portion (one end portion) of the inner lead 11 corresponding to the electrode pad portion 17 is connected by a bonding wire 18 to form a semiconductor element mounting unit frame 19 which forms an electrical conduction circuit. (4) In the resin sealing step, as shown in FIG. 1A, a single-sided resin sealing die 20 for forming the semiconductor device 10 (see FIG. 1C) is prepared. This single-sided resin sealing mold 2
0 is composed of a combination of an upper mold 20A and a lower mold 20B. Upper mold 20A includes an upper mold formed in the sealing resin filling the cavity 22 and the periphery thereof to form a space filled with a high heat resistance sealing resin 21 such as epoxy resin Pate
A resin injection port (not shown) is provided on the side surface of the sealing resin-filled cavity 22 in addition to the sealing surface 23. As shown in FIG. 1A, a resin injection port 22A may be provided above the sealing resin filling cavity 22. The lower die 20B includes a lower die parting surface 24 that faces the upper die parting surface 23 and contacts the semiconductor element mounting unit frame 19. In this state, the semiconductor element mounting unit frame 19 is attached to the single-sided resin sealing mold 2
Placed in 0, upper mold parting surface 23 and lower mold party
The semiconductor element mounting unit frame 19 is press-contacted and fixed with the ring surface 24.
【００１３】ここで、この半導体装置の製造方法におい
て、樹脂封止工程での封止樹脂２１の外部実装面１１Ａ
への流入を防ぐ作用について説明する。半導体素子搭載
ユニットフレーム１９には、裏面側に内部リード１１の
他端部に形成された外部実装面１１Ａを露出する接続用
開口部１６Ａを設けた弾力性を有する絶縁皮膜層１６が
形成されて、内部リード１１、支持枠１３及び半導体素
子搭載部１２の周辺は全て絶縁皮膜層１６で被覆され
る。また、上型パーティング面２３及び下型パーティン
グ面２４が半導体素子搭載ユニットフレーム１９の上面
及び下面を圧接すると、弾力性のある絶縁皮膜層１６が
内部リード１１及び支持枠１３に押し付けられて内部リ
ード１１及び支持枠１３の下面が絶縁皮膜層１６の表面
に沈み込む。これにより、更に絶縁皮膜層１６が内部リ
ード１１と支持枠１３の周辺に密着し、内部リード１１
と支持枠１３の周辺は閉じられる。したがって、封止樹
脂充填キャビティ２２の中に注入された封止樹脂２１が
内部リード１１と下型パーティング面２４との間に流入
する隙間は生じない。次に、図１（Ｂ）に示すように、
内部リード１１の外部実装面１１Ａを上下から押し付け
た状態で、封止樹脂充填キャビティ２２の中央上面側に
設けた樹脂注入口２２Ａから封止樹脂充填キャビティ２
２内に封止樹脂２１を注入する。その結果、図１（Ｃ）
に示すように、封止樹脂２１の底面部位２５に外部実装
面１１Ａのみが露出した複数の半導体素子パッケージ２
６が形成され、その他の底面部位は絶縁皮膜層１６に被
覆された半導体素子パッケージユニットフレーム２７を
形成する。
（５）半導体素子パッケージ分離工程では、前記樹脂封
止工程で形成された半導体素子パッケージユニットフレ
ーム２７の封止樹脂２１の外周面から外側に突出した内
部リード１１を、図１（Ｃ）に破線で示す切断面Ｃで切
断し、半導体素子パッケージ２６を半導体装置１０の外
周周辺部で個々に分離して半導体装置１０を形成する。Here, in the method of manufacturing the semiconductor device, the external mounting surface 11A of the sealing resin 21 in the resin sealing step is used.
The action of preventing the inflow to the air will be described. The semiconductor element mounting unit frame 19 is provided with a resilient insulating film layer 16 provided with a connection opening 16A on the back surface side to expose the external mounting surface 11A formed on the other end of the internal lead 11. The inner leads 11, the support frame 13, and the periphery of the semiconductor element mounting portion 12 are all covered with the insulating film layer 16. The upper mold parting surface 23 and the lower mold Partin
When the insulating surface layer 16 is pressed against the upper surface and the lower surface of the semiconductor element mounting unit frame 19, the elastic insulating film layer 16 is pressed against the inner leads 11 and the supporting frame 13, and the lower surfaces of the inner lead 11 and the supporting frame 13 are electrically insulating film. It sinks into the surface of layer 16. As a result, the insulating film layer 16 further adheres to the inner leads 11 and the periphery of the support frame 13,
The periphery of the support frame 13 is closed. Therefore, there is no gap in which the sealing resin 21 injected into the sealing resin filled cavity 22 flows between the inner lead 11 and the lower mold parting surface 24. Next, as shown in FIG.
With the external mounting surface 11A of the inner lead 11 pressed from above and below, the resin injection port 22A provided on the central upper surface side of the sealing resin filling cavity 22 is used to form the sealing resin filling cavity 2
The encapsulating resin 21 is injected into the inside 2. As a result, FIG. 1 (C)
, A plurality of semiconductor element packages 2 in which only the external mounting surface 11A is exposed at the bottom surface portion 25 of the sealing resin 21.
6 is formed, and the other bottom surface portion forms the semiconductor element package unit frame 27 covered with the insulating film layer 16. (5) In the semiconductor element package separation step, the internal leads 11 protruding outward from the outer peripheral surface of the sealing resin 21 of the semiconductor element package unit frame 27 formed in the resin sealing step are broken lines in FIG. The semiconductor device 10 is formed by cutting along the cutting plane C shown in FIG.
【００１４】図３（Ａ）、（Ｂ）、（Ｃ）に示すよう
に、本発明の第２の実施の形態に係る半導体装置の製造
方法は、内部リードと半導体素子搭載部が異なる平面上
に配置されたＳＯＮ型、ＱＦＮ型の半導体装置に適用し
た場合である。なお、製造工程及び片面樹脂封止金型の
構造は前記第１の実施の形態に係る半導体装置の製造方
法で説明した内容と略同じであり、同一の構成について
は同一の符号を付して、詳しい説明は省略する。第２の
実施の形態に係る半導体装置３０においては、形状加工
工程で、半導体素子搭載部３２と、その周辺に配列され
た内部リード３１と、これを支持する支持枠３３とをエ
ッチング加工又はプレス加工によって導体回路パターン
３４を形成する際、半導体素子搭載部３２を内部リード
３１に対して上方に変位させると共に、内部リード３１
の一端部のワイヤボンディング面３１Ａをプレスによる
曲げ加工などにより半導体素子３７に近い高さになるよ
うに変形させて、半導体素子搭載ユニットフレーム３９
を形成している点で第１の実施の形態に係る半導体装置
１０と異なる。また、その後の工程は前記第１の実施の
形態に係る半導体装置の製造方法と略同じであるが、概
略説明すると、形状加工工程では導体回路パターン３４
は数個、一体的に連接した導体回路ユニットフレーム３
５を形成する。弾力性皮膜形成工程では、導体回路ユニ
ットフレーム３５の外部実装面３１Ｂを除く裏面側に、
弾力性を有する絶縁皮膜層３６を形成する。すなわち、
内部リード３１の外部実装面３１Ｂを露出する接続用開
口部３６Ａを設けると共に、内部リード３１及び支持枠
３３のそれぞれ周辺を覆う部分を残して樹脂露出用開口
部３６Ｂを設けた絶縁皮膜層３６を形成する。半導体素
子搭載工程では、導体回路ユニットフレーム３５の各半
導体素子搭載部３２に半導体素子３７を固着・搭載し、
半導体素子３７のパッド部と対応する内部リード３１の
先端のワイヤボンディング面３１Ａをボンディングワイ
ヤ３８によって接続して電気的導通回路を形成する半導
体素子搭載ユニットフレーム３９を構成する。したがっ
て、樹脂封止工程で、封止樹脂充填キャビティ２２内に
封止樹脂２１Ａを注入すると、図３（Ｃ）に示すよう
に、封止樹脂２１Ａの底面部位２５Ａと外部実装面３１
Ｂが露出した半導体装置３０が形成される。As shown in FIGS. 3A, 3B and 3C, in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, the internal lead and the semiconductor element mounting portion are on different planes. This is the case where the present invention is applied to the SON type and QFN type semiconductor devices arranged in. The manufacturing process and the structure of the single-sided resin sealing mold are substantially the same as those described in the method for manufacturing a semiconductor device according to the first embodiment, and the same components are designated by the same reference numerals. , Detailed description is omitted. In the semiconductor device 30 according to the second embodiment, the semiconductor element mounting portion 32, the inner leads 31 arranged around the semiconductor element mounting portion 32, and the support frame 33 that supports the semiconductor element mounting portion 32 are etched or pressed in the shape processing step. When forming the conductor circuit pattern 34 by processing, the semiconductor element mounting portion 32 is displaced upward with respect to the internal lead 31, and
The wire bonding surface 31A at one end of the semiconductor element mounting unit frame 39 is deformed to have a height close to that of the semiconductor element 37 by bending by pressing or the like.
Is different from the semiconductor device 10 according to the first embodiment. Further, the subsequent steps are substantially the same as the method of manufacturing the semiconductor device according to the first embodiment. However, in brief description, in the shape processing step, the conductor circuit pattern 34 is formed.
Several conductor circuit unit frames 3 that are integrally connected
5 is formed. In the elastic film forming step, on the back surface side of the conductor circuit unit frame 35 excluding the outer mounting surface 31B,
An insulating film layer 36 having elasticity is formed. That is,
The insulating coating layer 36 is provided with the connection opening 36A exposing the external mounting surface 31B of the inner lead 31 and the resin exposing opening 36B except for the portions covering the periphery of the inner lead 31 and the support frame 33. Form. In the semiconductor element mounting step, the semiconductor element 37 is fixedly mounted on each semiconductor element mounting portion 32 of the conductor circuit unit frame 35,
A semiconductor element mounting unit frame 39 that forms an electrical conduction circuit by connecting the wire bonding surface 31A at the tip of the internal lead 31 corresponding to the pad portion of the semiconductor element 37 by a bonding wire 38 is formed. Therefore, when the sealing resin 21A is injected into the sealing resin filled cavity 22 in the resin sealing step, as shown in FIG. 3C, the bottom surface portion 25A of the sealing resin 21A and the external mounting surface 31 are formed.
The semiconductor device 30 in which B is exposed is formed.
【００１５】このような方法により、導体回路ユニット
フレーム３５の外部実装面３１Ｂを除く裏面側に、弾力
性を有する絶縁皮膜層３６を形成しているので、内部リ
ード３１、支持枠３３の周辺は全て絶縁皮膜層３６で被
覆される。また、上型パーティ ング面２３及び下型パー
ティング面２４が半導体素子搭載ユニットフレーム３９
の上面及び絶縁皮膜層３６を介して下面を圧接すると、
弾力性のある絶縁皮膜層３６が内部リード３１及び支持
枠３３に押しつけられて内部リード３１及び支持枠３３
の下面が絶縁皮膜層３６の表面に沈み込み、内部リード
３１と支持枠３３の周辺は閉じられる。したがって、内
部リード３１の封止樹脂２１Ａとの境界部に位置する箇
所のＲ部を含み、内部リード３１の周辺は絶縁皮膜層３
６によって覆われ、封止樹脂充填キャビティ２２の中に
注入された封止樹脂２１Ａが内部リード３１と下型パー
ティング面２４との間に流入する隙間は生じない。By such a method, since the insulating film layer 36 having elasticity is formed on the back surface side of the conductor circuit unit frame 35 excluding the outer mounting surface 31B, the periphery of the inner leads 31 and the support frame 33 is All are covered with the insulating film layer 36. The upper mold parting surface 23 and the lower die par
The mounting surface 24 is the semiconductor element mounting unit frame 39.
When the lower surface is pressed against the upper surface of the
The elastic insulating film layer 36 is pressed against the inner leads 31 and the support frame 33 so that the inner leads 31 and the support frame 33
The lower surface of sunk into the surface of the insulating film layer 36, and the periphery of the inner lead 31 and the support frame 33 is closed. Therefore, the inner lead 31 includes the R portion at the boundary between the inner lead 31 and the sealing resin 21A, and the periphery of the inner lead 31 is surrounded by the insulating film layer 3.
Covered by 6, the lower die par injected sealing resin 21A and the internal lead 31 in a sealing resin filling the cavity 22
There is no inflowing gap with the toning surface 24.
【００１６】図４（Ａ）、（Ｂ）、（Ｃ）に示すよう
に、本発明の第３の実施の形態に係る半導体装置の製造
方法は、前記第１及び第２の実施の形態の片面樹脂封止
金型の下型に微小高さの環状突起を形成させたものであ
る。なお、製造工程及は前記第２の実施の形態に係る半
導体装置の製造方法で説明した内容と略同じであり、同
一の構成については同一の符号を付して、詳しい説明は
省略する。第３の実施の形態に係る半導体装置３０Ａに
おいては、片面樹脂封止金型２００の上型２００Ａは、
封止樹脂２１０を充填する空間を形成する封止樹脂充填
キャビティ２２０及びその周囲に形成された上型パーテ
ィング面２３０を備えている。下型２００Ｂは、上型パ
ーティング面２３０に対面する下型パーティング面２４
０に、上型パーティング面２３０の上型パーティング領
域２３０Ａより幅狭の下型パーティング領域２４１Ａが
突出する、例えば０．０１〜０．３ｍｍ程度の微小高さ
の凸形状の環状突起２４１を備えている点で第２の実施
の形態に係る半導体装置３０と異なる。As shown in FIGS. 4A, 4B, and 4C, the semiconductor device manufacturing method according to the third embodiment of the present invention is the same as that of the first and second embodiments. An annular protrusion having a minute height is formed on a lower die of a one-sided resin sealing die. The manufacturing process and the manufacturing process of the semiconductor device according to the second embodiment are substantially the same as those described above, and the same components are designated by the same reference numerals and detailed description thereof will be omitted. In the semiconductor device 30A according to the third embodiment, the upper die 200A of the single-sided resin sealing die 200 is
The upper mold is formed in the sealing resin filling the cavity 220 and the periphery thereof to form a space filled with the sealing resin 210 Pate
The wing surface 230 is provided. The lower die 200B is an upper die pad.
Lower mold parting surface 24 facing the facing surface 230
0, a lower mold parting area 241A, which is narrower than the upper mold parting area 230A of the upper mold parting surface 230, projects, for example, a protrusion having a minute height of about 0.01 to 0.3 mm. The semiconductor device 30 according to the second embodiment differs from the semiconductor device 30 according to the second embodiment in that the annular protrusion 241 having a shape is provided.
【００１７】ここで、この半導体装置の製造方法によ
り、封止樹脂２１０の外部実装面３１Ｂへの流入を防ぐ
作用について説明する。上型パーティング面２３０及び
下型パーティング面２４０によって半導体素子搭載ユニ
ットフレーム３９の内部リード３１の上面及び下面を圧
接する。すなわち、上型パーティング面２３０で支持枠
３３と共に支持枠３３に連結されている内部リード３１
を、絶縁皮膜層３６を介して環状突起２４１の下型パー
ティング領域２４１Ａに押しつける。そうすると、絶縁
皮膜層３６が下型パーティング面２４０に密着する。ま
た、内部リード３１の変形を極端に拡大して表現した図
４（Ｂ）に示すように、上型パーティング領域２３０Ａ
の下型パーティング領域２４１Ａより広い部分が、環状
突起２４１の外側に出ている内部リード３１を矢印Ｄの
方向に折り曲げるように押し下げるので、封止樹脂充填
キャビティ２２０内の内部リード３１は下面に設けられ
た絶縁皮膜層３６に押しつけられ、内部リード３１の下
面に形成された外部実装面３１Ｂと絶縁皮膜層３６との
境界が密着する。その結果、外部実装面３１Ｂへ封止樹
脂２１０が流入する隙間は生じなくなる。なお、前記本
発明の第１、第２及び第３の実施の形態に係る半導体装
置の製造方法において、樹脂封止工程の下流側に、露出
した内部リードの外部実装面にソルダーボール又は半田
材料等からなる突起部のバンプを形成する外部接続端子
形成工程を設けてもよい。この場合、内部リードの外部
実装面に確実に半田を載せることができ、半田接合不良
を防ぐことができる。Here, the function of preventing the sealing resin 210 from flowing into the external mounting surface 31B by this method of manufacturing a semiconductor device will be described. The upper mold parting surface 230 and the lower mold parting surface 240 press-contact the upper surface and the lower surface of the internal lead 31 of the semiconductor element mounting unit frame 39. That is, the inner leads 31 connected to the support frame 33 together with the support frame 33 on the upper mold parting surface 230.
The lower mold par annular projection 241 with an insulating film layer 36
It is pressed against the touching area 241A. Then, the insulating film layer 36 adheres to the lower mold parting surface 240. Further, as shown in FIG. 4 was expressed in extremely enlarged deformation of the inner leads 31 (B), the upper parting region 230A
A portion wider than the lower die parting area 241A pushes down the inner lead 31 protruding outside the annular protrusion 241 so as to be bent in the direction of the arrow D, so that the inner lead 31 inside the sealing resin-filled cavity 220 is located on the lower surface. The boundary between the external mounting surface 31B formed on the lower surface of the inner lead 31 and the insulating coating layer 36 is pressed against the provided insulating coating layer 36, and is brought into close contact. As a result, there is no gap in which the sealing resin 210 flows into the external mounting surface 31B. In the method of manufacturing a semiconductor device according to the first, second and third embodiments of the present invention, a solder ball or a solder material is formed on the external mounting surface of the exposed inner lead on the downstream side of the resin sealing step. An external connection terminal forming step of forming bumps on the protrusions made of, for example, may be provided. In this case, the solder can be surely placed on the outer mounting surface of the inner lead, and the solder joint failure can be prevented.
【００１８】[0018]
【発明の効果】請求項１〜４記載の半導体装置の製造方
法においては、導体回路ユニットフレームの外部実装面
を除く裏面側に、弾力性を有する絶縁皮膜層を形成して
いるので、内部リード、支持枠及び半導体搭載部の周辺
は全て絶縁皮膜層で被覆される。また、上型パーティン
グ面及び下型パーティング面が半導体素子搭載ユニット
フレームの上面及び下面を圧接すると、半導体素子搭載
ユニットフレームの上面は上型パーティング面に接触
し、内部リードと支持枠の周辺は閉じられる。したがっ
て、封止樹脂充填キャビティの周囲は全て封じ込まれた
状態となり、封止樹脂充填キャビティの中に注入された
封止樹脂が流入する隙間は生じない。その結果、内部リ
ードとプリント基板の接合パッドの半田接合不良を防
ぎ、実装不良を低減できる。そして、片面樹脂封止金型
は、前記上型パーティング面と、これに対応し、前記上
型パーティング面より幅狭の凸形状の環状突起を設けた
下型パーティング面とを備えているので、上型パーティ
ング面と下型パーティング面が半導体素子搭載ユニット
フレームを圧接すると、上型パーティング領域の下型パ
ーティング領域より広い部分が、環状突起の外側の内部
リードを押し下げ、封止樹脂充填キャビティ内の内部リ
ードの他端部がさらに絶縁皮膜層に密着し、封止樹脂が
内部リードの他端部側に流入する隙間が生じることはな
い。また、請求項２記載の半導体装置の製造方法におい
ては、前記絶縁皮膜層には、前記外部実装面が露出する
接続用開口部を形成しているので、接続用開口部を介し
て外部実装面を外部接続端子に簡単に接続することがで
きる。なお、内部リードの外部実装面が露出するが、内
部リード及び支持枠のそれぞれ周辺が絶縁皮膜層によっ
て被覆されるので、封止樹脂充填キャビティの中に注入
された封止樹脂が内部リードと下型パーティング面との
間に流入する隙間は生じない。In the method according to claim 1-4 Symbol mounting of the semiconductor device according to the present invention, on the back side except for the outer mounting surface of the conductor circuit unit frame, since an insulating film layer having elasticity, internal The periphery of the leads, the support frame, and the semiconductor mounting portion are all covered with an insulating film layer. Also, upper mold party
When the upper surface and the lower surface of the semiconductor element mounting unit frame are brought into pressure contact with the upper surface and the lower surface of the semiconductor element mounting unit frame, the upper surface of the semiconductor element mounting unit frame contacts the upper parting surface , and the periphery of the inner lead and the support frame is closed. Therefore, the entire periphery of the sealing resin filled cavity is in a sealed state, and there is no gap in which the injected sealing resin flows into the sealing resin filled cavity. As a result, it is possible to prevent defective solder joints between the inner leads and the joint pads of the printed circuit board, and reduce defective mounting. Then, one-sided resin-sealing mold includes: the upper die parting plane, correspondingly, and a lower mold parting surface provided with annular protrusion having a convex shape of the narrow than the upper mold parting surface There is a high- class party
When ring surface and the lower mold parting surface is pressed against a semiconductor element mounting unit frame, the lower mold path of the upper mold parting region
The area wider than the mounting area pushes down the inner lead outside the annular protrusion, the other end of the inner lead inside the encapsulation resin filled cavity further adheres to the insulating film layer, and the encapsulation resin is located on the other end side of the inner lead. There is no gap to flow into. Further, in the method of manufacturing a semiconductor device according to claim 2 , since the insulating film layer is formed with a connection opening for exposing the external mounting surface, the external mounting surface is exposed through the connection opening. Can be easily connected to the external connection terminal. Although the external mounting surface of the inner lead is exposed, the periphery of the inner lead and the support frame are covered with the insulating film layer, so that the sealing resin injected into the sealing resin-filled cavity is not covered with the inner lead and the lower surface. There is no inflow gap with the mold parting surface .
【００１９】請求項３記載の半導体装置の製造方法にお
いては、樹脂封止工程の下流側で、外部実装面が露出し
た接続用開口部にソルダーボール又はバンプを接続して
外部接続端子を形成しているので、内部リードの外部実
装面に確実に半田を載せることができ、半田接合不良を
防ぐことができる。更に、請求項４記載の半導体装置の
製造方法においては、前記絶縁皮膜層は、ポリイミド系
樹脂又はポリエチレン系樹脂中にＳｉＣ、酸化珪素、酸
化アルミニュームの酸化物の微粉末を均一に分散させた
混合樹脂からなっているので、封止樹脂を片面樹脂封止
金型に注入したとき、封止樹脂の成形時の熱によって絶
縁皮膜層が溶融して破損するようなことはない。In a method of manufacturing a semiconductor device according to a third aspect of the present invention, a solder ball or bump is connected to a connection opening having an exposed external mounting surface on the downstream side of a resin sealing step to form an external connection terminal. Therefore, the solder can be surely placed on the outer mounting surface of the inner lead, and the solder joint failure can be prevented. Further, in the method for manufacturing a semiconductor device according to claim 4, wherein the insulating coating layer, SiC in the polyimide-based resin or polyethylene-based resin, silicon oxide, uniformly dispersing fine powder of an oxide of aluminum oxide, New arm Since it is made of mixed resin, when the sealing resin is injected into the one-sided resin sealing mold, the insulating coating layer is not melted and damaged by the heat during the molding of the sealing resin.
【図１】（Ａ）、（Ｂ）、（Ｃ）はそれぞれ本発明の第
１の実施の形態に係る半導体装置の製造方法の樹脂封止
工程を示す側断面図、同樹脂封止工程でのリード部分の
拡大側断面図、同半導体素子パッケージ分離工程を示す
側断面図である。1A, 1B, and 1C are side cross-sectional views showing a resin encapsulation step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG. 4A is an enlarged side cross-sectional view of the lead portion of FIG.
【図２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）はそれぞれ本
発明の第１の実施の形態に係る半導体装置の製造方法の
形状加工工程を示す平面図、同形状加工工程を示す側断
面図、同弾力性皮膜形成工程を示す側断面図、同半導体
素子搭載工程を示す側断面図である。2 (A), (B), (C), and (D) are plan views showing the shape processing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, respectively. FIG. 4 is a side sectional view showing the same, a side sectional view showing the same elastic film forming step, and a side sectional view showing the same semiconductor element mounting step.
【図３】（Ａ）、（Ｂ）、（Ｃ）はそれぞれ本発明の第
２の実施の形態に係る半導体装置の製造方法の樹脂封止
工程を示す側断面図、同樹脂封止工程での内部リード部
分の拡大側断面図、同半導体素子パッケージ分離工程後
の状態を示す側断面図である。3 (A), (B), and (C) are side cross-sectional views showing a resin encapsulation process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is an enlarged side sectional view of an internal lead portion of FIG. 4 and a side sectional view showing a state after the same semiconductor element package separating step.
【図４】（Ａ）、（Ｂ）、（Ｃ）はそれぞれ本発明の第
３の実施の形態に係る半導体装置の製造方法の樹脂封止
工程を示す側断面図、同樹脂封止工程での内部リード部
分の拡大側断面図、同半導体素子パッケージ分離工程後
の状態を示す側断面図である。4A, 4B, and 4C are side cross-sectional views showing a resin encapsulation process of a method for manufacturing a semiconductor device according to a third embodiment of the present invention, and FIG. 3 is an enlarged side sectional view of an internal lead portion of FIG. 4 and a side sectional view showing a state after the same semiconductor element package separating step.
【図５】（Ａ）、（Ｂ）、（Ｃ）はそれぞれ従来の半導
体装置の製造方法の樹脂封止工程を示す側断面図、同半
導体素子パッケージ分離工程を示す側断面図、同樹脂封
止工程での内部リード部分の拡大側断面図である。5A, 5B, and 5C are side sectional views showing a resin encapsulation step, a semiconductor element package separating step in the conventional semiconductor device manufacturing method, and a resin encapsulation step, respectively. It is an expanded side sectional view of an internal lead part in a stopping process.
【図６】（Ａ）、（Ｂ）、（Ｃ）はそれぞれ従来の他の
半導体装置の製造方法の樹脂封止工程を示す側断面図、
同樹脂封止工程での内部リード部分の拡大側断面図、同
半導体素子パッケージ分離工程後の状態を示す側断面図
である。6A, 6B, and 6C are side cross-sectional views showing a resin encapsulation process of another conventional method for manufacturing a semiconductor device,
FIG. 7 is an enlarged side sectional view of an internal lead portion in the resin sealing step, and a side sectional view showing a state after the semiconductor element package separating step.
１０ 半導体装置 １１ 内部リー
ド
１１Ａ 外部実装面 １２ 半導体素
子搭載部
１３ 支持枠 １４ 導体回路
パターン
１５ 導体回路ユニットフレーム
１５Ａ 半導体素子搭載基板フレーム １６ 絶縁皮膜
層
１６Ａ 接続用開口部 １７ 半導体素
子
１８ ボンディングワイヤ
１９ 半導体素子搭載ユニットフレーム
２０ 片面樹脂封止金型 ２０Ａ 上型
２０Ｂ 下型 ２１ 封止樹脂
２１Ａ 封止樹脂 ２２ 封止樹脂
充填キャビティ
２２Ａ 樹脂注入口 ２３ 上型パー
ティング面
２４ 下型パーティング面 ２５ 底面部位
２５Ａ 底面部位 ２６ 半導体素
子パッケージ
２７ 半導体素子パッケージユニットフレーム
３０ 半導体装置 ３０Ａ 半導体
装置
３１ 内部リード ３１Ａ ワイヤ
ボンディング面
３１Ｂ 外部実装面 ３２ 半導体素
子搭載部
３３ 支持枠 ３４ 導体回路
パターン
３５ 導体回路ユニットフレーム ３６ 絶縁皮膜
層
３６Ａ 接続用開口部 ３６Ｂ 樹脂露
出用開口部
３７ 半導体素子 ３８ ボンディ
ングワイヤ
３９ 半導体素子搭載ユニットフレーム
２００ 片面樹脂封止金型 ２００Ａ 上型
２００Ｂ 下型 ２１０ 封止樹
脂
２２０ 封止樹脂充填キャビティ ２３０ 上型パ
ーティング面
２３０Ａ 上型パーティング領域 ２４０ 下型パ
ーティング面
２４１ 環状突起 ２４１Ａ 下型
パーティング領域
10 semiconductor device 11 internal lead
Do
11A External mounting surface 12 Semiconductor element
Child mount
13 Support frame 14 Conductor circuit
pattern
15 Conductor circuit unit frame
15A Semiconductor element mounting board frame 16 Insulation film
layer
16A Connection opening 17 Semiconductor element
Child
18 Bonding wire
19 Semiconductor element mounting unit frame
20 One-sided resin sealing mold 20A Upper mold
20B lower mold 21 sealing resin
21A sealing resin 22 sealing resin
Filling cavity
22A Resin injection port 23 Upper moldPar
Surface
24 Lower moldParting surface 25 Bottom part
25A Bottom part 26 Semiconductor element
Child package
27 Semiconductor device package unit frame
30 semiconductor device 30A semiconductor
apparatus
31 internal lead 31A wire
Bonding surface
31B External mounting surface 32 Semiconductor element
Child mount
33 Support Frame 34 Conductor Circuit
pattern
35 Conductor circuit unit frame 36 Insulation film
layer
36A Connection opening 36B Resin dew
Outgoing opening
37 Semiconductor element 38 Bondy
Ngwire
39 Semiconductor element mounting unit frame
200 One side resin sealing mold 200A Upper mold
200B Lower mold 210 Sealing tree
Fat
220 sealing resin filling cavity 230 upper moldPa
Coating surface
230A upper moldpartingArea 240 Lower moldPa
Coating surface
241 Annular projection 241A Lower mold
partingregion
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 23/28 Ｈ０１Ｌ 23/28 Ａ 23/50 23/50 Ｙ // Ｂ２９Ｌ 31:34 Ｂ２９Ｌ 31:34 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/56 B29C 45/02 B29C 45/14 B29C 45/26 H01L 23/28 H01L 23/50 B29L 31:34 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI H01L 23/28 H01L 23/28 A 23/50 23/50 Y // B29L 31:34 B29L 31:34 (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/56 B29C 45/02 B29C 45/14 B29C 45/26 H01L 23/28 H01L 23/50 B29L 31:34
Claims (4)
パッドに接続し、他端部が半導体装置の封止樹脂の底面
部位に露出して外部実装面を形成する樹脂封止型半導体
装置の製造方法であって、 金属条材からエッチング加工又はプレス加工によって、
半導体素子搭載部とその周辺に配列された前記内部リー
ドと、これを支持する支持枠を備えた導体回路パターン
を複数連接した導体回路ユニットフレームを形成する形
状加工工程と、 前記形状加工工程で形成された前記導体回路ユニットフ
レームの前記外部実装面を除く裏面側に、弾力性を有す
る絶縁皮膜層を設けた半導体素子搭載基板フレームを形
成する弾力性皮膜形成工程と、 前記弾力性皮膜形成工程で形成された前記半導体素子搭
載基板フレームの各半導体素子搭載部に前記半導体素子
を搭載し、該半導体素子の電極パッド部と対応する前記
内部リードの一端部を接続して電気的導通回路を設けた
半導体素子搭載ユニットフレームを形成する半導体素子
搭載工程と、 前記半導体素子搭載工程で形成された半導体素子搭載ユ
ニットフレームを、複数の封止樹脂充填キャビティ及び
その周囲に形成された上型パーティング面を備えた上型
と、前記上型パーティング面に対面する下型パーティン
グ面を備えた下型との組み合わせからなる片面樹脂封止
金型内に載置し、前記上型パーティング面と下型パーテ
ィング面とで前記半導体素子搭載ユニットフレームを圧
接固定して前記絶縁皮膜層を介して前記内部リードを押
し付けた状態で、前記封止樹脂充填キャビティ内に前記
封止樹脂を注入して前記外部実装面が前記封止樹脂の底
面部位に露出した複数の半導体素子パッケージを形成す
る半導体素子パッケージユニットフレームを製造する樹
脂封止工程と、 前記樹脂封止工程で形成された半導体素子パッケージユ
ニットフレームの樹脂封止領域から突出した前記内部リ
ードを切断して、前記半導体装置の外周周辺部で前記半
導体素子パッケージを個々に分離して前記半導体装置を
形成する半導体素子パッケージ分離工程とを有し、 前記片面樹脂封止金型は、前記上型パーティング面と、
これに対応し、前記上型パーティング面より幅狭の凸形
状の環状突起を設けた前記下型パーティング面とを備
え、前記上型パーティング面と前記下型パーティング面
との組み合わせからなることを特徴とする半導体装置の
製造方法。 1. A resin-sealed semiconductor device in which one end of an internal lead is connected to an electrode pad of a semiconductor element and the other end is exposed at a bottom surface portion of a sealing resin of a semiconductor device to form an external mounting surface. A method of manufacturing, which comprises etching or pressing metal strips,
A shape processing step of forming a conductor circuit unit frame in which a plurality of conductor circuit patterns including a semiconductor element mounting portion and the internal leads arranged around the semiconductor element mounting portion and a support frame for supporting the semiconductor element mounting portion are connected, and the shape processing step is performed. An elastic film forming step of forming a semiconductor element mounting substrate frame provided with an insulating film layer having elasticity on the back surface side of the conductor circuit unit frame other than the external mounting surface, and the elastic film forming step. The semiconductor element is mounted on each semiconductor element mounting portion of the formed semiconductor element mounting substrate frame, and one end portion of the internal lead corresponding to the electrode pad portion of the semiconductor element is connected to provide an electrical conduction circuit. The semiconductor element mounting step of forming the semiconductor element mounting unit frame, and the semiconductor element mounting unit frame formed in the semiconductor element mounting step. The arm, and the upper mold having a plurality of sealing resin filling the cavity and the upper mold parting surface formed around its lower mold Partin facing said upper mold parting surface
Placed on one side resin sealing metal inner mold consisting of a lower mold provided with a grayed surface, the upper mold parting surface and the lower mold Pate
The mounting surface of the semiconductor element mounting unit by press-fitting and fixing the internal lead through the insulating film layer, and injecting the encapsulating resin into the encapsulating resin-filled cavity to externally mount the encapsulating resin. A resin encapsulation step of manufacturing a semiconductor element package unit frame having a plurality of semiconductor element packages whose surfaces are exposed at the bottom surface portion of the encapsulation resin; and a resin of the semiconductor element package unit frame formed in the resin encapsulation step. by cutting the inner leads protruding from the sealing area, said individually separating the semiconductor device package at the outer peripheral portion of the semiconductor device and a semiconductor device package separation step of forming said semiconductor device, said one side The resin-sealed mold has the upper mold parting surface,
Corresponding to this, convex shape narrower than the upper mold parting surface
With the lower parting surface provided with a ring-shaped protrusion
The upper mold parting surface and the lower mold parting surface
Of a semiconductor device characterized by comprising a combination of
Production method.
おいて、前記絶縁皮膜層には、前記外部実装面が露出す
る接続用開口部を設けたことを特徴とする半導体装置の
製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the insulating film layer is provided with a connection opening for exposing the external mounting surface.
おいて、前記樹脂封止工程の下流側に、前記外部実装面
が露出した前記接続用開口部にソルダーボール又はバン
プを接続して外部接続端子を形成する外部接続端子形成
工程を設けたことを特徴とする半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2 , wherein a solder ball or a bump is connected to the connection opening where the external mounting surface is exposed, on the downstream side of the resin encapsulation step, for external connection. A method of manufacturing a semiconductor device, comprising: an external connection terminal forming step of forming a terminal.
導体装置の製造方法において、前記絶縁皮膜層は、ポリ
イミド系樹脂又はポリエチレン系樹脂中にＳｉＣ、酸化
珪素、酸化アルミニュームの酸化物の微粉末を均一に分
散させた混合部材からなることを特徴とする半導体装置
の製造方法。 4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the insulating coating layer, SiC in the polyimide-based resin or polyethylene-based resin, silicon oxide, aluminum oxide, New arm A method for manufacturing a semiconductor device, comprising a mixing member in which fine oxide powder is uniformly dispersed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29449498A JP3455116B2 (en) | 1998-09-30 | 1998-09-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29449498A JP3455116B2 (en) | 1998-09-30 | 1998-09-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000114295A JP2000114295A (en) | 2000-04-21 |
| JP3455116B2 true JP3455116B2 (en) | 2003-10-14 |
Family
ID=17808499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29449498A Expired - Fee Related JP3455116B2 (en) | 1998-09-30 | 1998-09-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3455116B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4569048B2 (en) * | 2001-06-04 | 2010-10-27 | ソニー株式会社 | Surface mount semiconductor package and manufacturing method thereof |
| CN100536121C (en) * | 2001-12-14 | 2009-09-02 | 株式会社瑞萨科技 | Semiconductor device and preparation method thereof |
| JP4815935B2 (en) | 2005-08-02 | 2011-11-16 | 日立電線株式会社 | Method for producing molded body |
| CN100426499C (en) * | 2006-11-17 | 2008-10-15 | 威盛电子股份有限公司 | An electronic assembly and circuit board for same |
| JP5308108B2 (en) * | 2008-09-11 | 2013-10-09 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Circuit device manufacturing method |
| JP5308107B2 (en) * | 2008-09-11 | 2013-10-09 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Circuit device manufacturing method |
| JP5971531B2 (en) * | 2014-04-22 | 2016-08-17 | 大日本印刷株式会社 | Resin-sealed semiconductor device and manufacturing method thereof |
| WO2018146755A1 (en) * | 2017-02-08 | 2018-08-16 | 信越エンジニアリング株式会社 | Resin sealing device and resin sealing method |
-
1998
- 1998-09-30 JP JP29449498A patent/JP3455116B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000114295A (en) | 2000-04-21 |
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