JP2001267452A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001267452A
JP2001267452A JP2000074065A JP2000074065A JP2001267452A JP 2001267452 A JP2001267452 A JP 2001267452A JP 2000074065 A JP2000074065 A JP 2000074065A JP 2000074065 A JP2000074065 A JP 2000074065A JP 2001267452 A JP2001267452 A JP 2001267452A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor device
adhesive
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000074065A
Other languages
Japanese (ja)
Inventor
Hidemi Ozawa
英美 小澤
Masakatsu Goto
正克 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP2000074065A priority Critical patent/JP2001267452A/en
Publication of JP2001267452A publication Critical patent/JP2001267452A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To improve a wire-bonding connection reliability by preventing pollution of bonding electrodes caused by an adhesive material at the time of die bonding. SOLUTION: In a BGA semiconductor device 1, a semiconductor chip 3 is mounted on a major surface of a printed circuit board 2 with an adhesive material, and bonding electrodes 2b formed on the major surface of the board 2 and electrodes 3a formed on the chip 3 are connected by bonding wires 5 respectively. Solder bumps are formed on a rear side of the board 2. A frame-shaped dam 2d for preventing flowing out of the adhesive is made in between the bonding electrodes 2b and an outer periphery of the chip 3. The dam 2d prevents the adhesive from flowing down to the bonding electrodes 2b at the time of die bonding or the like.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ボンディングワイ
ヤにおける接続不良の防止技術に関し、特に、ＢＧＡ
（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）形半導体装置にお
けるボンディングワイヤの接続不良防止に適用して有効
な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for preventing a connection failure in a bonding wire, and more particularly, to a BGA.
The present invention relates to a technology effective when applied to prevent connection failure of a bonding wire in a (Ball Grid Array) type semiconductor device.

【０００２】[0002]

【従来の技術】表面実装形半導体装置の１つとして、た
とえば、ＢＧＡがある。本発明者が検討したところによ
れば、ＢＧＡ形の半導体装置は、プリント配線基板上に
搭載された半導体チップの電極と該プリント配線基板に
形成されたボンディング用電極とをボンディングワイヤ
によってボンディングした後、樹脂封止してパッケージ
を形成している。2. Description of the Related Art As one of surface-mount type semiconductor devices, for example, there is a BGA. According to studies made by the present inventors, a BGA type semiconductor device is manufactured by bonding electrodes of a semiconductor chip mounted on a printed wiring board and bonding electrodes formed on the printed wiring board with bonding wires. The package is formed by resin sealing.

【０００３】また、パッケージの裏面には、外部導出用
リードの代わりとして球形のはんだ、いわゆる、はんだ
ボールが形成されている。半導体装置の実装時には、は
んだボールを電子部品などを実装する実装配線基板に形
成された電極部に重合させ、リフローによりはんだボー
ルを溶融し、電気的に接続している。In addition, a spherical solder, that is, a so-called solder ball is formed on the back surface of the package instead of the lead for leading out. At the time of mounting a semiconductor device, solder balls are superimposed on an electrode portion formed on a mounting wiring board on which electronic components and the like are mounted, and the solder balls are melted by reflow to be electrically connected.

【０００４】なお、この種の半導体装置について詳しく
述べてある例としては、１９９３年５月３１日、日経Ｂ
Ｐ社発行、香山 晋、成瀬 邦彦（監）、「ＶＬＳＩパ
ッケージング技術（下）」Ｐ１７３〜Ｐ１７８があり、
この文献には、ＢＧＡ形半導体装置の構成などが記載さ
れている。[0004] As an example describing this type of semiconductor device in detail, see Nikkei B on May 31, 1993.
Published by Company P, Susumu Kayama, Kunihiko Naruse (monitoring), "VLSI Packaging Technology (2)" P173-P178,
This document describes the configuration of a BGA type semiconductor device and the like.

【０００５】[0005]

【発明が解決しようとする課題】ところが、上記のよう
な半導体装置では、次のような問題点があることが本発
明者により見い出された。However, the present inventor has found that the above-described semiconductor device has the following problems.

【０００６】近年、半導体装置の小型化に伴い、ＢＧＡ
形半導体装置においてもファインピッチ化が進んでい
る。このファインピッチＢＧＡの場合、プリント配線基
板が小面積化されているので半導体チップの周辺部から
プリント配線基板に形成されたボンディング電極までの
距離も短くなっている。In recent years, with the miniaturization of semiconductor devices, BGA
Fine-pitch semiconductor devices are also becoming finer. In the case of the fine pitch BGA, since the area of the printed wiring board is reduced, the distance from the peripheral portion of the semiconductor chip to the bonding electrode formed on the printed wiring board is also reduced.

【０００７】それによって、ダイボンディング時や、接
着材を硬化させるベイク時などに半導体チップをプリン
ト配線基板に接着する接着材が流れだし、その流れ出し
た接着材によってボンディング電極が汚染されてしまう
恐れがある。[0007] As a result, the adhesive for bonding the semiconductor chip to the printed wiring board flows out during die bonding or baking to cure the adhesive, and the bonding electrode may be contaminated by the flowed adhesive. is there.

【０００８】汚染されたボンディング電極にワイヤボン
ディングを行った場合、ボンディングワイヤの接合が不
充分となり、圧着はがれや接続不良などが生じてしま
い、半導体装置の信頼性を損ねてしまうという問題があ
る。When wire bonding is performed on a contaminated bonding electrode, there is a problem in that bonding of the bonding wire becomes insufficient, so that pressure bonding may be peeled off or a connection failure may occur, thereby impairing the reliability of the semiconductor device.

【０００９】本発明の目的は、ボンディング電極の汚染
を防止し、ワイヤボンディングの接続信頼性を向上する
ことのできる半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device capable of preventing contamination of a bonding electrode and improving connection reliability of wire bonding.

【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１１】[0011]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１２】すなわち、本発明の半導体装置は、プリン
ト配線基板の主面に半導体チップが搭載され、該プリン
ト配線基板の主面に設けられた接続用電極と半導体チッ
プに設けられたチップ電極とがボンディングワイヤを介
して接続された構成からなり、該プリント配線基板の接
続用電極と半導体チップの外周部との間に半導体チップ
をプリント配線基板に接着する際に用いられる接着材の
流出を防止するダムを備えたものである。That is, in the semiconductor device of the present invention, a semiconductor chip is mounted on a main surface of a printed wiring board, and a connection electrode provided on the main surface of the printed wiring board and a chip electrode provided on the semiconductor chip are formed. It is configured to be connected via bonding wires, and prevents leakage of an adhesive used when bonding the semiconductor chip to the printed wiring board between the connection electrode of the printed wiring board and the outer peripheral portion of the semiconductor chip. It has a dam.

【００１３】以上のことにより、ダイボンディング時に
接着材が流れだすことによる接続用電極の汚染を防止で
きるので、半導体装置のボンディング不良などを大幅に
低減することができ、半導体装置の接続信頼性を向上す
ることができる。As described above, contamination of the connection electrode due to the flow of the adhesive during die bonding can be prevented, so that the bonding failure of the semiconductor device can be greatly reduced, and the connection reliability of the semiconductor device can be reduced. Can be improved.

【００１４】[0014]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.

【００１５】図１は、本発明の一実施の形態によるファ
インピッチＢＧＡ形半導体装置の上面図、図２（ａ）
は、本発明の一実施の形態による半導体装置の断面図、
（ｂ）は、半導体装置に形成されたダム、およびその近
傍の説明図である。FIG. 1 is a top view of a fine pitch BGA type semiconductor device according to an embodiment of the present invention, and FIG.
Is a cross-sectional view of a semiconductor device according to an embodiment of the present invention,
(B) is an explanatory view of a dam formed in a semiconductor device and its vicinity.

【００１６】本実施の形態において、表面実装形の一種
であるＢＧＡ形の半導体装置１は、図１、図２に示すよ
うに、プリント配線基板２が設けられている。プリント
配線基板２には、基板コア２ａが設けられている。In this embodiment, a BGA type semiconductor device 1 which is a type of surface mount type is provided with a printed wiring board 2 as shown in FIGS. The printed wiring board 2 is provided with a board core 2a.

【００１７】この基板コア２ａは、たとえば、ガラスク
ロス基材などから形成されており、基板コア２ａの主面
には、ボンディング電極（接続用電極）２ｂ、および配
線パターンが形成されている。The substrate core 2a is formed of, for example, a glass cloth base material. A bonding electrode (connection electrode) 2b and a wiring pattern are formed on the main surface of the substrate core 2a.

【００１８】基板コア２ａの裏面には、バンプ用電極、
ならびに配線パターンが形成されており、ボンディング
電極２ｂとバンプ用電極とは、配線パターン、ならびに
スルーホールによってそれぞれ電気的に接続されてい
る。On the back surface of the substrate core 2a, a bump electrode,
In addition, a wiring pattern is formed, and the bonding electrode 2b and the bump electrode are electrically connected to each other by the wiring pattern and the through hole.

【００１９】そして、ボンディング電極２ｂ、バンプ用
電極を除く、基板コア２ａの全面にはソルダレジスト２
ｃが形成されている。このソルダレジスト２ｃは、たと
えば、メラニン、エポキシ、アクリル、ポリスチロール
などからなり、はんだ付け不要な配線パターンなどが溶
融はんだと接触することなどを防止する。A solder resist 2 is formed on the entire surface of the substrate core 2a except for the bonding electrodes 2b and the bump electrodes.
c is formed. The solder resist 2c is made of, for example, melanin, epoxy, acrylic, or polystyrene, and prevents a wiring pattern that does not need to be soldered from coming into contact with the molten solder.

【００２０】また、ボンディング電極２ｂは、基板コア
２ａの周辺部近傍に形成されており、バンプ用電極は、
基板コア２ａの所定のピッチでアレイ状に形成されてい
る。プリント配線基板２主面の中央部には、半導体チッ
プ３が接着材４を介して接着されている。The bonding electrode 2b is formed near the periphery of the substrate core 2a.
The substrate cores 2a are formed in an array at a predetermined pitch. A semiconductor chip 3 is bonded to a central portion of the main surface of the printed wiring board 2 via an adhesive 4.

【００２１】プリント配線基板２には、接着材が流れ出
すのを防止する額縁状のダム２ｄがボンディング電極２
ｂと半導体チップ３の外周部との間に位置するように形
成されている。このダム２ｄは、基板コア２ａに形成さ
れたソルダレジスト２ｃと同じ材料から形成されてい
る。On the printed wiring board 2, a frame-shaped dam 2d for preventing the adhesive from flowing out is provided with a bonding electrode 2d.
It is formed so as to be located between b and the outer peripheral portion of the semiconductor chip 3. The dam 2d is made of the same material as the solder resist 2c formed on the substrate core 2a.

【００２２】さらに、半導体チップ３の周辺部近傍に
は、電極（チップ電極）３ａが形成されている。電極３
ａとプリント配線基板２のボンディング電極２ａとは、
金ワイヤなどのボンディングワイヤ５によってそれぞれ
ボンディングされている。Further, an electrode (chip electrode) 3a is formed near the periphery of the semiconductor chip 3. Electrode 3
a and the bonding electrode 2a of the printed wiring board 2
Each is bonded by a bonding wire 5 such as a gold wire.

【００２３】プリント配線基板２に搭載された半導体チ
ップ３、ボンディングワイヤ５、ボンディング電極２ｂ
の周辺部およびそれら近傍は、封止樹脂６によって封止
されている。The semiconductor chip 3, the bonding wires 5, and the bonding electrodes 2b mounted on the printed wiring board 2
And its vicinity are sealed by a sealing resin 6.

【００２４】プリント配線基板２のバンプ用電極には、
球形のはんだからなるはんだバンプ７がそれぞれ形成さ
れている。半導体装置１は、これらはんだバンプ７のピ
ッチが１ｍｍ以下となる、いわゆるファインピッチＢＧ
Ａとなっている。The bump electrodes of the printed wiring board 2 include
Solder bumps 7 made of spherical solder are respectively formed. The semiconductor device 1 has a so-called fine pitch BG in which the pitch of the solder bumps 7 is 1 mm or less.
A.

【００２５】これらはんだバンプ７は半導体装置１の外
部接続端子となる。半導体装置を実装する際には、はん
だバンプ７を、電子部品などを実装する実装配線基板に
形成された電極（ランド）に重合させて搭載してリフロ
ーを行い、はんだバンプ７を溶融させて電気的に接続す
る。These solder bumps 7 become external connection terminals of the semiconductor device 1. When mounting a semiconductor device, the solder bumps 7 are superimposed on electrodes (lands) formed on a mounting wiring board on which electronic components and the like are mounted and mounted, and reflow is performed. Connection.

【００２６】次に、本実施の形態におけるプリント配線
基板２へのダム２ｄの形成について説明する。Next, the formation of the dam 2d on the printed wiring board 2 in the present embodiment will be described.

【００２７】まず、配線パターン、ボンディング電極２
ａなどが形成されたプリント配線基板２の主面全面にソ
ルダレジストを印刷、硬化させた後、ボンディング電極
２ｂをエッチングにより露出させる。その後、ソルダレ
ジスト上に再度ソルダレジストを印刷、硬化させ、ダム
２ｄ以外の部分をエッチングにより除去する。これによ
り、ダム２ｄが形成される。この２度目にソルダレジス
ト印刷は、プリント配線基板２の主面全面に施してもよ
いし、ダム２ｄ周辺にのみ施すようにしてもよい。First, the wiring pattern, the bonding electrode 2
After printing and hardening a solder resist on the entire main surface of the printed wiring board 2 on which the a is formed, the bonding electrode 2b is exposed by etching. Thereafter, the solder resist is printed and hardened again on the solder resist, and portions other than the dam 2d are removed by etching. Thereby, a dam 2d is formed. The second solder resist printing may be performed on the entire main surface of the printed wiring board 2 or may be performed only around the dam 2d.

【００２８】半導体チップ３をプリント配線基板２上に
搭載するダイボンディング時には、プリント配線基板２
の中央部に接着材４が塗布され、半導体チップ３が搭載
される。At the time of die bonding for mounting the semiconductor chip 3 on the printed wiring board 2,
The adhesive 4 is applied to the center of the semiconductor chip 3, and the semiconductor chip 3 is mounted.

【００２９】この時、半導体チップ３の圧力などによっ
て接着材４が流れ出すが、該半導体チップ３を囲うよう
に形成された額縁状のダム２ｄによってボンディング電
極２ａに接着材４が流出することを防止することができ
る。At this time, the adhesive 4 flows out due to the pressure of the semiconductor chip 3 and the like, but the adhesive 4 is prevented from flowing out to the bonding electrode 2a by the frame-shaped dam 2d formed so as to surround the semiconductor chip 3. can do.

【００３０】また、ダイボンディング後、接着材４を硬
化させるためにベイクを行うが、このベイクによって接
着材４の粘度が一時的に下がり、より接着材４が流出し
やすくなるが、この場合においても、ダム２ｄによって
ボンディング電極２ａへの接着材４の流出を確実に防止
することができる。After the die bonding, baking is performed to cure the adhesive 4. This baking temporarily lowers the viscosity of the adhesive 4 and makes the adhesive 4 easier to flow out. Also, the outflow of the adhesive 4 to the bonding electrode 2a can be reliably prevented by the dam 2d.

【００３１】よって、半導体チップ３とボンディング電
極２ｂとの距離が短いファインピッチＢＧＡ形半導体装
置１における接着材４によるボンディング電極２ｂへの
汚染を確実に防止することができる。Accordingly, contamination of the bonding electrode 2b by the adhesive 4 in the fine pitch BGA type semiconductor device 1 in which the distance between the semiconductor chip 3 and the bonding electrode 2b is short can be reliably prevented.

【００３２】それにより、本実施の形態によれば、プリ
ント配線基板２に形成されたダム２ｄによって、ボンデ
ィングワイヤ５の圧着はがれや接続不良などを防止で
き、半導体装置１の接続信頼性を大幅に向上することが
できる。Thus, according to the present embodiment, due to the dam 2 d formed on the printed wiring board 2, the bonding wire 5 can be prevented from being peeled off or a connection failure, and the connection reliability of the semiconductor device 1 can be greatly improved. Can be improved.

【００３３】また、本実施の形態においては、額縁状の
ダム２ｄを半導体装置１に形成して接着材４の流出を防
止したが、たとえば、図３（ａ）、（ｂ）に示すよう
に、半導体チップ３の外周部とボンディング電極２ａと
の間に溝（ダム）２ｅを形成するようにしてもよい。In the present embodiment, the frame-shaped dam 2d is formed in the semiconductor device 1 to prevent the adhesive 4 from flowing out. For example, as shown in FIGS. 3 (a) and 3 (b), Alternatively, a groove (dam) 2e may be formed between the outer peripheral portion of the semiconductor chip 3 and the bonding electrode 2a.

【００３４】この場合、溝２ｅに接着材４を貯めること
によってボンディング電極２ｂへの流出を防止すること
ができる。それにより、接着材４によるボンディング電
極２ｂへの汚染を確実に防止でき、半導体装置１の接続
信頼性を大幅に向上することができる。In this case, outflow to the bonding electrode 2b can be prevented by storing the adhesive 4 in the groove 2e. Accordingly, contamination of the bonding electrode 2b by the adhesive 4 can be reliably prevented, and the connection reliability of the semiconductor device 1 can be greatly improved.

【００３５】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることはいうまでも
ない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

【００３６】たとえば、前記実施の形態では、ファイン
ピッチＢＧＡ形の半導体装置について記載したが、ファ
インピッチＢＧＡでなくとも、たとえば、プリント配線
基板に対して比較的大きな半導体チップが搭載される通
常のＢＧＡなどの半導体チップとボンディング電極との
距離が短い半導体装置にダムを設けることにより、接着
材によるボンディング電極への汚染を確実に防止するこ
とができるので、半導体装置の接続信頼性を大幅に向上
することができる。For example, in the above-described embodiment, the fine pitch BGA type semiconductor device has been described. However, even if the semiconductor device is not a fine pitch BGA, for example, a normal BGA in which a relatively large semiconductor chip is mounted on a printed circuit board is used. By providing a dam in a semiconductor device having a short distance between a semiconductor chip and a bonding electrode, the contamination of the bonding electrode by an adhesive can be reliably prevented, and the connection reliability of the semiconductor device is greatly improved. be able to.

【００３７】さらに、前記実施の形態による接着材の流
出防止用のダムが形成される半導体装置はＢＧＡ形以外
でもよく、パッケージ材料としてプリント配線基板を用
い、ＣＯＢ（Ｃｈｉｐ Ｏｎ Ｂｏａｄ）のようにワイ
ヤボンディング後に樹脂封止し、裏面に形成したはんだ
バンプによって実装基板などに実装する、いわゆる、Ｏ
ＭＰＡＣ（Ｏｖｅｒ−Ｍｏｌｄ Ｐａｃｋａｇｅ）構造
の半導体装置であればよい。Further, the semiconductor device in which the dam for preventing the adhesive from flowing out according to the above-described embodiment may be formed of a type other than the BGA type. It is sealed with a resin after bonding, and mounted on a mounting substrate or the like by solder bumps formed on the back surface.
Any semiconductor device having an MPAC (Over-Mold Package) structure may be used.

【００３８】[0038]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

【００３９】（１）本発明によれば、プリント配線基板
の接続用電極と半導体チップの外周部と間に接着材の流
出を防止するダムを備えたことにより、ダイボンディン
グ時などに接着材の流出を確実に防止することができ
る。(1) According to the present invention, a dam for preventing the adhesive from flowing out is provided between the connection electrode of the printed wiring board and the outer peripheral portion of the semiconductor chip. Outflow can be reliably prevented.

【００４０】（２）また、本発明では、上記（１）によ
り、接着材による接続用電極の汚染を防ぐことができる
のでボンディングワイヤの圧着はがれや接続不良などを
防止でき、半導体装置の接続信頼性を大幅に向上するこ
とができる。(2) In the present invention, according to the above (1), the contamination of the connection electrode by the adhesive can be prevented, so that the bonding wire can be prevented from coming off or the connection failure, and the connection reliability of the semiconductor device can be prevented. Performance can be greatly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態によるファインピッチＢ
ＧＡ形半導体装置の上面図である。FIG. 1 shows a fine pitch B according to an embodiment of the present invention.
It is a top view of a GA type semiconductor device.

【図２】（ａ）は、本発明の一実施の形態による半導体
装置の断面図、（ｂ）は、半導体装置に形成されたダ
ム、およびその近傍を拡大した説明図である。FIG. 2A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2B is an enlarged explanatory view of a dam formed in the semiconductor device and the vicinity thereof.

【図３】（ａ）は、本発明の他の実施の形態による半導
体装置の断面図、（ｂ）は、半導体装置に形成されたダ
ム、およびその近傍を拡大した説明図である。FIG. 3A is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3B is an enlarged explanatory view of a dam formed in the semiconductor device and its vicinity.

【符号の説明】[Explanation of symbols]

１ 半導体装置 ２ プリント配線基板 ２ａ 基板コア ２ｂ ボンディング電極（接続用電極） ２ｃ ソルダレジスト ２ｄ ダム ２ｅ 溝（ダム） ３ 半導体チップ ３ａ 電極（チップ電極） ４ 接着材 ５ ボンディングワイヤ ６ 封止樹脂 ７ はんだバンプ Reference Signs List 1 semiconductor device 2 printed wiring board 2a substrate core 2b bonding electrode (connection electrode) 2c solder resist 2d dam 2e groove (dam) 3 semiconductor chip 3a electrode (chip electrode) 4 adhesive 5 bonding wire 6 sealing resin 7 solder bump

───────────────────────────────────────────────────── フロントページの続き (72)発明者 後藤 正克 北海道亀田郡七飯町字中島145番地 日立 北海セミコンダクタ株式会社内 Ｆターム(参考） 4M109 AA01 BA04 DB16 GA10 5F044 AA02 JJ03 5F047 AA17 AB00 BA23 BA33 BB16 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masakatsu Goto 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido F-term in Hitachi Hokkai Semiconductor Co., Ltd. 4M109 AA01 BA04 DB16 GA10 5F044 AA02 JJ03 5F047 AA17 AB00 BA23 BA33 BB16

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 プリント配線基板の主面に半導体チップ
が搭載され、前記プリント配線基板の主面に形成された
接続用電極と前記半導体チップに形成されたチップ電極
とがボンディングワイヤを介して接続された半導体装置
であって、前記プリント配線基板の接続用電極と前記半
導体チップの外周部との間に、前記半導体チップを前記
プリント配線基板に接着させる接着材の流出を防止する
ダムを備えたことを特徴とする半導体装置。A semiconductor chip is mounted on a main surface of a printed wiring board, and connection electrodes formed on the main surface of the printed wiring board are connected to chip electrodes formed on the semiconductor chip via bonding wires. A semiconductor device, comprising a dam between an electrode for connection of the printed wiring board and an outer peripheral portion of the semiconductor chip for preventing an adhesive material for bonding the semiconductor chip to the printed wiring board from flowing out. A semiconductor device characterized by the above-mentioned.
JP2000074065A 2000-03-16 2000-03-16 Semiconductor device Pending JP2001267452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000074065A JP2001267452A (en) 2000-03-16 2000-03-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000074065A JP2001267452A (en) 2000-03-16 2000-03-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2001267452A true JP2001267452A (en) 2001-09-28

Family

ID=18592178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000074065A Pending JP2001267452A (en) 2000-03-16 2000-03-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2001267452A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066551A (en) * 2004-08-25 2006-03-09 Renesas Technology Corp Method for manufacturing semiconductor device
WO2010001505A1 (en) * 2008-07-02 2010-01-07 オムロン株式会社 Electronic component
WO2016002360A1 (en) * 2014-07-04 2016-01-07 株式会社イースタン Method for producing wiring board, and wiring board
JP2016139731A (en) * 2015-01-28 2016-08-04 ミツミ電機株式会社 Module and method of manufacturing the same
WO2022264822A1 (en) * 2021-06-14 2022-12-22 株式会社村田製作所 Secondary battery

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066551A (en) * 2004-08-25 2006-03-09 Renesas Technology Corp Method for manufacturing semiconductor device
JP4565931B2 (en) * 2004-08-25 2010-10-20 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
WO2010001505A1 (en) * 2008-07-02 2010-01-07 オムロン株式会社 Electronic component
US8274797B2 (en) 2008-07-02 2012-09-25 Omron Corporation Electronic component
US9922923B2 (en) 2014-07-04 2018-03-20 Kabushiki Kaisha Eastern Method of manufacturing wiring substrate and wiring substrate
JP2016018815A (en) * 2014-07-04 2016-02-01 株式会社イースタン Method of manufacturing wiring board and wiring board
CN106463471A (en) * 2014-07-04 2017-02-22 株式会社伊斯丹 Method for producing wiring board, and wiring board
WO2016002360A1 (en) * 2014-07-04 2016-01-07 株式会社イースタン Method for producing wiring board, and wiring board
CN106463471B (en) * 2014-07-04 2019-03-08 株式会社伊斯丹 The manufacturing method and wiring substrate of wiring substrate
TWI666736B (en) * 2014-07-04 2019-07-21 日商依斯特恩股份有限公司 Manufacturing method of wiring board and wiring board
JP2016139731A (en) * 2015-01-28 2016-08-04 ミツミ電機株式会社 Module and method of manufacturing the same
KR20160092915A (en) * 2015-01-28 2016-08-05 미쓰미덴기가부시기가이샤 Module and manufacturing method thereof
TWI677955B (en) * 2015-01-28 2019-11-21 日商三美電機股份有限公司 Module and manufacturing method thereof
KR102403971B1 (en) * 2015-01-28 2022-05-31 미쓰미덴기가부시기가이샤 Module and manufacturing method thereof
WO2022264822A1 (en) * 2021-06-14 2022-12-22 株式会社村田製作所 Secondary battery

Similar Documents

Publication Publication Date Title
US6734557B2 (en) Semiconductor device
US7224073B2 (en) Substrate for solder joint
KR100449307B1 (en) Semiconductor device and method for manufacturing the same
US6864588B2 (en) MCM package with bridge connection
US7015591B2 (en) Exposed pad module integrating a passive device therein
JP3150253B2 (en) Semiconductor device, its manufacturing method and mounting method
US20020119595A1 (en) Semiconductor package using tape circuit board with a groove for preventing encapsulant from overflowing and manufacturing method thereof
JP3478139B2 (en) Lead frame manufacturing method
KR100292033B1 (en) Semiconductor chip package and method for manufacturing same
JP2001267452A (en) Semiconductor device
JP2000040676A (en) Manufacture of semiconductor device
JP2001024133A (en) Lead frame, resin sealed semiconductor device employing it and manufacture thereof
JPH11260990A (en) Lead frame, resin-sealed semiconductor device and its manufacture
JPH11345900A (en) Semiconductor device
JP2003046034A (en) Resin-sealed semiconductor device
JP2003023243A (en) Wiring board
KR20110013902A (en) Package and manufacturing method thereof
JP3875407B2 (en) Semiconductor package
JPH10154766A (en) Manufacture of semiconductor package and semiconductor package
KR200278534Y1 (en) Chip size package
KR200172710Y1 (en) Chip size package
JP2001358253A (en) Bga type semiconductor device
JP2001024033A (en) Tape for mounting semiconductor elements semiconductor device and manufacture thereof
JP2006351607A (en) Circuit board, its manufacturing method and manufacturing method of semiconductor package
KR20030033706A (en) Flipchip Package