JPH0997857A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH0997857A
JPH0997857A JP7251566A JP25156695A JPH0997857A JP H0997857 A JPH0997857 A JP H0997857A JP 7251566 A JP7251566 A JP 7251566A JP 25156695 A JP25156695 A JP 25156695A JP H0997857 A JPH0997857 A JP H0997857A
Authority
JP
Japan
Prior art keywords
metal plate
semiconductor device
insulating sheet
fixed
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7251566A
Other languages
Japanese (ja)
Inventor
Nobuyuki Mori
伸之 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP7251566A priority Critical patent/JPH0997857A/en
Publication of JPH0997857A publication Critical patent/JPH0997857A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the thermal resistance of a package. SOLUTION: An IC chip 2 is fixed to one main surface of a metal plate 1 and at the same time a wire 4 which is electrically connected to the pad of the chip 2 is fixed via an insulation sheet 8, and a solder ball 6 which becomes a protruding electrode to be electrically connected to the wire 4 is adhered also onto the other main surface of the metal plate 1 via the insulation sheet 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置とその製
造方法に関し、特にBGA(Ball GridArr
ay)型の集積回路パッケージの構造とその製作方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a BGA (Ball Grid Arr).
The present invention relates to a structure of an ay) type integrated circuit package and a manufacturing method thereof.

【0002】[0002]

【従来の技術】この種のパッケージを備えた半導体装置
は、極めて多数の外部端子を必要とする場合等に適して
いる。
2. Description of the Related Art A semiconductor device provided with this type of package is suitable for a case where an extremely large number of external terminals are required.

【0003】ちなみに、この種のパッケージを記載した
「NIKKEI MICRODEVICES」(199
4年3月号,第62頁)にみられる図8の断面図を参照
すると、この半導体装置は、プリント基板35の上主表
面にICチップ3が固着され、ICチップ30の主表面
に配列された多数のパッドと、プリント基板35の主表
面に形成された配線とを、各々ボンディング・ワイヤで
接続し、さらにモールド樹脂32で、少なくともICチ
ップ30やワイヤ31等を覆っている。プリント基板3
5の裏面(下主表面)には、突起電極となる多数の半田
バンプ34が格子状に配列され、内面が金属導体からな
る多数の貫通穴33は、上主表面の配線と、半田バンプ
34に接続された配線とを、各々電気的に接続してい
る。この半導体装置は、実装基板(マザーボード)上に
載置され、半田バンプ34をリフロー等で溶融し、実装
基板上の電極と接続している。
Incidentally, "NIKKEI MICRODEVICES" (199 which describes this type of package)
8 (March 4, issue, page 62), this semiconductor device has an IC chip 3 fixed to the upper main surface of a printed circuit board 35 and arranged on the main surface of the IC chip 30. The numerous pads formed and the wiring formed on the main surface of the printed circuit board 35 are connected to each other by bonding wires, and at least the IC chip 30 and the wires 31 are covered with the molding resin 32. Printed circuit board 3
On the back surface (lower main surface) of FIG. 5, a large number of solder bumps 34, which will be the protruding electrodes, are arranged in a grid pattern, and on the inner surface, a large number of through-holes 33 made of a metal conductor will be used. Are electrically connected to the wiring connected to. This semiconductor device is placed on a mounting substrate (motherboard), the solder bumps 34 are melted by reflowing or the like, and are connected to the electrodes on the mounting substrate.

【0004】このような半導体装置で使用しているプリ
ント基板35は、加工性が良好であること、貫通穴を形
成し易いことや、原材料が安いこと等の理由により、絶
縁性の合成樹脂基体が用いられている。
The printed circuit board 35 used in such a semiconductor device has an insulating synthetic resin substrate because of its good workability, easy formation of through holes, inexpensive raw materials, and the like. Is used.

【0005】しかしながら、このようなプリント基板3
5は、熱伝導性が良好でないため、ICチップ30から
実装基板までの熱抵抗が高くなり、特にICチップ30
の消費電力が大きい場合には、ジャンクション温度が上
昇し、誤動作や短寿命等の問題を行き起こし、まれにI
Cチップ30の熱破壊に至ることがある。特に、高速動
作を行うICチップ30の電流量は大きく、消費電力の
増大は避けることができない。また、高集積化にともな
い、消費電力が増大する。
However, such a printed circuit board 3
In No. 5, since the thermal conductivity is not good, the thermal resistance from the IC chip 30 to the mounting substrate becomes high, and especially the IC chip 30
If the power consumption is large, the junction temperature rises, which causes problems such as malfunction and short life.
The C chip 30 may be destroyed by heat. In particular, the amount of current of the IC chip 30 that operates at high speed is large, and an increase in power consumption cannot be avoided. In addition, power consumption increases with high integration.

【0006】そこで、パッケージ自体に大きなヒートシ
ンクを備えることも考えられるが、これでは実装堆積が
増大する不利があるだけでなく、実装筐体に収納できな
くなる心配もある。
Therefore, it is conceivable to provide the package itself with a large heat sink, but this not only has the disadvantage of increasing the mounting deposition, but also may make it impossible to store the package in the mounting housing.

【0007】[0007]

【発明が解決しようとする課題】以上のような諸問題点
等に鑑み、本発明では、次の課題を掲げる。 (1)パッケージの熱抵抗を小さくし、ICチップで発
生する熱を拡散し易くすること。 (2)ICチップの高速動作化,高集積化が進んでも、
誤動作を引き起こしたり、寿命が短かくなることのない
ようにすること。 (3)ICチップで発生する熱が、主に実装基板を介し
て、放散し易くすること。 (4)半導体実装の外形寸法が増大しないようにするこ
と。 (5)ICチップのジャンクション温度の上昇を抑え、
高い信頼性を備えた半導体装置を提供できるようにする
こと。
In view of the above problems and the like, the present invention has the following problems. (1) To reduce the thermal resistance of the package and to easily diffuse the heat generated in the IC chip. (2) Even if high-speed operation and high integration of IC chips are advanced,
Do not cause a malfunction or shorten the life of the product. (3) The heat generated by the IC chip should be easily dissipated mainly through the mounting board. (4) Make sure that the external dimensions of the semiconductor package do not increase. (5) To suppress the rise in junction temperature of the IC chip,
To provide a semiconductor device with high reliability.

【0008】[0008]

【課題を解決するための手段】本発明の第1の構成は、
金属板の一主表面上に、半導体チップが固着されると共
に、この半導体チップのパッドと電気的に接続された第
1の配線が絶縁シートを介して固着され、前記金属板の
他主表面上に、第2の配線と電気的に接続される突起電
極が絶縁シートを介して固着されていることを特徴とす
る。
The first structure of the present invention is as follows.
The semiconductor chip is fixed to one main surface of the metal plate, and the first wiring electrically connected to the pad of the semiconductor chip is fixed to the other main surface of the metal plate through the insulating sheet. In addition, a protruding electrode electrically connected to the second wiring is fixed via an insulating sheet.

【0009】特に、前記金属板の側面上に、前記第1,
第2の配線を互いに連絡する配線が絶縁シートを介して
固着されていることを特徴とし、さらに前記一主表面上
の絶縁シートと、前記側面上の絶縁シートと、前記他主
表面上の絶縁シートとが、一体のシートとなっているこ
とも特徴とする。
Particularly, on the side surface of the metal plate, the first,
Wirings connecting the second wirings to each other are fixed via an insulating sheet, and further, the insulating sheet on the one main surface, the insulating sheet on the side surface, and the insulating on the other main surface. Another feature is that the seat and the seat are integrated.

【0010】また、特に前記金属板は、銅を主材料とし
た金属基体に金メッキの施されたものであることを特徴
とする。
Further, in particular, the metal plate is characterized in that a metal base body mainly made of copper is plated with gold.

【0011】さらに、特に前記金属板の側面は曲面とな
っているか、または前記主表面との間に面取りが施され
ている平面となっていることも特徴とし、特に前記金属
板の側面と前記絶縁シートとの間には、隙間が設けられ
ていることも特徴とする。
Further, in particular, the side surface of the metal plate is a curved surface or a flat surface chamfered between the side surface of the metal plate and the side surface of the metal plate. A feature is that a gap is provided between the insulating sheet and the insulating sheet.

【0012】前記第1の構成に加えて、少なくとも前記
金属板の側面上の配線を覆うように、絶縁枠が取り付け
られていることを特徴とする。
In addition to the first structure, an insulating frame is attached so as to cover at least the wiring on the side surface of the metal plate.

【0013】本発明の第2の構成は、半導体チップのパ
ッドと各々電気的に接続される配線が絶縁シートの一表
面に配置されたテープを使用する半導体装置の製造方法
において、前記絶縁シートの一表面と同一の表面に前記
配線に電気的に接続されかつこの半導体装置を実装する
基板の電極に接続するための突起電極が、形成されるこ
とを特徴とする。
A second structure of the present invention is a method for manufacturing a semiconductor device, which uses a tape in which wirings electrically connected to pads of a semiconductor chip are arranged on one surface of an insulating sheet. A protrusion electrode for electrically connecting to the wiring and for connecting to an electrode of a substrate on which the semiconductor device is mounted is formed on the same surface as one surface.

【0014】特に前記テープのうち前記突起電極の形成
される部分を、半導体チップの固着される金属板を挟ん
で折り曲げ、この金属板に固着することを特徴とし、さ
らに前記テープのうち前記突起電極の形成される部分が
折り曲げられるように、前記金属板を、前記テープと所
定の角度で固着することも特徴とする。
In particular, the portion of the tape on which the protruding electrodes are formed is bent by sandwiching a metal plate to which a semiconductor chip is fixed, and is fixed to the metal plate. It is also characterized in that the metal plate is fixed to the tape at a predetermined angle so that the portion in which is formed can be bent.

【0015】本発明の第1の構成によれば、半導体装置
の全堆積の大部分を金属板で召めることになるため、金
属板の熱容量が大きくでき、また金属板の主表面及び側
面から熱放散を行うことができるため、極めて熱抵抗の
低いパッケージとなる。
According to the first configuration of the present invention, since most of the total deposition of the semiconductor device can be carried out by the metal plate, the heat capacity of the metal plate can be increased, and the main surface and side surface of the metal plate can be increased. Since heat can be dissipated from the package, the package has extremely low thermal resistance.

【0016】特に、絶縁シート,配線を各々別々に製造
せず、一度に製造できるため、製造工程が増加すること
なく、また貫通穴を形成する必要がない。また、金属板
の側面が曲面等になっているため、絶縁シート及び配線
が破損する心配がない。
In particular, since the insulating sheet and the wiring can be manufactured at once without separately manufacturing them, the number of manufacturing steps does not increase and it is not necessary to form the through holes. Further, since the side surface of the metal plate is a curved surface or the like, there is no fear of damaging the insulating sheet and the wiring.

【0017】さらに、隙間が設けられている部分は、突
起電極の配列を、より正しい位置に設定することが容易
である。絶縁枠が取り付けられた場合には、取り扱い上
配線を破損する心配がない。
Further, it is easy to set the arrangement of the protruding electrodes at a more correct position in the portion where the gap is provided. When the insulating frame is attached, there is no risk of damaging the wiring in handling.

【0018】本発明の第2の構成によれば、突起電極を
形成する部分と半導体チップと接続する部分とを、同一
の絶縁シート上に形成できるため、テープの製造が容易
となる。
According to the second structure of the present invention, the portion for forming the protruding electrode and the portion for connecting to the semiconductor chip can be formed on the same insulating sheet, so that the tape can be easily manufactured.

【0019】特に、テープを折り曲げるだけでよいた
め、貫通穴等を別途製造する必要がない。また、折り曲
げられるように、金属板の角度を設定するだけでよいか
ら、格別製造工程を増加することがなく、自動化にも適
している。
In particular, since it is only necessary to bend the tape, it is not necessary to separately manufacture a through hole or the like. Further, since it is sufficient to set the angle of the metal plate so that it can be bent, it is suitable for automation without increasing the number of special manufacturing steps.

【0020】[0020]

【発明の実施の形態】本発明の第1の実施の形態を示す
図1の平面図を参照すると、この半導体装置は、製造段
階中のものであり、まずTABテープ3とこの下に位置
する金属板1とが用意される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the plan view of FIG. 1 showing a first embodiment of the present invention, this semiconductor device is in a manufacturing stage. First, a TAB tape 3 and a lower part thereof are located. The metal plate 1 is prepared.

【0021】金属板1は、熱伝導良好な例えば銅を主材
料とした金属基体に金メッキしたもので、正方形の上主
面及び下主面を有し、一定の厚さ(0.5mm乃至5.
0mm)を備える。この金属板1の中央にはICチップ
2が固着される。金属板1の四方の側面は、後述する半
円形断面のような曲線断面を呈している。
The metal plate 1 is a metal substrate mainly made of copper, which has good heat conductivity, and is plated with gold. The metal plate 1 has a square upper main surface and a lower main surface, and has a constant thickness (0.5 mm to 5 mm). .
0 mm). An IC chip 2 is fixed to the center of the metal plate 1. The four side surfaces of the metal plate 1 have a curved cross section such as a semicircular cross section described later.

【0022】TABテープ3は、正方形の外形を呈し、
ポリイミドフィルムのような電気的絶縁性が良好で、1
0μ乃至30μ程度の折り曲げが容易な弾力性のある合
成樹脂の絶縁シート8が選ばれる。このフィルムの上面
には、突起電極となる半田ボール6の固着するランドが
所定間隔で配列され、ここから各々配線4が伸び、イン
ナーリード5と電気的に接続される。この配線4,イン
ナーリード5は、10μ乃至30μ厚の金が好ましい。
絶縁シート8の中央部分は、ICチップ2よりも若干大
きい方形の開口部13があり、各辺の中程には、切り込
み9が設けられる。この切り込む9は、後工程でテープ
3を折り曲げ易くすると共に、寸法上のクリアランスを
確保するように、三角形と円形との組み合わせの平面形
状を呈する。インナーリード5の部分には、絶縁シート
8がなく、開口部13となる。
The TAB tape 3 has a square outer shape,
Good electrical insulation like polyimide film, 1
An elastic synthetic resin insulating sheet 8 which can be easily bent by about 0 μ to 30 μ is selected. On the upper surface of this film, lands to which solder balls 6 serving as protruding electrodes are fixed are arranged at predetermined intervals, from which wirings 4 extend and are electrically connected to inner leads 5. The wiring 4 and the inner leads 5 are preferably made of gold having a thickness of 10 μm to 30 μm.
The central portion of the insulating sheet 8 has a rectangular opening 13 slightly larger than the IC chip 2, and a notch 9 is provided in the middle of each side. The cut 9 has a planar shape of a combination of a triangle and a circle so that the tape 3 can be easily bent in a later step and a dimensional clearance is secured. The portion of the inner lead 5 does not have the insulating sheet 8 and serves as the opening 13.

【0023】まず、TABテープ3の下に、金属板1が
45度の平面角度でかつ中央に正確に位置合わせされた
後、インナーリード5と、ICチップの主表面の電極と
が、熱圧着等により各々電気的に接続される。この際
に、TABテープ3と放熱板1とをすでに接着しておく
ことが好ましい。
First, the metal plate 1 is accurately aligned with the center of the TAB tape 3 at a plane angle of 45 degrees, and then the inner leads 5 and the electrodes on the main surface of the IC chip are thermocompression bonded. Etc. are electrically connected to each other. At this time, it is preferable that the TAB tape 3 and the heat dissipation plate 1 are already bonded.

【0024】次に、TABテープ3は、折り曲げ線1
1,12に沿っていわゆる山折りとなるように折り曲げ
て、金属板1を包むようにする。
Next, the TAB tape 3 is the bending line 1
The metal plate 1 is wrapped along 1, 2 so as to be a so-called mountain fold.

【0025】この時の金属板1の裏面の状態を示す図2
の平面図を参照すると、TABテープ3は、四方から包
むように、金属板1の裏面を覆っている。この際、TA
Bテープ3の端部が互いに重なり合うことのないよう
に、かつ端部同士が離間しないように、正確に位置合わ
せを行い、接着する。こうして、所定間隔で配列された
半田ボール6が完成する。尚、この半田ボール6は、こ
の工程の後に、半田ボール6が完成する。尚、この半田
ボール6は、この工程の後に、半田リフロー等により、
形成してもよい。さらに、配線4の部分には、絶縁性被
膜が形成されることが好ましい。
FIG. 2 showing the state of the back surface of the metal plate 1 at this time.
2, the TAB tape 3 covers the back surface of the metal plate 1 so as to wrap it from all sides. At this time, TA
The B tapes 3 are accurately aligned and bonded so that the ends do not overlap each other and the ends do not separate from each other. In this way, the solder balls 6 arranged at predetermined intervals are completed. The solder balls 6 are completed after this step. It should be noted that this solder ball 6 is formed by solder reflow or the like after this step.
You may form. Further, it is preferable that an insulating film is formed on the wiring 4.

【0026】図2のA−A′線の断面図を示す図3を参
照すると、TABテープ3の上面の配線4は、金属板1
の半円形断面を呈する側面7を経て、裏面にまで達して
いる。
Referring to FIG. 3 which is a sectional view taken along the line AA ′ of FIG. 2, the wiring 4 on the upper surface of the TAB tape 3 is formed by the metal plate 1.
Through a side surface 7 having a semicircular cross section, reaching the back surface.

【0027】次に、少なくともインナーリード5,IC
チップ2の表面は、モールド樹脂10で覆う。尚図3に
おいては中心線16を軸に左右対称性を有しているの
で、左側のみを図示した。
Next, at least the inner lead 5 and the IC
The surface of the chip 2 is covered with the mold resin 10. Incidentally, in FIG. 3, since it has a left-right symmetry with the center line 16 as an axis, only the left side is shown.

【0028】半田ボール6の配列をより正確に行うため
には、図4の断面図に示すように、側面7とTABテー
プ3との間に隙間14ができるように、金属板1の寸法
を10μ乃至100μ程度小さくする。この隙間14が
存在するため、図2におけるテープ3の端部の位置合わ
せを行う上で寸法上の余裕があり、調整が簡単に行え
る。
In order to arrange the solder balls 6 more accurately, the metal plate 1 is dimensioned so that a gap 14 is formed between the side surface 7 and the TAB tape 3 as shown in the sectional view of FIG. It is reduced by about 10 μ to 100 μ. Due to the presence of the gap 14, there is a dimensional margin in aligning the ends of the tape 3 in FIG. 2, and the adjustment can be easily performed.

【0029】第1の実施の形態によれば、ICチップ2
が直接金属板1に固着されていることや、多数の半田ボ
ール6が薄い絶縁シート8を介して金属板1に接着され
ていること等により、ICチップ2で発生した熱は、金
属板1に伝導され、さらに、実装基板や上方にも拡散さ
れるため、極めて熱抵抗を小さくすることができ、また
従来のプリント基板に相当する位置に金属板1があるた
め、従来よりも熱容量が大きく、熱抵抗が小さいにもか
かわらず、従来と同一の外形寸法で済ますことができ、
実装構造が大きくなることがない。
According to the first embodiment, the IC chip 2
Are directly adhered to the metal plate 1, and a large number of solder balls 6 are adhered to the metal plate 1 through a thin insulating sheet 8. Therefore, the heat generated in the IC chip 2 is generated by the metal plate 1. Is further conducted to the mounting board and diffused upward, so that the thermal resistance can be made extremely small. Further, since the metal plate 1 is located at a position corresponding to the conventional printed circuit board, the heat capacity is larger than the conventional one. Despite the low thermal resistance, the same external dimensions as the conventional one can be used.
The mounting structure does not become large.

【0030】また、TABテープの同一表面上に、イン
ナーリードと突起電極とを形成できるため、別途突起電
極部分を形成する必要がなく、製造工程の増加を極力抑
えることができる。
Further, since the inner lead and the protruding electrode can be formed on the same surface of the TAB tape, it is not necessary to separately form the protruding electrode portion, and the increase in manufacturing process can be suppressed as much as possible.

【0031】第1の実施の形態では、金属板1の側面7
の断面形状を、半円形としたが、これに限定されるもの
ではなく、側面が金属板1の上面と直角で、かつ角が面
取りされていてもよい。また、切り込み9は、配線4の
ない領域にまで拡大して、大きく形成してもよい。配線
4や半田ボール等の数は、必要に応じて、適宜増減でき
る。
In the first embodiment, the side surface 7 of the metal plate 1 is
Although the cross-sectional shape of the above is a semicircle, the present invention is not limited to this, and the side surface may be perpendicular to the upper surface of the metal plate 1 and the corner may be chamfered. Further, the notch 9 may be enlarged to a region where the wiring 4 is absent and formed to be large. The number of wirings 4, solder balls, etc. can be increased or decreased as necessary.

【0032】TABテープ3において、後工程で接続の
必要のない部分の配線4は、すべて絶縁性の被覆で覆う
ことが好ましい。
In the TAB tape 3, it is preferable to cover all the wiring 4 in the portion which does not need to be connected in the subsequent step with an insulating coating.

【0033】TABテープ3、放熱板1の平面形状は、
正方形に限定したが、この他に、任意の長方形であって
もよい。この場合にも、図2に示したように、端部が隙
間なく固着される。
The plane shapes of the TAB tape 3 and the heat sink 1 are
Although it is limited to a square, any other rectangle may be used. Also in this case, as shown in FIG. 2, the ends are fixed without any gap.

【0034】本発明の第2の実施の形態を示す図5の断
面図を参照すると、この実施の形態は、金属板1の側面
上にTABテープ3を介して取り付けられた絶縁枠18
を備えること以外、図1乃至第4で示した第1の実施の
形態と共通する。
Referring to the cross-sectional view of FIG. 5 showing the second embodiment of the present invention, in this embodiment, the insulating frame 18 mounted on the side surface of the metal plate 1 via the TAB tape 3 is used.
1 is shared with the first embodiment shown in FIGS. 1 to 4.

【0035】この絶縁枠18は、金属板1の四側面と、
周端部とを取り囲む方形の枠であり、半導体装置の取り
扱い中に損傷することを防止するものであり、実装基板
に実装後は取り外してもよいが、装着したままで使用し
てもよい。この絶縁枠18は、図4で示したように、隙
間14がある場合でも、取り付けることができる。この
場合は、絶縁シート8が変形するため、これを吸収しえ
るような空間19を確保しておくことが好ましい。
The insulating frame 18 has four side surfaces of the metal plate 1,
It is a rectangular frame that surrounds the peripheral edge portion and prevents damage during handling of the semiconductor device. It may be removed after mounting on the mounting board, or it may be used as it is mounted. The insulating frame 18 can be attached even when there is the gap 14 as shown in FIG. In this case, since the insulating sheet 8 is deformed, it is preferable to secure a space 19 capable of absorbing this.

【0036】上述した第1,第2の実施の形態における
ICチップ2は、放熱板1の各辺に平行した形で中央部
分に固定されているが、TABテープ3とは45度の角
度をなしている。しかし、TABテープ3の各辺と平行
した形で、ICチップ2が固定されていてもよい。
The IC chip 2 in the above-described first and second embodiments is fixed to the central portion in a form parallel to each side of the heat dissipation plate 1, but forms an angle of 45 degrees with the TAB tape 3. I am doing it. However, the IC chip 2 may be fixed in a form parallel to each side of the TAB tape 3.

【0037】このように、TABテープの辺と平行した
ICチップを、本発明の第3の実施の形態として示す図
5の平面図、図6の裏面の平面図を参照すると、このT
ABテープ20は、この辺と平行な辺を持つ開口部1
3′を有する絶縁シート8′と、放熱板1′の周囲に沿
った半田ボール6分の配列と、ICチップ1′の電極に
対応したインナーリード5′の配列と、インナーリード
5′と半田ボール6′とを各々接続する配線4′とを備
える。
Thus, referring to the plan view of FIG. 5 showing the IC chip parallel to the side of the TAB tape as the third embodiment of the present invention and the plan view of the back surface of FIG. 6, this T
The AB tape 20 has an opening 1 having a side parallel to this side.
An insulating sheet 8'having 3 ', an array of solder balls 6 along the periphery of the heat sink 1', an array of inner leads 5'corresponding to the electrodes of the IC chip 1 ', and an inner lead 5'and solder. And a wire 4'for connecting each of the balls 6 '.

【0038】この他の構成及び製造方法は、上述した第
1,第2の実施の形態と共通するため、共通した算用数
字で図示するに留め、説明を省略する。
Since the other construction and manufacturing method are common to those of the above-described first and second embodiments, they are only shown with common arithmetic numerals and their explanations are omitted.

【0039】上述した第1乃至第3の実施の形態で使用
したTABテープ3,20は、同一形状のものを連続的
に接続して製造しておき、金属板1,1′を固着する時
に、分離することが好ましい。
The TAB tapes 3 and 20 used in the above-described first to third embodiments are manufactured by continuously connecting those having the same shape, and when fixing the metal plates 1 and 1 '. , Preferably separated.

【0040】[0040]

【発明の効果】以上説明した通り、本発明によれば、熱
容量が大きい金属板が放熱効果良く用いられ、また同一
絶縁シートの表面に突起電極と半導体チップのパッドと
接続される配線とが形成されるため、パッケージの熱抵
抗を小さくし、ICチップで発生する熱を放散し易くす
ると共に、製造工程の増加を極力抑えることができ、上
述した各課題がことごとく達成される。
As described above, according to the present invention, a metal plate having a large heat capacity is used with good heat dissipation effect, and a protruding electrode and a wiring connected to a pad of a semiconductor chip are formed on the surface of the same insulating sheet. Therefore, the heat resistance of the package can be reduced, the heat generated in the IC chip can be easily dissipated, and the increase in the number of manufacturing processes can be suppressed as much as possible, and each of the above-mentioned problems can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態のTABテープ等を
示す平面図である。
FIG. 1 is a plan view showing a TAB tape or the like according to a first embodiment of the present invention.

【図2】図1のTABテープを折り曲げた状態を裏面か
ら見た平面図である。
FIG. 2 is a plan view of the folded state of the TAB tape of FIG. 1, viewed from the back side.

【図3】図2のA−A′線の断面図である。FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG.

【図4】図3の他例を示す断面図である。FIG. 4 is a cross-sectional view showing another example of FIG.

【図5】本発明の第2の実施の形態を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a second embodiment of the present invention.

【図6】本発明の第3の実施の形態のTABテープ等を
示す平面図である。
FIG. 6 is a plan view showing a TAB tape or the like according to a third embodiment of the present invention.

【図7】図6のテープを折り曲げた状態を裏面から見た
平面図である。
FIG. 7 is a plan view of the folded state of the tape of FIG. 6 viewed from the back surface.

【図8】従来の半導体装置を示す断面図である。FIG. 8 is a sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1,1′ 金属板 2,2′,30 ICチップ 3,15,20 TABテープ 4,4′ 配線 5,5′ インナーリード 6,6′ 半田ボール 7 側面 8,8′ 絶縁シート 9 切り込み 10,32 モールド樹脂 11,12 折り曲げ線 13,13′ 開口部 14 隙間 16 中心線 18 絶縁枠 19 空間 31 ワイヤ 33 貫通穴 34 半田バンプ 35 プリント基板 1,1 'Metal plate 2,2', 30 IC chip 3,15,20 TAB tape 4,4 'Wiring 5,5' Inner lead 6,6 'Solder ball 7 Side surface 8,8' Insulation sheet 9 Notch 10, 32 Mold resin 11, 12 Bending line 13, 13 'Opening 14 Gap 16 Center line 18 Insulating frame 19 Space 31 Wire 33 Through hole 34 Solder bump 35 Printed circuit board

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 金属板の一主面上に、半導体チップが固
着されると共に、この半導体チップのパッドと電気的に
接続された第1の配線が絶縁シートを介して固着され、
前記金属板の他主面上に、第2の配線と電気的に接続さ
れる突起電極が絶縁シートを介して固着されていること
を特徴とする半導体装置。
1. A semiconductor chip is fixed on one main surface of a metal plate, and a first wiring electrically connected to a pad of the semiconductor chip is fixed via an insulating sheet,
A semiconductor device, wherein a protruding electrode electrically connected to the second wiring is fixed on the other main surface of the metal plate via an insulating sheet.
【請求項2】 前記金属板の側面上に、前記第1,第2
の配線を互いに連絡する配線が絶縁シートを介して固着
されている請求項1記載の半導体装置。
2. The first and second parts on the side surface of the metal plate.
The semiconductor device according to claim 1, wherein the wirings interconnecting the wirings are fixed to each other via an insulating sheet.
【請求項3】 前記一主面上の絶縁シートと、前記側面
上の絶縁シートと、前記他主面上の絶縁シートとが、一
体のシートとなっている請求項2記載の半導体装置。
3. The semiconductor device according to claim 2, wherein the insulating sheet on the one main surface, the insulating sheet on the side surface, and the insulating sheet on the other main surface are integrated sheets.
【請求項4】 前記金属板は、銅を主材料とした金属基
体に金メッキの施されたものである請求項1記載の半導
体装置。
4. The semiconductor device according to claim 1, wherein the metal plate is a metal base body mainly made of copper and plated with gold.
【請求項5】 前記金属板の側面は曲面となっている
か、または前記主表面との間に、面取りが施されている
平面となっている請求項1記載の半導体装置。
5. The semiconductor device according to claim 1, wherein a side surface of the metal plate is a curved surface or a flat surface chamfered between the side surface and the main surface.
【請求項6】 前記金属板の側面と前記絶縁シートとの
間には、隙間が設けられている請求項2記載の半導体装
置。
6. The semiconductor device according to claim 2, wherein a gap is provided between a side surface of the metal plate and the insulating sheet.
【請求項7】 少なくとも前記金属板の側面上の配線を
被うように、絶縁枠が取り付けられている請求項2及び
6記載の半導体装置。
7. The semiconductor device according to claim 2, wherein an insulating frame is attached so as to cover at least the wiring on the side surface of the metal plate.
【請求項8】 半導体チップのパッドと各々電気的に接
続される配線が絶縁シートの一表面に配置されたテープ
を使用する半導体装置の製造方法において、前記絶縁シ
ートの一表面と同一表面に、前記配線に電気的に接続さ
れかつこの半導体装置を実装する基板の電極に接続する
ための突起電極が、形成されることを特徴とする半導体
装置の製造方法。
8. A method of manufacturing a semiconductor device using a tape in which wirings each electrically connected to a pad of a semiconductor chip are arranged on one surface of an insulating sheet, the method comprising: A method of manufacturing a semiconductor device, comprising forming a protruding electrode electrically connected to the wiring and connected to an electrode of a substrate on which the semiconductor device is mounted.
【請求項9】 前記テープのうち前記突起電極の形成さ
れる部分を、半導体チップの固着される金属板を挟んで
折り曲げ、この金属板に固着する請求項8記載の半導体
装置の製造方法。
9. The method of manufacturing a semiconductor device according to claim 8, wherein a portion of the tape on which the protruding electrode is formed is bent with a metal plate to which a semiconductor chip is fixed sandwiched between and is fixed to the metal plate.
【請求項10】 前記テープのうち前記突起電極の形成
される部分が折り曲げられるように、前記金属板を、前
記テープと所定の角度で固着する請求項9記載の半導体
装置の製造方法。
10. The method of manufacturing a semiconductor device according to claim 9, wherein the metal plate is fixed to the tape at a predetermined angle so that a portion of the tape where the protruding electrode is formed is bent.
JP7251566A 1995-09-28 1995-09-28 Semiconductor device and its manufacture Pending JPH0997857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7251566A JPH0997857A (en) 1995-09-28 1995-09-28 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7251566A JPH0997857A (en) 1995-09-28 1995-09-28 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0997857A true JPH0997857A (en) 1997-04-08

Family

ID=17224728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7251566A Pending JPH0997857A (en) 1995-09-28 1995-09-28 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0997857A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769765A (en) * 1980-10-17 1982-04-28 Matsushita Electric Ind Co Ltd Sealed body of semiconductor device
JPH06295935A (en) * 1993-04-07 1994-10-21 Hitachi Ltd Semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769765A (en) * 1980-10-17 1982-04-28 Matsushita Electric Ind Co Ltd Sealed body of semiconductor device
JPH06295935A (en) * 1993-04-07 1994-10-21 Hitachi Ltd Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof

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