JPS6315448A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6315448A JPS6315448A JP61159226A JP15922686A JPS6315448A JP S6315448 A JPS6315448 A JP S6315448A JP 61159226 A JP61159226 A JP 61159226A JP 15922686 A JP15922686 A JP 15922686A JP S6315448 A JPS6315448 A JP S6315448A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin layer
- epoxy resin
- sealing resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 23
- 238000007789 sealing Methods 0.000 claims abstract description 20
- 239000003822 epoxy resin Substances 0.000 abstract description 16
- 229920000647 polyepoxide Polymers 0.000 abstract description 16
- 239000002390 adhesive tape Substances 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000203 mixture Substances 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000000843 powder Substances 0.000 abstract description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 abstract 2
- 239000010931 gold Substances 0.000 abstract 2
- 229910052737 gold Inorganic materials 0.000 abstract 2
- 239000004033 plastic Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、信頼性の優れた半導体装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a highly reliable semiconductor device.
トランジスタ、ＩＣ，ＬＳＩ等の半導体素子は、通常セ
ラミックパッケージもしくはプラスチックパッケージ等
により封止され、半導体装置化されている。上記セラミ
ックパッケージは、構成材料そのものが耐熱性を有し、
耐透湿性にも優れているため、温度、湿度に対して強く
、しがも中空パッケージのため機械的強度も高く信頼性
の高い封止が可能である。しかしながら、構成材料が比
較的高価なものであることと、量産性に劣る欠点がある
ため、最近では上記プラスチックパッケージを用いた樹
脂封止が主流になっている。この種の樹脂封止には、従
来からエポキシ樹脂組成物が使用されており、良好な成
績を収めている。このようにして樹脂封止（トランスフ
ァー成形におけるダイレクトモールド）された半導体素
子を第２図に示す。図において、■は半導体素子、２は
パッド、３はリード、４はプラスチックパッケージ、５
は金線である。しかしながら、半導体分野の技術革新に
よって集積度の向上とともに素子サイズの大形化、配線
の微細化が進み、パッケージも小形化、薄形化する（川
向にあり、これに伴って封止材料に対してより以上の信
頼性（得られる半導体装置の内部応力、耐湿信頼性等）
の向上が要望されている。特に、半導体封止に用いるエ
ポキシ樹脂組成物は、硬化温度から室温に冷却する過程
で、収縮に基づくかなりの内部応力を発生し、上記信頼
性を低下させるため、このような内部応力を低減させる
改善が望まれている。Semiconductor elements such as transistors, ICs, and LSIs are usually sealed with ceramic packages, plastic packages, or the like to form semiconductor devices. The above-mentioned ceramic package has heat resistance in the constituent material itself,
It also has excellent moisture permeability, so it is resistant to temperature and humidity, and because it is a hollow package, it has high mechanical strength and can be sealed with high reliability. However, since the constituent materials are relatively expensive and the mass productivity is poor, resin sealing using the above-mentioned plastic package has recently become mainstream. Epoxy resin compositions have conventionally been used for this type of resin sealing, and have achieved good results. A semiconductor element sealed with resin in this manner (direct molded in transfer molding) is shown in FIG. In the figure, ■ is a semiconductor element, 2 is a pad, 3 is a lead, 4 is a plastic package, and 5 is a
is a gold wire. However, due to technological innovations in the semiconductor field, the degree of integration has increased, element sizes have become larger, and interconnections have become finer, and packages have also become smaller and thinner. (Internal stress, moisture resistance reliability, etc. of the resulting semiconductor device)
There is a need for improvement. In particular, epoxy resin compositions used for semiconductor encapsulation generate considerable internal stress due to shrinkage in the process of cooling from the curing temperature to room temperature, reducing the reliability, so it is necessary to reduce such internal stress. Improvement is desired.
上記のように、これまでの封止用エポキシ樹脂組成物は
、硬化温度から室温に冷却する過程で、収縮に基づくか
なりの内部応力を発生していた。As described above, conventional epoxy resin compositions for sealing have generated considerable internal stress due to shrinkage during the cooling process from the curing temperature to room temperature.
そのため、生成プラスチックパッケージに損傷が生じた
り、また、配線に損傷が生じたりする等の弊害を生じて
いた。このような内部応力低減のために、ゴム粒子の添
加、液状エラストマーによる変性等が行われてきたが、
エポキシ樹脂マトリックス中にかかるゴム粒子のドメイ
ンが多量に存在することによりエポキシ樹脂組成物の流
動性が減じろ等の欠点も併発している。したがって、内
部応力の低減に充分な効果が得られていないのが実情で
ある。This has caused problems such as damage to the produced plastic package and damage to the wiring. In order to reduce such internal stress, addition of rubber particles, modification with liquid elastomer, etc. have been carried out.
Due to the presence of a large amount of such rubber particle domains in the epoxy resin matrix, there are also disadvantages such as a decrease in the fluidity of the epoxy resin composition. Therefore, the reality is that a sufficient effect in reducing internal stress has not been achieved.
この発明は、このような事情に鑑みなされたもので、内
部応力を低減させ、信頼性を向上させることをその目的
とする。The present invention was made in view of these circumstances, and its purpose is to reduce internal stress and improve reliability.
上記の目的を達成するため、この発明の半導体装置は、
半導体素子が封止樹脂層内に形成された空洞部内に空間
を保って収容されているという構成をとる。In order to achieve the above object, the semiconductor device of the present invention includes:
The structure is such that the semiconductor element is housed in a cavity formed in the sealing resin layer with space maintained therebetween.
すなわち、この発明者は、上記封止樹脂の内部応力に起
因する弊害を解消するために一連の研究を重ねた結果、
封止樹脂層内に空洞部を形成し、この空洞部内に半導体
素子を位置させるようにすれば内部応力がこの空洞部で
吸収され半導体素子に及ばないということをつきとめ、
この発明に到達した。That is, as a result of a series of studies conducted by the inventor in order to eliminate the adverse effects caused by the internal stress of the above-mentioned sealing resin,
It was discovered that if a cavity is formed in the sealing resin layer and the semiconductor element is placed within this cavity, the internal stress will be absorbed by the cavity and will not reach the semiconductor element.
We have arrived at this invention.
つぎに、この発明を実施例にもとづいて詳しく説明する
。Next, the present invention will be explained in detail based on examples.
第１図はこの発明の一実施例を示している。図において
、１は半導体素子、２はそれを支受するパッド、３はリ
ードであり、上記リード３およびパッド２でフレーム（
４２Ｐｉｎ ）が構成されている。５はリード３と半導
体素子１を接続する金線、６は上下２つ割りのキャップ
でエポキシ樹脂から構成されており、内部に空間を保っ
て、パッド２付の半導体素子１および金線５ならびにリ
ード３の先端部を収容している。７は上下２つ割りのキ
ャップ６を一体化するだめのフッ素樹脂接着テープ、８
はこれらの全体を被覆するエポキシ樹脂硬化体製の封止
樹脂層である。FIG. 1 shows an embodiment of the invention. In the figure, 1 is a semiconductor element, 2 is a pad that supports it, 3 is a lead, and the lead 3 and pad 2 are connected to the frame (
42Pin) is configured. 5 is a gold wire that connects the lead 3 and the semiconductor element 1, and 6 is a cap made of epoxy resin that is divided into upper and lower halves. The tip of the lead 3 is housed therein. 7 is a fluororesin adhesive tape for integrating the upper and lower halves of the cap 6, 8
is a sealing resin layer made of a cured epoxy resin that covers all of these.
上記のような構造の半導体装置は、例えばつぎのように
して製造することができる。すなわち、４２ピンＤＩＰ
フレームのパッド２に、半導体素子１を、導電性粉末入
りのポリイミド系接着剤ペースト（ＪＲ−１０００，日
東電工社製）を用いて接着し、金線５で上記フレームの
り一ド３に結線する。つぎに、上記パッド２付の半導体
素子１および金線５ならびにリード３の先端側部分を収
容するように、上下２つ割りのエポキシ樹脂製のキャッ
プ６の片方を位置決めしてフッ素樹脂接着テープ７で固
定させるとともに、同様にしてエポキシ樹脂製のキャッ
プの他方をフッ素樹脂接着テープ７で固定し両者を一体
化させる。ついで、これを低圧トランスファープレス１
（８（ｌンプレス、コータキ社製）に掛け、エポキシ樹
脂組成物（ＭＰ−１０，日東電気工業社′Ｍ＞を用いて
トランスファー成形（注入圧カニ ７０ ｋｇ／ａ（、
成形条件：１７５℃、１２０ｓｅｃ、後硬化１７５℃×
５ｈ）し、第１図に示すような半導体装置を製造した。A semiconductor device having the above structure can be manufactured, for example, as follows. That is, 42 pin DIP
The semiconductor element 1 is bonded to the pad 2 of the frame using a polyimide adhesive paste containing conductive powder (JR-1000, manufactured by Nitto Denko Corporation), and the gold wire 5 is connected to the frame glue pad 3. . Next, one side of the epoxy resin cap 6, which is divided into upper and lower halves, is positioned so as to accommodate the semiconductor element 1 with the pad 2, the gold wire 5, and the front end portion of the lead 3, and the fluororesin adhesive tape 7 is positioned. At the same time, the other end of the epoxy resin cap is similarly fixed with a fluororesin adhesive tape 7 to integrate the two. Next, transfer this to low pressure transfer press 1
Transfer molding (injection pressure crab 70 kg/a (,
Molding conditions: 175℃, 120sec, post-curing 175℃×
5h), and a semiconductor device as shown in FIG. 1 was manufactured.
上記のようにして得られた半導体装置は、簡易Ｘ線装置
（ＳＮ １００Ａ、ソフテックス社製）で観察したと
ころ、素子周辺部には中空部分が形成されており、半導
体素子ｌに加わる内部応力が０であることが推察できた
。When the semiconductor device obtained as described above was observed using a simple X-ray device (SN 100A, manufactured by Softex), it was found that a hollow portion was formed around the device, and internal stress applied to the semiconductor device l was observed. It can be inferred that is 0.
また、上記のようにして得られた半導体装置をプレッシ
ャークツカー装置（ＰＣＴ装置）に掛け、その結果を、
エポキシ樹脂キャップを使用しない以外は上記実施例と
同様にして製造された半導体装置（比較例品）と対照し
て第１表に示した。In addition, the semiconductor device obtained as described above is subjected to a pressure tester (PCT device), and the results are as follows.
Table 1 shows a comparison with a semiconductor device (comparative example product) manufactured in the same manner as in the above example except that the epoxy resin cap was not used.
第１表から実施例品は耐湿性能が著しく優れていること
がわかる。It can be seen from Table 1 that the example products have extremely excellent moisture resistance.
なお、上記の実施例では、封止樹脂層８内に形成する空
洞部をエポキシ樹脂製キャップ６を使用して形成してい
るが、空洞部の形成はこれに限定するものではな（、封
止樹脂層８内に空洞部ができればどのような方法を採用
してもよい。また、上記のようにキャップ６を使用する
場合には、封止樹脂層８の形成に使用する樹脂組成物と
キャップとをほぼ同材質のものに設定すると、相互の線
膨張係数が近似するようになって封止樹脂層８とキャッ
プ６との界面における内部応力が小さくなるため好まし
い。また、キャップ６に使用する樹脂は、上記のように
エポキシ樹脂に限定するものではなく、ポリエステル樹
脂等であっても差し支えはない。さらに、キャップ６を
止める接着テープ７としては、フッ素樹脂接着テープだ
けではなく、ポリイミド樹脂接着テープを使用してもよ
いしシリコーンゴム系接着テープを使用してもよい。特
に、上記のように・エポキシ樹脂製のキャップ６を使用
する場合には、その肉厚を０．５ ａｍ程度に設定する
ことが効果の点で好適である。In the above embodiment, the cavity formed in the sealing resin layer 8 is formed using the epoxy resin cap 6, but the formation of the cavity is not limited to this. Any method may be used as long as a cavity is formed in the sealing resin layer 8. In addition, when using the cap 6 as described above, the resin composition used to form the sealing resin layer 8 and It is preferable to use substantially the same material as the cap because the linear expansion coefficients of the cap and the cap become similar and the internal stress at the interface between the sealing resin layer 8 and the cap 6 is reduced. The resin to be used is not limited to epoxy resin as mentioned above, and may be polyester resin, etc.Furthermore, as the adhesive tape 7 for fixing the cap 6, not only fluororesin adhesive tape but also polyimide resin can be used. Adhesive tape or silicone rubber adhesive tape may be used.In particular, when using the cap 6 made of epoxy resin as described above, the thickness should be approximately 0.5 am. From the viewpoint of effectiveness, it is preferable to set it to .
以上のように、この発明の半導体装置は、半導体素子が
、封止樹脂層内に形成された空洞部内に空間を保って収
容されているため、製造過程で生じる内部応力が上記空
洞部で吸収され、半導体素子に及ばない。したがって、
封止樹脂層および配線等に損傷が生じていす、極めて信
頼性が高い。As described above, in the semiconductor device of the present invention, since the semiconductor element is housed in the cavity formed in the sealing resin layer with space maintained, internal stress generated during the manufacturing process is absorbed in the cavity. However, it is not as good as semiconductor devices. therefore,
Extremely reliable, with no damage to the sealing resin layer, wiring, etc.
第１図はこの発明の一実施例の構成を示す縦断面図、第
２図は従来例の構成を示す縦断面図である。
１・・・半導体素子 ２・・・パッド ３・・・リード
６・・・キャップ ７・・・フッ素樹脂接着テープ
８・・・封止樹脂層
゛第２図FIG. 1 is a longitudinal sectional view showing the structure of an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view showing the structure of a conventional example. 1...Semiconductor element 2...Pad 3...Lead 6...Cap 7...Fluororesin adhesive tape
8... Sealing resin layer (Figure 2)
Claims (3)
に空間を保つて収容されていることを特徴とする半導体
装置。(1) A semiconductor device characterized in that a semiconductor element is housed in a cavity formed in a sealing resin layer with space maintained therebetween.
に埋設されたキャップにより形成されている特許請求の
範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the cavity formed in the sealing resin layer is formed by a cap embedded in the sealing resin layer.
導体素子を収容したのちテープ止めにより一体化されて
いる特許請求の範囲第２項記載の半導体装置。(3) The semiconductor device according to claim 2, wherein the cap is divided into upper and lower halves, and after accommodating a semiconductor element therein, the cap is integrated with tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61159226A JPS6315448A (en) | 1986-07-07 | 1986-07-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61159226A JPS6315448A (en) | 1986-07-07 | 1986-07-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6315448A true JPS6315448A (en) | 1988-01-22 |
Family
ID=15689094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61159226A Pending JPS6315448A (en) | 1986-07-07 | 1986-07-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6315448A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0348361A2 (en) * | 1988-06-22 | 1989-12-27 | STMicroelectronics S.r.l. | Hollow plastic package for semiconductor devices |
| JPH0247857A (en) * | 1988-08-10 | 1990-02-16 | Nec Corp | Resin sealed type semiconductor device |
| US5446315A (en) * | 1991-03-08 | 1995-08-29 | Japan Gore-Tex, Inc. | Resin-sealed semiconductor device containing porous fluorocarbon resin |
| US5767569A (en) * | 1995-08-07 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Tab tape and semiconductor chip mounted on tab tape |
| US6191492B1 (en) * | 1988-08-26 | 2001-02-20 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device including a densified region |
| US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
| KR100931900B1 (en) * | 2006-06-01 | 2009-12-15 | 브로드콤 코포레이션 | Leadframe IC package with integrated heat spreaders at the top and bottom |
| EP3451374B1 (en) * | 2017-09-01 | 2023-03-15 | TDK-Micronas GmbH | Semiconductor device package |
-
1986
- 1986-07-07 JP JP61159226A patent/JPS6315448A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0348361A2 (en) * | 1988-06-22 | 1989-12-27 | STMicroelectronics S.r.l. | Hollow plastic package for semiconductor devices |
| JPH0247857A (en) * | 1988-08-10 | 1990-02-16 | Nec Corp | Resin sealed type semiconductor device |
| US6191492B1 (en) * | 1988-08-26 | 2001-02-20 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device including a densified region |
| US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
| US5446315A (en) * | 1991-03-08 | 1995-08-29 | Japan Gore-Tex, Inc. | Resin-sealed semiconductor device containing porous fluorocarbon resin |
| US5767569A (en) * | 1995-08-07 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Tab tape and semiconductor chip mounted on tab tape |
| KR100931900B1 (en) * | 2006-06-01 | 2009-12-15 | 브로드콤 코포레이션 | Leadframe IC package with integrated heat spreaders at the top and bottom |
| EP3451374B1 (en) * | 2017-09-01 | 2023-03-15 | TDK-Micronas GmbH | Semiconductor device package |
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