JPH08255854A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To enable a semiconductor device to be enhanced in signal transmission rate and lessened in electrical noises by a stray capacitance between a semiconductor chip and leads by a method wherein inner leads and a semiconductor chip on a chip circuit forming surface are sealed up with a resin composition which is a compound of thermosetting resin and substantially spherical organic filler. CONSTITUTION: A mixture composed of resol-phenolic resin as the basic resin, substantially spherical molten silica particles as the filler 0.1 to 100μm grain size, 5 to 20μm average grain diameter, and 0.90 maximum packing density, and various additives is melted by heating, solidified by cooling, and ground into resin sealing material. Then, a semiconductor device of LOC structure is sealed up with the resin sealing material through a transfer molding machine. Resin sealing martial is low in molten viscosity and excellent in fluidity, so that it is filled into narrow gaps inside the package without deforming a bonding wire of Au or a lead frame and carrying away a semiconductor chip 1 when semiconductor device of LOC structure is sealed up with the resin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a package of a high-integration large-scale integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in order to protect a semiconductor chip, the semiconductor chip is molded and sealed with a resin. Before performing this sealing, position the leads on the semiconductor chip,
Several methods have been used to attach.

For example, a lead frame having a tab in the center is used, and a semiconductor chip is attached and used before encapsulation. In this conventional technique, there is known a method of connecting an electrode pad near the periphery of a semiconductor chip to a corresponding inner lead with a bonding wire.

A common problem with prior art semiconductor packages has been the formation of cracks along the mold parting line which is the exit of the lead wire of the metal lead frame.

Another problem is that the path through which the environmental pollution source penetrates from the outside to the semiconductor chip along the metal leads is relatively short.

Further, another problem is that the bonding wires required to connect the inner leads to the electrode pads of the semiconductor chip are relatively long, and the bonding wires are crossed in order to alternately assign the input / output terminals. It was not possible.

Therefore, in order to solve the above problem, a plurality of inner leads are formed on the circuit formation surface of the semiconductor chip.
In a semiconductor device in which the semiconductor chip is adhered with an adhesive with an insulating film interposed therebetween, the inner lead and the semiconductor chip are electrically connected with a bonding wire and sealed with a mold resin, a circuit of the semiconductor chip is formed. A semiconductor device has been proposed in which a shared inner lead (bus bar inner lead) is provided near the center line in the longitudinal direction of the surface (Japanese Patent Laid-Open No. 61-241959).

[0008]

However, as a result of examining the above-mentioned conventional semiconductor device, the present inventor found the following problems.

That is, in the conventional semiconductor device, (1)
On the circuit forming surface of the semiconductor chip, a plurality of inner leads are adhered to the semiconductor chip with an insulating film interposed by an adhesive, but the stray capacitance between the inner leads and the semiconductor chip becomes large. However, there is a problem that the signal transmission speed becomes slower as the stray capacitance becomes larger and the electric noise becomes larger.

(2) Since the area of the insulating film is large, the amount of moisture absorbed increases, and the moisture absorbed during reflow vaporizes and expands in the package, causing a package crack.

(3) Since a polyimide resin is used as the material of the insulating film, the amount of moisture absorbed increases, and the moisture absorbed during the reflow vaporizes and expands in the package, causing package cracks. There was a problem of doing.

(4) Since an acrylic resin is used as the material of the adhesive, the adhesive is deteriorated by a pressure cooker test or the like, and reliability is improved due to problems such as electrical leakage between leads and corrosion of aluminum electrodes. There was a problem of deterioration.

(5) Since the polyimide-based resin coat for alpha (α) ray countermeasure is not coated on the entire circuit forming surface of the semiconductor chip, there is a problem that an error due to alpha (α) ray occurs.

(6) Although the common inner lead (bus bar inner lead) is used as the heat sink, the inner lead is not entirely covered on the element portion having a large heat generating portion.
There is a problem that the heat dissipation is insufficient in the device of 1 watt or more.

(7) Since the area of the insulating film made of the polyimide resin is large, there is a problem that it is weak against temperature cycle.

(8) Since wire bonding is performed beyond the common inner lead (bus bar inner lead), there is a problem that productivity is poor.

(9) Since the adhesive layer is soft and it is difficult to set the wire bonding conditions, there is a problem that productivity is poor.

(10) Since the workability for attaching the insulating film to the semiconductor chip is poor, there is a problem that productivity is poor.

(11) Since the semiconductor chip is only fixed by a part of the inner lead, the semiconductor chip is not sufficiently fixed. For this reason, since the semiconductor chip moves during resin encapsulation (molding), there is a problem that productivity is poor.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

It is an object of the present invention to provide a technique capable of improving the signal transmission speed and reducing the electrical noise due to the stray capacitance between the semiconductor chip and the lead in the semiconductor device.

Another object of the present invention is to provide a technique capable of improving the heat dissipation efficiency of the generated heat in the semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the influence of heat during reflow in a semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the influence of heat in a temperature cycle in a semiconductor device.

Another object of the present invention is to provide a technique capable of preventing the occurrence of molding defects in a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0027]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

The semiconductor chip is electrically connected by a bonding wire, and on the circuit forming surface of the semiconductor chip,
In a semiconductor device in which a plurality of arranged inner leads and the semiconductor chip are sealed with a resin, the sealing resin material is a resin composition in which a substantially spherical inorganic filler is mixed with a thermosetting resin. Characteristic semiconductor device.

The semiconductor chip is electrically connected by a bonding wire, and on the circuit forming surface of the semiconductor chip,
In a method of manufacturing a semiconductor device in which a plurality of arranged inner leads and the semiconductor chip are sealed with resin, there is a gap between the inner leads and the semiconductor chip main surface, and the resin sealing is the semiconductor chip. From the outer surface of the sealing body on the main surface side to the surface of the inner lead portion, and from the outer surface of the sealing body on the side opposite to the semiconductor chip main surface to the back surface of the semiconductor chip Of the lower flow path portion and an intermediate flow path portion in the gap between the inner lead and the semiconductor chip main surface which are formed narrower than the upper flow path portion or the lower flow path portion, and the sealing is performed. A method of manufacturing a semiconductor device, wherein a resin composition comprising a thermosetting resin mixed with a substantially spherical inorganic filler is used as the resin material.

Further, the spherical inorganic filler has a particle size distribution of 0.1 to 100 μm, an average particle diameter of 5 to 20 μm, and a maximum packing density of 0.8 or more, and the spherical inorganic filler is 70 in the resin composition. More than the weight percentage (wt%) was compounded.

Further, the encapsulating resin material is a resin composition containing, as the curable resin, at least one of a phenol-curable epoxy resin, a resole-type phenol resin, and a bismaleimide resin as a main component. The method for manufacturing a semiconductor device according to claim 9 or 10.

Further, the encapsulating resin material contains, as the curable resin, either a resol type phenol resin or a bismaleimide resin as a main component, and the molded product has a bending strength at 215 ° C. of 3 kgf / mm ^2. That is all.

Further, the sealing resin material as an inorganic filler has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20.
The fused silica is substantially spherical and has a maximum packing density of 0.8 or more.

Further, the sealing resin material as an inorganic filler has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20.
67.5 volume percentage (vo) of substantially spherical fused silica having a maximum packing density of 0.8 or more with respect to the entire composition.
1%) or more, the molded product has a linear expansion coefficient of 1.4 × 1
It is 0 to ⁵ / ° C. or less.

Further, when the sealing material is mixed with 10 times amount of ion-exchanged water and extracted at 120 ° C. for 100 hours, the pH of the extract is 3 to 7 and the electric conductivity is 200 μS / cm.
Hereinafter, the extraction amount of halogen ions, ammonia ions, and metal ions is 10 ppm or less.

Further, the plurality of inner leads are selected from inorganic or thermoplastic resin or thermosetting resin having a softening point higher than the bonding temperature as a filler in an adhesive for bonding to the semiconductor chip via an insulator. Spherical fine particles having a constant particle size are mixed.

(Operation) According to the present invention, an optimum insulator can be selected depending on the semiconductor element.

According to the present invention, (1) the filler has a particle size distribution of 0.1 to 100 μm, an average particle size of 5 to 20 μm,
The encapsulating material using substantially spherical fused silica having a maximum packing density of 0.8 or more has a lower melt viscosity and a higher fluidity of the material than the case where the rectangular fused silica which is used for one time is used. Since it is good, the gold (Au) wire and the lead are not deformed and the semiconductor chip is not swept away at the time of molding. Further, it is possible to fill the narrow gap of the package well.

(2) Since the sealing material using the spherical fused silica has little influence on the melt viscosity and fluidity of the material, the compounding amount can be increased to achieve low thermal expansion of the material. Therefore, the package has good crack resistance.

(3) Good reliability can be obtained by using a high-purity resole-type phenol resin or polyimide resin.

(4) A sealing material using a high-purity resole-type phenol resin or a polyimide resin has a high heat resistance of a molded product, and in particular, it has a high mechanical strength at high temperature, so that the package absorbs moisture. It is possible to obtain reflow resistance (package crack) in the case of being allowed to perform, or moisture resistance reliability and thermal shock resistance after reflow.

According to the present invention, a filler of spherical fine particles having a constant particle diameter is mixed as a filler in the adhesive of the present invention, so that the gap between the semiconductor chip and the lead is constant (same as the filler diameter). The control can be performed, and the variation in the capacitance between the semiconductor chip and the lead can be reduced.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows a resin-encapsulated semiconductor device for encapsulating a DRAM which is Embodiment 1 of the present invention.
(Partial cross-sectional perspective view), FIG. 2 (plan view) and FIG. 3 (cross-sectional view taken along the line ii in FIG. 2).

As shown in FIG. 1, FIG. 2 and FIG.
AM (semiconductor pellet) 1 SOJ (S mall O ut-line
It is sealed with a J-bend type resin-sealed package 2. The DRAM 1 has a large capacity of 16 [Mbit] × 1 [bit], and has a planar rectangular shape of 16.48 [mm] × 8.54 [mm]. This DRAM 1 is 400 [m
il] is sealed in the resin-sealed package 2.

A memory cell array and peripheral circuits are mainly arranged on the main surface of the DRAM 1. As will be described later in detail, the memory cell array has a plurality of memory cells (storage elements) that store 1-bit information arranged in a matrix. The peripheral circuit is composed of a direct peripheral circuit and an indirect peripheral circuit.
The direct peripheral circuit is a circuit for directly controlling the information writing operation and the information reading operation of the memory cell. Direct peripheral circuits include row address decoder circuits, column address decoder circuits,
Includes a sense amplifier circuit and the like. The indirect peripheral circuit is a circuit that indirectly controls the operation of the direct peripheral circuit. The indirect peripheral circuit includes a clock signal generation circuit, a buffer circuit and the like.

Inner leads 3A are arranged on the main surface of the DRAM 1, that is, on the surface on which the memory cell array and peripheral circuits are arranged. An insulating film 4 is interposed between the DRAM 1 and the inner lead 3A. The insulating film 4 is formed of, for example, a polyimide resin film. An adhesive layer (not shown) is provided on each surface of the insulating film 4 on the DRAM 1 side and the inner lead 3A side. As the adhesive layer, for example, a polyether amide imide resin or an epoxy resin is used. Resin-sealed package 2 of this kind employs a LOC (L ead O n C hip ) structure in which the inner leads 3A on DRAM 1. The resin-encapsulated package 2 that employs the LOC structure can freely route the inner leads 3A without being restricted by the shape of the DRAM 1. Therefore, the DRAM 1 having a large size corresponding to the routing can be sealed. That is, in the resin-encapsulated package 2 that adopts the LOC structure, the encapsulation size can be suppressed to be small even if the size of the DRAM 1 is increased due to the increase in capacity, so that the packaging density can be increased.

One end of the inner lead 3A is formed integrally with the outer lead 3B. The signals applied to the outer leads 3B are defined and numbered according to the standard. In FIG. 2, the front left end is the 1st terminal, and the front right end is the 14th terminal. The back side of the right end (the terminal number is shown in the inner lead 3A) is the 15th terminal, and the back side of the left end is the 28th terminal. That is, this resin-sealed package 2 has terminals 1-6, terminals 9-14, and 15-2.
It is composed of a total of 24 terminals including the 0th terminal and the 23rd to 28th terminals.

The first terminal is a power supply voltage Vcc terminal.
The power supply voltage Vcc is, for example, a circuit operating voltage of 5 [V]. No. 2 terminal is a data input signal terminal (D), No. 3 terminal is an empty terminal, No. 4 terminal is a write enable signal terminal (W), 5
The No. terminal is a row address strobe signal terminal (RE), and the No. 6 terminal is an address signal terminal (A ₁₁ ).

The 9th terminal is an address signal terminal (A ₁₀ ), 10
No. terminal is address signal terminal (A ₀ ), No. 11 terminal is address signal terminal (A ₁ ), No. 12 terminal is address signal terminal
Terminals (A ₂ ) and 13 are address signal terminals (A ₃ ). 1
The fourth terminal is a power supply voltage Vcc terminal. The 15th terminal is a reference voltage Vss terminal. The reference voltage Vss is, for example, a circuit reference voltage 0 [V]. The 16th terminal is an address signal terminal
(A ₄ ), the 17th terminal is the address signal terminal (A ₅ ), the 18th terminal is the address signal terminal (A ₆ ), the 19th terminal is the address signal terminal (A ₇ ), and the 20th terminal is the address signal terminal (A 5). ₈ ).

The 23rd terminal is an address signal terminal (A ₉ ), 2
The 4th terminal is an empty terminal, the 25th terminal is a column address strobe signal terminal (CE), the 26th terminal is an empty terminal, and the 27th terminal is a data output signal terminal. The 28th terminal is a reference voltage Vss terminal.

The other end of the inner lead 3A has a DR
The long sides of the rectangular shape of AM1 are crossed and extended to the center side of DRAM1. The other end of the inner lead 3A is DRA with the bonding wire 5 interposed.
It is connected to an external terminal (bonding pad) BP arranged in the central portion of M1. The bonding wire 5 uses an aluminum (Al) wire. Further, as the bonding wire 5, a gold (Au) wire, a copper (Cu) wire, a coated wire having a surface of a metal wire coated with an insulating resin, or the like may be used. The bonding wire 5 is bonded by a bonding method using thermocompression and ultrasonic vibration.

No. 1 terminal of the inner lead 3A,
The inner leads (Vcc) 3A of the 14th terminals are integrally formed, and the central portion of the DRAM 1 is extended in parallel with its long side. Similarly, the inner leads (Vss) 3A of the 15th and 28th terminals are integrally formed, and
The central portion of the RAM 1 is stretched in parallel with its long side. Inner lead (Vcc) 3A, inner lead (Vs
s) Each of the 3A is extended in parallel within the region defined by the tip on the other end side of the other inner leads 3A. This inner lead (Vcc) 3A, inner lead
Each of the (Vss) 3A is configured to be able to supply the power supply voltage Vcc and the reference voltage Vss to any position on the main surface of the DRAM 1. That is, the resin-sealed semiconductor device 2 is configured to easily absorb power source noise,
It is configured so that the operating speed of M1 can be increased.

A pellet supporting lead 3C is provided on the rectangular short side of the DRAM 1.

Each of the inner lead 3A, the outer lead 3B, and the pellet supporting lead 3C is cut and molded from the lead frame. The lead frame is made of, for example, Fe-Ni (for example, Ni content of 42 or 50).
[%]) Alloy, Cu, etc.

The DRAM 1, the bonding wire 5,
The inner lead 3A and the pellet supporting lead 3C are sealed with a resin sealing portion 6. The resin sealing portion 6 uses an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added in order to reduce the stress. Silicone rubber has the effect of reducing the coefficient of thermal expansion of the epoxy resin. The filler is formed of spherical silicon oxide particles, and similarly has a function of lowering the coefficient of thermal expansion.

Next, FIG. 3 (chip layout diagram) shows a schematic structure of the DRAM 1 sealed in the resin-sealed package 2.

As shown in FIG. 3, a memory cell array (MA) 11 is arranged on almost the entire surface of the DRAM 1.
The DRAM 1 of the present embodiment is not limited to this,
The memory cell array 11 is roughly divided into four memory cell arrays 11A to 11D. In FIG. 3, DRAM
Two memory cell arrays 11A and 11B are arranged on the upper side of 1, and two memory cell arrays 11C and 11B are arranged on the lower side.
1D is arranged. Each of the four divided memory cell arrays 11A to 11D is further subdivided into 16 memory cell arrays (MA) 11E. That is,
In the DRAM 1, 64 memory cell arrays 11E are arranged. One memory cell array 11E subdivided into 64 pieces has a capacity of 256 [Kbit].

A sense amplifier circuit (SA) 13 is arranged between each of the two memory cell arrays 11E of the 64 subdivided DRAMs. The sense amplifier circuit 13 is composed of a complementary MISFET (CMOS). A column address decoder circuit (YDEC) 12 is arranged at one end on the lower side of each of the memory cell arrays 11A and 11B of the four divided DRAMs 1.
Similarly, a column address decoder circuit (YDEC) 12 is provided at one upper end of each of the memory cell arrays 11C and 11D.
Is arranged.

A word driver circuit (WD) 14, a row address decoder circuit (XDEC) 15, and a unit mat control circuit 16 are provided at one end on the right side of each of the memory cell arrays 11A and 11C of the four divided DRAMs 1. Each of them is sequentially arranged from the left side to the right side. Similarly,
A word driver circuit 14, a row address decoder circuit 15, and a unit mat control circuit 16 are sequentially arranged from the right side to the left side at one end on the left side of each of the memory cell arrays 11B and 11D.

Each of the sense amplifier circuit 13, the column address decoder circuit 12, the word driver circuit 14, and the row address decoder circuit 15 constitutes a direct peripheral circuit of the peripheral circuits of the DRAM 1. The direct peripheral circuit is a circuit for directly controlling the memory cells arranged in the subdivided memory cell array 11E of the memory cell array 11.

Peripheral circuits 17 and external terminals BP are arranged between the memory cell arrays 11A and 11B of the four divided DRAM 1 and between the memory cell arrays 11C and 11D, respectively. Peripheral circuit 17
Are a main amplifier circuit 1701, an output buffer circuit 1702, a substrate potential generation circuit (Vss generator circuit)
1703 and a power supply circuit 1704 are arranged. A total of 16 main amplifier circuits 1701 are arranged in units of 4. A total of four output buffer circuits 1702 are arranged.

For the external terminal BP, the resin-encapsulated semiconductor device 2 has the LOC structure, and the inner lead 3A is extended to the central portion of the DRAM 1.
It is located in the central part of 1. The external terminals BP are arranged in the regions defined by the memory cell arrays 11A and 11C, 11B and 11D, respectively, from the upper end side to the lower end side of the DRAM 1. The signal applied to the external terminal BP has been described in the resin-sealed semiconductor device 2 shown in FIG. 2 described above, and thus the description thereof is omitted here. Basically, since the inner leads 3A to which the reference voltage (Vss) and the power supply voltage (Vcc) are applied extend from the upper end side to the lower end side on the surface of the DRAM 1, the DRAM 1 has its extending direction. A plurality of external terminals BP for the reference voltage (Vss) and the power supply voltage (Vcc) are arranged along the line. That is, DRA
M1 is configured so that the reference voltage (Vss) and the power supply voltage (Vcc) can be sufficiently supplied. Data input signal (D), data output signal (Q), address signal (A ₀ ~ A
₁₁ ), clock-related signals and control signals are arranged centrally in the DRAM 1.

Between the memory cell arrays 11A and 11C of the four divided DRAM1, 11B,
Peripheral circuits 18 are arranged between 11D. On the left side of the peripheral circuit 18, a row address strobe (RE) system circuit 1801, a write enable (W) system circuit 1802, a data input buffer circuit 1803, a VCC limiter circuit 1804, an X address driver circuit (logical stage) 1805, X. The system redundancy circuit 1806 and the X address buffer circuit 1807 are arranged. Peripheral circuit 1
A column address strobe (CE) system circuit 1808, a test circuit 1809, a VDL limiter circuit 1810, and a Y address driver circuit (logical stage) 181 are provided on the right side of FIG.
1, Y system redundancy circuit 1812, Y address buffer circuit 1
Each of 813 is arranged. In the center of the peripheral circuit 18, a Y address driver circuit (drive stage) 1814,
An X address driver circuit (drive stage) 1815 and a mat selection signal circuit (drive stage) 1816 are arranged.

The peripheral circuits 17 and 18 (including 16) are D
It is used as an indirect peripheral circuit of RAM1.

Next, details of the lead frame will be described.

The lead frame of the first embodiment is shown in FIG.
And as shown in FIG. 5 (plan view of the entire lead frame),
Twenty signal inner leads 3A ₁ and two common inner leads 3A ₂ are provided. The inner leads 3A (the signal inner leads 3A ₁ and the common inner leads 3A ₂ ) have an insulating film (insulator) 4 for the inner leads 3A as shown in FIGS. The stepped structure is such that the distance between the semiconductor chip 1 and the portion closer to the outer lead 3B than the portion bonded to is wider than the distance between the portion bonded to the insulating film (insulator) 4 and the semiconductor chip 1. There is. By thus forming the inner lead 3A with the stepped structure, the stray capacitance between the semiconductor chip and the lead becomes smaller than that of the conventional one, so that the signal transmission speed can be improved and the electrical noise can be reduced. .

Further, the main surface of the semiconductor chip 1 is adhered to the insulating film 4, the insulating film 4 and the inner lead 3 are bonded together.
For the adhesion with A, as shown in FIG. 6, an adhesive 7 is used. Moreover, as shown in FIG. 7, the adhesive 7 is not used for bonding the main surface of the semiconductor chip 1 and the insulating film 4, but is used only for bonding the insulating film 4 and the inner lead 3A. Is also good.

The inner lead 3A has the above-mentioned effects even when applied to a package in which the common inner lead 3A ₂ is not provided.

At a predetermined position of the lead frame,
As shown in FIGS. 1 and 5, a chip supporting lead (suspension lead) 3C for fixing the main surface of the semiconductor chip 1 by adhesion is provided.

As described above, the main surface of the semiconductor chip 1 is bonded and fixed by the suspension leads 3C which are not energized.
Since the semiconductor chip 1 is firmly fixed, the reliability and moisture resistance of the semiconductor device can be improved.

Next, the details of the insulating film 4 will be described.

The area occupied by the insulating film 4 on the main surface of the semiconductor chip 1 is at least ½ or less of the area of the semiconductor chip 1. As described above, since the area occupied by the insulating film 4 is at least ½ or less of the area of the semiconductor chip 1, the amount of moisture absorbed by the insulating film 4 is reduced. It is possible to prevent the influence of steam generated by the heat of the cycle. That is, it is possible to prevent cracks and the like from occurring in the package, so that the reliability of the semiconductor device can be improved.

Further, as a result, the stray capacitance between the semiconductor chip 1 and the leads becomes smaller than that of the conventional one, so that the signal transmission speed can be improved and the electrical noise can be reduced.

Further, the above-mentioned effect can be made more remarkable by setting the area for joining the insulating film 4 and the main surface of the semiconductor chip 1 to the minimum value that can be manufactured. Further, since the insulating film (insulating film) is used only in a portion of the inner lead that is bonded to the semiconductor chip, it is possible to reduce leakage between the leads.

Further, instead of the insulating film 4 on the main surface of the semiconductor chip 1, as shown in FIG. 8, a resin molded body 6 including a part of the inner leads 3A is used to form the semiconductor chip 1 and the semiconductor chip 1. The distance between the inner lead 3A and the inner lead 3A may be set sufficiently large to reduce the stray capacitance between the semiconductor chip 1 and the inner lead 3A.

By doing so, the resin molding 6
Since the mold resin (for example, resin) 2A and the mold resin (for example, resin) 2A are formed of a material having a good compatibility, the peeling between the peeling interface leads can be reduced.

The resin molding 6 and the semiconductor chip 1 may be bonded with an adhesive 7 as shown in FIG.

Base material of insulating film 4 and resin molded body 6
As the one, one selected from epoxy resin, BT (bismaleimide triazine) resin, phenol resin (resole resin, etc.), polyimide resin (aromatic polyimide or alicyclic polyimide having ether bond and carbonyl bond, etc.), etc. Alternatively, a plurality of resins are contained as a main component, and if necessary, an inorganic filler or a fiber curing agent, various additives, etc. are added to the resin for molding.

Other examples of the material of the base material of the insulating film 4 and the resin molded body 6 include alicyclic polyimide, polyester, polysulfone, aromatic polyetheramide, aromatic aromatic polyesterimide, polyphenylene sulfide, polyamide. The main component is a thermoplastic resin such as imide and its modified product, polyether ether ketone, polyether sulfone, and polyether amide imide, and if necessary, an inorganic filler or fiber, and an additive are added thereto for molding.

In addition, the insulating film 4 or the resin molding 6
As an adhesive for joining the inner lead 3A and the semiconductor chip 1, epoxy resin, BT resin, phenol resin (resole resin etc.) polyimide resin, isomerane resin, silicone resin and a plurality of these resins are used. It can be selected from modified thermosetting resins or thermoplastic resins such as aromatic polyetheramides, polyetheretherketones, polysulfones, aromatic polyesterimides, polyesters and alicyclic polyimides.

Further, in the case of surface mounting type integrated circuit such as SOJ, the vapor phase reflow soldering method or the infrared reflow soldering method is used when soldering is mounted on a printed circuit board (PCB). In this case, moisture absorbed in the package is reflowed. There is a case where the sealing resin is vaporized and expanded at a temperature (215 to 260 ° C.), peels off the adhesive at the chip interface, and the internal pressure of the peeled surface rises, and the sealing resin cracks.

In the LOC structure, since the inner lead 3A and the semiconductor chip 1 are joined by the insulating film 4 or the resin molded body 6, the insulating film 4 or the resin molded body 6 is formed.
The above-mentioned phenomenon is accelerated by its own moisture absorption. Therefore,
In order to reduce this, it is effective to reduce the volume of the insulating film 4 and reduce the amount of moisture absorption.

The lower limit of the bonding area is an area capable of withstanding an external force received in the steps of wire bonding and resin (resin) molding (sealing).

Now, the material properties of the insulating film 4 or the insulator of the resin molded body 6 will be examined.

A semiconductor device of LOC structure or COL (Ch
A material satisfying at least two of the following seven conditions is used as a bonding insulating material between the inner lead 3A and the semiconductor chip 1 in the semiconductor device having the ip on led) structure.

(1) The saturated moisture absorption rate is the same as or lower than that of the sealing resin.

This is effective in preventing resin cracks during vapor face solder (VPS).

(2) Dielectric constant of 4.0 (at 10 ³ H)
z, room temperature to 200 ° C.) or less.

This reduces the stray capacitance between the inner leads and the semiconductor chip.

(3) Barcol hardness at 200 ° C. is 20 or more.

This improves the wire bondability.

(4) The content of U and Th is 1 ppb or less,
The amount of soluble halogen element when extracted at 120 ° C. for 100 hours is 10 ppm or less.

This is effective in preventing soft errors and improving moisture resistance.

(5) Adhesiveness to the semiconductor chip and the inner leads is good.

This can secure wire bondability, improve moisture resistance, prevent current leakage between inner leads, and the like.

(6) The coefficient of linear thermal expansion is not more than 20 × 10 ⁶ / ° C.

This reduces warpage when an insulating material is joined to the inner lead 3A, and improves the workability of joining to the semiconductor chip in the next step.

(7) The glass transition temperature Tg of the thermoplastic resin is 220 ° C. or higher.

This is due to the high temperature (21
At 5 ° C.), a material having a glass transition temperature Tg of 220 ° C. is thermally deformed to easily cause package cracks, but the above conditions have an effect of preventing this.

An embodiment of a material satisfying at least two of the above seven conditions will be described.

For example, both surfaces of Kapton (polyimide film manufactured by DuPont) 500H or Upilex S (polyimide film manufactured by Ube Industries, Ltd.) are roughened, and both surfaces are coated with 25 μm of polyetherimide having a glass transition temperature Tg of 220 or more. The film described above is a material that satisfies the conditions except the item (1) in the above item.

Further, a bismaleimide film or an epoxy film or an epoxy modified polyimide film 12 having high-purity quartz fiber or aramid fiber as a reinforcing material is used.
Adhesive selected from an epoxy resin, a resole resin, an isomeramine resin, a phenol-modified epoxy resin, and an epoxy-modified polyimide resin on both sides of 5 μm is 10 to 25
(1) of the above items for films coated / dried with μm
It is a material that satisfies the item (6).

Also, Teflon PFA (4 manufactured by DuPont)
Fluoroethylene-perfluoroalkoxy copolymer), Teflon EFP (DuPont tetrafluoroethylene-perhexafluoropropylene copolymer), or Kapton F type (Toray DuPont Kapton film on both sides. FEP thinly coated material)
Both sides of the film, by improving the adhesiveness by a method such as plasma treatment, epoxy resin, resole resin, aromatic polyether amide resin, a film coated with an adhesive selected from a polyimide precursor, etc. on both sides, All of the items are satisfied, and the moisture absorption coefficient and the dielectric constant are particularly small.

Next, a method of adhering and fixing the semiconductor chip 1 to the lead frame 3 with the insulating film 4 interposed and using an adhesive will be described.

As shown in FIG. 11 (developed view showing the relationship between the lead frame 3, the insulating film 4, and the semiconductor chip 1), the signal inner leads 3 on the main surface of the semiconductor chip 1 are shown.
The insulating film 4 is divided and affixed with an adhesive 7 (FIGS. 1 and 6) on the positions facing A, the common inner lead 3A ₂ , and the suspension lead 3C, respectively. next,
As shown in FIG. 6, the signal inner leads 3A ₁ , common inner leads 3A ₂ , and suspension leads 3C of the lead frame 3 are bonded and fixed by an adhesive 7.

Examples of the mold resin material (resin) are shown below.

(1) A particle size distribution of 0.1 to 0.1 is added to the thermosetting resin.
A resin composition is used in which a substantially spherical inorganic filler having a particle size of 100 μm, an average particle size of 5 to 20 μm, and a maximum packing density of 0.8 or more is mixed in an amount of 70% by weight (wt%) or more.

In this case, the resin component may be any of epoxy, resole and polyimide.

As described above, the mold resin material using the spherical inorganic filler (for example, fused silica) is as shown in FIG.
As shown in FIG. 2 (a diagram showing the relationship between the packing density and the fluidity of the filler), the material has a small influence on the melt viscosity and the fluidity, so that the compounding amount can be increased to achieve low thermal expansion of the material. Further, FIG. 13 (a diagram showing the relationship between the filler content and the physical properties of the molded product) and FIG. 14 (a diagram showing the relationship between the filler content and thermal stress) are used to reduce the thermal stress of the molded product. be able to. Therefore, the package has good crack resistance.

In particular, when a semiconductor device having a delicate structure such as a LOC structure is molded, the device can be prevented from being deformed or damaged.

(2) A resin composition containing at least one of a high-purity phenol-curable epoxy resin, a resole-type phenol resin, and a bismaleimide resin as a main component is used.

As shown in Table 1 (on the last page), the characteristics of the cured product obtained by using the unpurified resole resin are large differences from the purified product in that the volume resistivity is 3 digits or more, especially at 140 ° C. different. Further, since there are many ionic impurities, there is a large difference in the electrical conductivity of the extract.

A method for producing a purified resole resin is, for example, 500 g of phenol and 30% formalin 55 in a flask.
0 g and 5 g of zinc acetate as a curing agent are added, and the mixture is gradually heated with stirring and heated at 90 ° C. for 60 minutes while refluxing. Then, the pressure in the flask was reduced to 20 mmHg to remove condensed water and powder reaction components.

Next, 300 g of acetone was added to the reaction product to dissolve the reaction product, and pure water was added to the reaction product to give 5
Stir vigorously at 00 ° C. for 30 minutes. After cooling, the tough aqueous layer was removed, the reaction product was again dissolved in 300 g of acetone, pure water was added, and the mixture was vigorously stirred at 50 ° C. for 30 minutes.
After cooling, the upper aqueous layer is removed. This washing operation is repeated 5 times. After each washing, a part of the reaction product is taken out and dried under reduced pressure at 40 ° C. for 48 hours to obtain 6 types of resol-type phenol resins having different degrees of purification.

The number of purification times, the melting point and the curing characteristics of the resol-type phenol resin thus obtained, and 50 g of pure water were added to 5 g of these resol-type phenol resins to obtain 120
The analysis results of hydrogen ion concentration (pH), electric conductivity and extracted ionic impurity concentration of the extracted water after heating at ℃ for 120 hours are summarized in Table 2 (on the last page).

As is clear from Table 2, the resole-type resin phenol resin obtained by repeating the washing operation 5 times has an extremely small amount of ionic impurities (Japanese Patent Application No. 63-
141750).

As described above, the effect of the refining is that the difference in the characteristics described above causes the reliability of the moisture resistance of the molded product and the Au / A ratio.
It is possible to improve the high temperature life of the l-junction and the device characteristics.

(3) A high-purity resol-type phenol resin or a bismaleimide resin as a main component,
Moreover, the molded product has a bending strength at 215 ° C. of 3 kgf / m.
m ² or more, for example, those of Examples 2 and 3 in Table 1 are used.

As described above, since the encapsulating material using the high-purity resol-type phenol resin or polyimide resin has a high heat resistance of the molded product and the bending strength at 215 ° C. is 3 kgf / mm ² or more, the package absorbs moisture. When used, the reflow resistance (package crack), the humidity resistance after reflow, and the thermal shock resistance are extremely good.

(4) Particle size distribution of 0.1 to 1 as the inorganic filler to be added to the base resin of the above (2) or (3).
00 μm, average particle size 5 to 20 μm, and maximum packing density of 0.
8 or more of substantially spherical fused silica,
For example, one of Examples 1, 2, and 3 in Table 1 is used.

As described above, since the sealing material using the spherical fused silica has little influence on the melt viscosity and fluidity of the material, the compounding amount can be increased to achieve low thermal expansion of the material. Therefore, the package has good crack resistance in addition to the effect of the item (2) or (3).

(5) The resin sealing material is an inorganic filler having a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20 μm.
m, the maximum packing density is 0.8 or more, and substantially spherical fused silica is used in an amount of 67.5% by volume (vol.
%) Or more, and the molded product has a linear expansion coefficient of 1.4 × 10
⁵ / ° C. or less, and one of Examples 1, 2, and 3 in Table 1 is used, for example.

By doing so, the effect of the spherical fused silica can be further enhanced.

(6) When the resin sealing material is mixed with 10 times the amount of ion-exchanged water and extracted at 120 ° C. for 100 hours, the pH of the extract is 3 to 7 and the electric conductivity is 200 μS /
cm or less, and those having an extraction amount of halogen ions, ammonia ions, and metal ions of 10 ppm or less, for example, any one of Examples 1, 2, and 3 in Table 1 is used.

Next, an experimental example of the resin encapsulating materials (1) to (6) will be described.

As shown in Table 1, an epoxy resin (conventional example), a resol type phenol resin (Example 1) and a bismaleimide resin (Example 2) were used as base resins as thermosetting resins. Particle size distribution 0.1
A substantially spherical fused silica having a particle size of 100 μm, an average particle size of 5 to 20 μm and a maximum packing density of 0.90, and various additives are further added, and the mixture is melt-heated for 10 minutes by a biaxial roll heated to about 80 ° C. Then, it was cooled and pulverized to prepare three types of resin sealing materials.

Then, using each resin sealing material, a semiconductor device having the LOC structure shown in FIG. 1, that is, 16 MDRAM was molded by a transfer molding machine. Mold temperature is 180 ℃, transfer pressure is 70kgf /
mm ² , and the molding time was 90 seconds.

According to the above experimental example, the following effects could be obtained.

(1) Particle size distribution of 0.1 to 1 as filler
The encapsulating material using substantially spherical fused silica having a diameter of 00 μm, an average particle size of 5 to 20 μm, and a maximum packing density of 0.8 or more is melted as compared with the case of using generally used prismatic fused silica. Since the viscosity is low and the fluidity of the material is good, there is no need to deform the bonding wire 5 such as Au or the lead frame 3 or to push the semiconductor chip 1 during molding, and also to fill the narrow gap of the package well. did.

(2) Since the spherical fused silica has little influence on the melt viscosity and fluidity of the material, the compounding amount can be increased to achieve low thermal expansion of the material. Therefore, the package had good crack resistance.

(3) An epoxy resin is used as a conventional semiconductor encapsulating material, and a phenol resin and a polyimide resin are poor in electrical characteristics and moisture resistance reliability because they contain many ionic impurities, and thus cannot be put to practical use. However, good reliability could be obtained by using a high-purity resol-type phenol resin or polyimide resin.

(4) The encapsulating material using a high-purity resol-type phenolic resin or polyimide resin has high heat resistance of the molded product, and since the mechanical strength at high temperature is particularly excellent, the encapsulating material is resistant to moisture absorption in the package. The reflow property (package crack), the moisture resistance reliability and the thermal shock resistance after the reflow were very good.

Next, a means for preventing the generation of voids, bending of the bonding wire, insufficient filling, etc. by injecting the resin sealing material into the mold will be described.

As shown in FIG. 1, a plurality of inner leads 3A are bonded on the main surface of the semiconductor chip 1 with an adhesive 7 with an insulating film 4 electrically insulating from the semiconductor chip 1 interposed therebetween. The inner leads 3A and the semiconductor chip 1 are electrically connected by the bonding wires 5,
In a 16 MDRAM sealed with resin, as shown in FIG.
A package structure in which the distance H ₁ from the portion of A bonded to the semiconductor chip 1 to the outer wall of the package ₂ is larger than the distance H ₂ from the surface opposite to the circuit forming surface of the semiconductor chip to the outer wall of the package. To

By adopting such a package structure, FIG. 16 (cross-sectional view modeling FIG. 15), FIG.
As shown in FIG. 16 (Harha cross-sectional view) and FIG. 18 (Nini cross-sectional view in FIG. 16), the depth h ₃₁ and h ₃₂ of the flow path above the inner lead 3A, the inner lead 3A and the semiconductor chip 1 are separated. relationship depth h ₁ of the bottom of the channel of depth h _2, and the semiconductor chip 1 of the intermediate portion is represented by each equation.

H ₁ = h ₂ = [h _c −t _c −2W _f t _f / W _c ]
÷ _{[2 (1 + W f / W} c) ] _{h 31 = h c -2h 1or2 -t} -t c h 32 = h 1or2 + t where, h _c: cavity depth t _c: Chip thickness t _f: lead frame Thickness W _c : Cavity width W _f : Lead frame length floating from the chip.

FIG. 19 is a graph showing the relationship between the above equations.

In this way, the resin flow path of the package 2 is divided into three, that is, the upper flow path of the inner lead 3A, the intermediate flow path of the inner lead 3A and the semiconductor chip 1, and the lower flow path of the semiconductor chip 1. By setting the depth of each flow channel and the resin flow channel structure so that the resin average flow velocity of the flow channels becomes equal, the resin average flow velocity of each flow channel shown in FIG. It is possible to prevent bending of the bonding wire (gold wire) 5, insufficient filling, and the like.

Further, since the resin flow velocities of the respective flow paths are the same, it is possible to prevent the semiconductor chip 1 and the inner leads 3A from being deformed, and it is possible to obtain a highly reliable package.

(Second Embodiment) As shown in FIGS. 20, 21A, 21B, 22A and 22B, a semiconductor integrated circuit device according to a second embodiment of the present invention is as follows. The insulating film 4 attached to the main surface of the semiconductor chip 1 of the embodiment I is provided on the entire surface of the chip closest surface of the signal inner lead 3A ₁ and the common inner lead 3A ₂ facing the semiconductor chip 1. Alternatively, the insulating film 4A is partially provided.

That is, for example, as shown in FIG. 20, the insulating film 4A faces the main surface of the semiconductor chip 1 of the signal inner lead 3A ₁ and the common inner lead 3A ₂ in the state of the lead frame 3. The insulating film 4A is previously provided on the entire surface of the surface closest to the semiconductor chip, and the insulating film 4A and the semiconductor chip 1 are bonded and fixed by an adhesive at the time of assembly.

In the lead frame 3 with the insulating film 4A, for example, the insulating film 4 is provided on the entire surface of the inner lead thin plate facing the main surface of the semiconductor chip 1 which is the closest to the semiconductor chip 1. After being attached and molded and cut by a press or the like, the signal inner lead 3A ₁ and the common inner lead 3A ₂ and the insulating film 4A are manufactured at once.

By doing so, the area of the insulating film 4A can be reduced. Further, the alignment of the signal inner lead 3A ₁ and the common inner lead 3A ₂ with the insulating film 4A can also be favorably performed. In addition, the signal inner lead 3A ₁ and the common lead 3
Since the insulating film 4 does not exist between A ₂ and A ₂ , leakage between them can be prevented.

The insulating film 4 can be divided into a plurality of sheets, for example, divided into four and attached, and the effect of heat stress can be reduced as compared with the case of one insulating film 4. .

Further, as shown in FIG. 21A, the signal inner lead 3A ₁ and the common lead among the entire surface (rear surface) closest to the semiconductor chip 1 of the surface facing the main surface of the semiconductor chip 1 are shared. The insulating film 4B is provided only on the portion corresponding to the bonding portion of 3A ₂ , and the semiconductor chip 1
It is possible to minimize the area occupied by the insulating film 4B.

The lead frame 3 with the insulating film 4B in which the area occupied by the insulating film 4B with respect to the semiconductor chip 1 is minimum is shared with the signal inner lead 3A ₁ as shown in FIG. 21B, for example. Lead 3A ₂
Semiconductor chip 1 on the surface opposite to the main surface of semiconductor chip 1
A hole a is provided at a predetermined position on the entire surface closest to
A sheet of insulating film 4 is attached, and the sheet is molded and cut with a press or the like, and the insulating film 4 is provided only at a position corresponding to the bonding portion of the signal inner lead 3A ₁ and the common lead 3A _2.
The one to which B is attached is produced.

By doing so, the amount of the insulating film can be further reduced as compared with the embodiment shown in FIG. 20, so that the moisture absorption amount can be further reduced. Further, with this structure, the semiconductor chip 1 can be easily fixed by combining the suspension leads.

In the embodiment shown in FIG. 21A, the insulating film 4A is provided only in the portion corresponding to the bonding portion, but the other portions are partially insulated as necessary. The film 4A may be provided.

Further, as shown in A of FIG. 22, an extension portion is formed so as to extend and intersect the portion of the common inner lead 3A ₂ and the signal inner lead 3A _{1 with} the portion of the insulating film 4A shown in FIG. Also, the insulating film 4C is provided.

The inner lead 3A with the insulating film 4C has a hole b in which only the portion corresponding to the signal inner lead 3A ₁ remains, as shown in FIG. 22B, for example.
A single insulating film 4 provided with is prepared, and the insulating film 4 is divided into two by cutting along the center line in the long side direction. The insulating film 4C divided into two parts is attached to the common inner lead 3A ₂ and the signal inner lead 3A ₁ to manufacture.

In this way, the insulating film 4 may be previously cut into a predetermined pattern to form the insulating film 4C, and the insulating film 4C may be attached to the common inner lead 3A ₂ and the signal inner lead 3A _1. Therefore, the method for producing the insulating film 4C is easy. Also, by doing so, since the paste insulating film 4C inner leads 3A ₁ for shared inner leads 3A ₂ and the signal, it is possible to flatten the tips of signal inner leads 3A _1, subsequent steps Work becomes easier.

The insulating film 4C, the common inner lead 3A ₂ and the signal inner lead 3A ₁ are adhered to each other by thermocompression bonding when a thermoplastic adhesive is used, and when a thermosetting adhesive is used. It is joined by hardening after temporary fixing.

Note that FIGS. 20 and 21A and FIG. 22A
The insulating films 4A, 4B, and 4C shown in (4) may be slightly wider than the width of the inner lead, or conversely may be narrower.

As can be seen from the above description, according to the second embodiment, the amount of the insulating film 4 arranged between the semiconductor chip 1, the signal inner lead 3A ₁ and the common lead 3A ₂ is small. Since it is extremely less than the conventional one,
The amount of water absorbed in the semiconductor device can be reduced even if the device is kept in a high humidity environment for a long time.

As a result, the water vapor pressure in the semiconductor device during the solder reflow process can be reduced, so that a semiconductor device that does not cause resin cracks can be provided.

(Third Embodiment) As shown in FIG. 23, a semiconductor integrated circuit device according to a third embodiment of the present invention has a bonding pad provided on the main surface of semiconductor chip 1 of the first embodiment. The main surface area of the semiconductor chip 1 other than BP is covered with the α-ray shielding polyimide film 8, and at least the signal inner lead 3A is provided on the main surface of the semiconductor chip 1.
Insulating film 4D is attached to the position where ₁ and the common inner lead 3A ₂ (not shown in FIG. 23) are bonded.
Are formed.

The thickness of the α-ray shielding polyimide film 8 is
It is 2.0 μm to 10.0 μm.

The thickness of the insulating film 4D is 75 μm.
m or more. As the insulating film 4D, a thermosetting resin containing a printable inorganic filler is suitable.

The area occupied by the insulating film 4D is at least ½ or less of the area of the semiconductor chip 1.

A polyimide film 9 is formed on the surface opposite to the main surface of the semiconductor chip 1.

Next, the entire main surface area of the semiconductor chip 1 other than the bonding pad BP provided on the main surface of the semiconductor chip 1 is covered with the α-ray shielding polyimide film 8, and the main surface of the semiconductor chip 1 is covered. One embodiment of the method of forming the insulating film 4D on the upper part where at least the tips of the signal inner lead 3A ₁ and the shared inner lead 3A ₂ are bonded is shown in FIG. 23 and FIG. This will be described with reference to sectional views of the steps).

First, the α-ray shielding polyimide film 8 is applied to the entire area of the silicon wafer 10 shown in FIG. 25 (plan view of the main surface of the silicon wafer), half-cured, and photo-etched to bond pads (external terminals). The BP is exposed (step 101 in FIG. 24A).

Next, the solvent-peelable dry film A is attached. (Step 102). A predetermined pattern is exposed on the solvent-peeling dry film A (step 10).
3) Then, a hole is formed by developing (step 104).

Next, a paste-like insulator (printing paste) C is applied, embedding with a squeegee (embedding with a printing squeegee), and curing (step 105,
106, 107).

Next, the solvent peelable dry film A is peeled off to form an insulating film 4D. Then, dicing is performed along the solid line on the silicon wafer 10 shown in FIG. 25 to complete the semiconductor chip with the insulating film 4D.

Another embodiment of the method for forming the α-ray shielding polyimide film 8 and the insulating film 4D is shown in FIG.
4B (manufacturing flow chart and sectional views of chips in each step), the α-ray shielding polyimide film 8 is applied to the entire region of the silicon wafer 10 and photo-etched to bond pads (external terminals). ) Exposing the BP (step 201 in FIG. 24B).

Next, the dry film D for solder resist
(Step 202). A predetermined pattern is exposed on the dry film D for the solder resist (step 203), and developed to develop the insulating film 4D (step 2).
04) is formed. Then, dicing is performed along the solid line on the silicon wafer 10 shown in FIG. 25 to complete the semiconductor chip with the insulating film 4D.

Even if the thick insulating film 4D is formed by a silicon wafer process, the silicon wafer 10 does not warp because it is partially formed.

26 to 28 show the insulating property formed on the main surface of the semiconductor chip 1 at least where the tips of the signal inner leads 3A ₁ and the common inner leads 3A ₂ and the suspension leads are bonded. 3 shows various pattern shapes of the film 4D.

As can be seen from the above description, according to the third embodiment, the α-ray shielding polyimide film 8 is coated on the entire main surface area of the semiconductor chip 1 except the bonding pads (external terminals) BP, Since the insulating film 4D is formed on the main surface of the chip 1 at least where the tips of the signal inner leads 3A ₁ and the common inner leads 3A ₂ are bonded, the α-ray shielding polyimide film 8 is used for the circuit. It is possible to block α rays to the entire formation area, and the semiconductor film 1 can be bonded and fixed by the insulating film 4D.

Further, since the insulating film 4D is formed on the main surface of the semiconductor chip 1 at least at the positions where the tips of the inner leads 3A and the suspension leads 3C are bonded, the semiconductor chip 1 and the inner leads 3A are not separated from each other. The stray capacitance between them can be reduced.

Also, since the insulating film 4D is a thermosetting resin containing a printable inorganic filler,
High precision insulating film 4D in wafer process
Can be formed.

Further, by forming the polyimide film 9 on the surface opposite to the main surface of the semiconductor chip 1, the adhesion between the semiconductor chip 1 and the resin is good, so that the package crack can be prevented.

In addition, the insulating film 4D has at least the solvent-peeled dry film A attached to the silicon wafer 10 and, after the usual exposure and development steps, a paste-like insulator (printing paste) is applied to the squeegee. Since the insulating film 4D is formed with high precision in a batch process by a wafer process including embedding, heating and curing, and peeling the solvent-peeling dry film, the productivity can be improved.

Further, since the insulating film 4D is formed only by exposing and developing the dry film D for solder resist, the productivity can be further improved.

(Fourth Embodiment) As shown in FIG. 29 (partially sectional perspective view), a resin-sealed conductor device according to a fourth embodiment of the present invention has the same structure as the semiconductor chip 1 of the first embodiment. On the surface, a plurality of signal inner leads 3A ₁ and a common inner lead 3A ₂ are adhered with an adhesive with an insulating film 4 electrically insulating from the semiconductor chip 1 interposed therebetween. The bonding wire 5 is formed between the lead 3A ₁ and the shared inner lead 3A ₂ and the semiconductor chip 1.
In a semiconductor device which is electrically connected with the mold resin 2A and is sealed with the mold resin 2A, as shown in FIG. 30 (a sectional view showing a state before resin molding taken along the line HO of FIG. 29), A part of the main surface of 1 is covered with a substance 20 that is more flexible or fluid than the molding resin, and the substance 2
0 so that it covers the entire bonding wire 5,
The outside of the substance 20 is sealed with a resin 2A.

That is, a dam 21 is provided so as to cover the entire bonding wire 5 straddling the shared inner lead 3A ₂ with the flexible / fluid substance 20, and the dam 21 is made of a flexible material such as silicone gel. The volatile / fluid substance 20 is dropped from above the bonding wire 5,
After curing, resin molding is performed by transfer molding.

For the dam 21, for example, a silicone rubber containing a silica filler having a high viscosity is used.

Further, the flexible / fluid substance 20 does not necessarily have to be the gel substance as described above, and has such flexibility or fluidity that the bonding wire 5 can be deformed therein. If so, various materials such as silicone grease and silicone rubber may be used.

By doing so, the bonding wire 5 can freely follow the deformation even when the main surface of the semiconductor chip 1 peels off and the steam expands during reflow soldering of a package that has absorbed moisture. The breaking of the bonding wire 5 can be prevented.

Further, since the deformation of the bonding wire 5 is restrained during the transfer molding of the molding resin 2A, even if the wire 5 becomes long to straddle the shared inner lead 3A ₂ , the deformation of the bonding wire 5 at the time of molding. It is possible to prevent short-circuiting between the bonding wires 5 or contact between the bonding wire 5 and the common inner lead 3A ₂ due to this.

For the purpose of only preventing the deformation of the bonding wire 5, the material covering the bonding wire 5 need not be a material having flexibility and fluidity. If there is a resin that can be potted on the bonding wire 5 portion on the main surface of the semiconductor chip 1, an epoxy resin or the like having the same elastic modulus as the transfer-molded resin 2A on the outside thereof may be used.

When the flexible / fluid substance 20 has fluidity, its viscosity needs to be higher than the melt viscosity of the resin 2A during transfer molding.

Since the resin 2A is not in direct contact with the bonding wire 5 due to the flexible / fluid substance 20,
The bonding wire 5 is repeatedly deformed by the relative thermal deformation between the semiconductor chip 1 and the mold resin 2A during the temperature cycle, and is not broken due to fatigue.

Further, when the flexible / fluid substance 20 is used, a gap is not generated on the surface of the bonding pad BP due to thermal stress, and therefore aluminum of the bonding pad portion is not corroded by moisture. .

FIG. 31 is a sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment in which the flexible / fluid substance 20 is used.

As shown in FIG. 31, the interface between the signal inner lead 3A ₁ and the resin 2A is less likely to have a gap than the main surface of the semiconductor chip 1. Therefore, the signal inner lead 3A of the bonding wire 5 is formed. The bonding part on the ₁ side is less likely to be broken. Therefore, in this embodiment, disconnection is unlikely to occur. Therefore, in this embodiment, the flexible / fluid substance 20 is provided only in the vicinity of the bonding portion (first bonding) on the side of the semiconductor chip 1 where breakage is likely to occur. As a result, the bonding wire 5
If it can be freely deformed, a certain degree of disconnection prevention effect can be obtained.

In this embodiment, the common inner lead 3A ₂ is used instead of the dam 21 shown in FIG.

However, in the case of this embodiment, since the entire bonding wire 5 is not covered with the flexible / fluid substance 20, when the package is subjected to the temperature cycle, the semiconductor chip 1 and the mold resin 2A are not covered with each other. Since the bonding wire 5 is repeatedly deformed by the relative thermal deformation between the two, the wire breakage due to fatigue is more likely to occur as compared with the embodiment of FIG.

There is also a certain degree of prevention effect on the deformation of the bonding wire 5 during transfer molding of the resin 2A.

Further, since the amount of the flexible / fluid substance 20 is reduced and the height can be lowered, it is effective not only for preventing disconnection during reflow soldering and wire deformation during transfer molding, but also for the entire package. Can be thinned and the packaging density can be improved.

FIG. 32 is a sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment in which the flexible / fluid substance 20 is used.

In this embodiment, as shown in FIG.
The entire main surface of the semiconductor chip 1 is covered with the flexible / fluid substance 20 so that the entire bonding wire 5 is covered.

The same effects as those of the embodiment of FIG. 30 can be obtained, and since the entire main surface of the semiconductor chip 1 is covered with the flexible / fluid material 20, the moisture resistance can be further improved. it can.

However, since the surface area of the flexible / fluid substance 20 is large, a gap is generated at the interface with the mold resin 2A during reflow soldering, and when vapor pressure acts, cracks occur in the upper mold resin 2A. It tends to occur.

FIG. 33 is a sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment in which the flexible / fluid substance 20 is used.

In this embodiment, as shown in FIG.
Only the entire bonding wire 5 provided on the main surface of the semiconductor chip 1 is covered with the substance 20 which is more flexible or fluid than the molding resin 2A.

The flexible / fluid substance 20 covering the bonding wire 5 does not need to have a raised shape on the main surface of the semiconductor chip 1, and may adhere only to the surface of the bonding wire 5. Good.

In order to perform such coating, first, the flexible / fluid substance 20 diluted with a solvent to have a low viscosity is dropped onto the semiconductor chip 1 and attached to the bonding wire 5, and then the solvent is added. Are evaporated to form.

In this case, the thicker the layer of the flexible / fluid substance 20 on the surface of the bonding wire 5, the greater the effect of preventing disconnection and deformation of the bonding wire 5.

By configuring in this way, FIG.
Since it is possible to reduce the amount of the flexible / fluid substance 20 for obtaining the same effect as that of the embodiment shown in FIG.
The generation of package cracks can be prevented by the vapor pressure generated between the flexible / fluid substance 20 and the mold resin 2A.

FIG. 34 is a sectional view showing the state before resin molding of the resin-sealed semiconductor device of another embodiment in which the flexible / fluid substance 20 is used.

In this embodiment, as shown in FIG.
The bonding wire 5 is covered with the flexible / fluid substance 20, and a hole 22 is made in the mold resin 2A on the surface opposite to the main surface of the semiconductor chip 1 to substantially expose a part of the semiconductor chip 1.

Here, the term "substantially" means the extent to which the thin film of the mold resin 2A on the surface opposite to the main surface of the semiconductor chip 1 or the vapor pressure generated inside the package 2 is easily broken during the manufacturing process. It is assumed that there is a thin resin layer.

As described above, since the flexible / fluid substance 20 can secure the moisture resistance of the bonding pad BP portion without causing the disconnection of the bonding wire 5 during the reflow soldering and the temperature cycle, the mold resin 2A can be secured.
Even if the hole 22 is formed in a part of, the moisture resistance does not decrease.

Further, since the vapor generated inside the package during the reflow soldering is diffused to the outside through the hole 22, the pressure does not rise and the resin crack does not occur.

The mold resin 2A exists on the surface of the hole 22 opposite to the main surface of the semiconductor chip 1 as long as the mold resin 2A can be easily penetrated by vapor pressure even if it is not completely exposed. It may be.

As can be seen from the above description, according to Embodiment IV, even if the main surface of the semiconductor chip 1 peels off and vapor expands during reflow soldering, the breaking of the bonding wire 5 is prevented. be able to.

Also, during transfer molding, short-circuit between wires due to deformation of the bonding wire 5, or inner wire 3A ₂ shared with the bonding wire 5 is formed.
It is possible to prevent contact with.

Further, it is possible to prevent resin cracks during reflow soldering without causing moisture resistance failure of the bonding pad BP portion and breaking of the bonding wire 5 during temperature cycling.

(Fifth Embodiment) As shown in FIG. 35 (cross-sectional view), a resin-sealed semiconductor device according to a fifth embodiment of the present invention is the same as the resin-sealed semiconductor device according to the first embodiment. A recess is provided on the surface opposite to the main surface of the semiconductor chip 1.

Due to this recess 101, the mold resin 2A
Can be restrained to the semiconductor chip 1 to reduce the stress generated in the mold resin portion of the corner portion of the surface opposite to the main surface of the semiconductor chip 1 where the reflow crack occurs, and prevent the reflow crack.

Further, the recess 101 may be processed by etching. Also, other methods may be used.

36A (plan view viewed from the side opposite to the main surface of FIG. 3) and FIG. 36B (cross-sectional view taken along the horizontal center line of A of FIG. 36) are the main parts of the semiconductor chip 1. It is a figure which shows the modification of the recessed part 101 provided in the surface opposite to the surface, and this example shows the annular recessed part 101 in the surface opposite to the main surface of the semiconductor chip 1.
a is provided.

37A (plan view) and 37B (cross-sectional view) are views showing another modification of the recess 101 provided on the surface opposite to the main surface of the semiconductor chip 1. An example is a rectangular recess 10 on the surface opposite to the main surface of the semiconductor chip 1.
1b is provided.

38A (plan view) and FIG. 38B (side view) are views showing a modified example of the convex portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1, and this example is shown. Is provided with a circular convex portion 101c on the surface opposite to the main surface of the semiconductor chip 1.

39A (plan view) and FIG. 39B (side view) are views showing another modified example of the convex portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1, In this example, a rectangular convex portion 10 is provided on the surface opposite to the main surface of the semiconductor chip 1.
1d is provided.

FIG. 40A (plan view) and FIG. 40B (side view) are views showing another modified example of the concave portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1. An example is an elliptical recess 10 on the surface opposite to the main surface of the semiconductor chip 1.
1e is provided.

41A (plan view) and FIG. 41B (side view) are views showing a modification of the concave portion or the convex portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1, In this example, recesses and protrusions 101f are provided by forming a plurality of grooves on the surface opposite to the main surface of the semiconductor chip 1. This may be provided with grooves in a grid pattern.

As described above, the semiconductor chip 1 is more firmly restrained by the mold resin 2A by providing, for example, any one of the concave portions or the convex portions 101a to 101f on the surface opposite to the main surface of the semiconductor chip 1. be able to.

Further, the stress generated in the mold resin 2A by the corner portion of the surface opposite to the main surface of the semiconductor chip 1 can be reduced.

FIG. 42 is a diagram showing another embodiment of the present invention related to the fifth embodiment. The fifth embodiment is the same as the fifth embodiment.
In the state where the silicon oxide film 102 is left on the surface opposite to the main surface of the semiconductor chip 1, for example, the concave portion or the convex portion 101 is provided on the surface opposite to the main surface of the semiconductor chip 1.

As described above, since the silicon oxide film 102 is left on the surface opposite to the main surface of the semiconductor chip 1,
Since the adhesive force between the silicon oxide film 102 and the mold resin 2A is strong, it is possible to prevent the mold resin 2A from peeling off from the surface opposite to the main surface of the semiconductor chip 1.

Further, the semiconductor chip 1 can be firmly restrained by the mold resin 2A by the concave portion or the convex portion 101.

(Embodiment 6) A resin-encapsulated semiconductor device according to Embodiment 6 of the present invention is a cross-sectional view taken along the line H-H in FIG. 43 (partially sectional perspective view) and FIG. 44. ), On the main surface of the semiconductor chip 1 of the first embodiment,
A plurality of signal inner leads 3A ₁ and common inner leads 3A _2, the bonded semiconductor chip 1 and electrically insulating insulating film 4 interposed an adhesive, inner leads 3A ₁ and the shared inner for the signal In the semiconductor device in which the lead 3A ₂ and the semiconductor chip 1 are electrically connected by the bonding wire 5 and sealed by the mold resin 2A, the semiconductor chip 1 is electrically connected to the central portion of the longitudinal side surface of the package 2. Heat dissipation lead 30 insulated from
1a is provided, one end of which extends to the upper part of the heat generating portion of the main surface of the semiconductor chip 1, and the other end of the heat dissipation lead 301a extends to the outer lower part of the surface of the package 2 opposite to the main surface of the semiconductor chip 1. It has been extended.

Thus, one end of the heat dissipation lead 301a electrically insulated from the semiconductor chip 1 is provided at the center of the side surface in the longitudinal direction of the package so as to extend to the upper portion of the heat generating portion of the main surface of the semiconductor chip 1. The heat dissipation lead 30
By extending the other end of 1a to the outer lower part of the surface of the package 2 opposite to the main surface of the semiconductor chip 1,
The heat dissipation efficiency of the heat of the heat generating portion of the semiconductor chip 1 can be improved.

45 (partially sectional perspective view) and FIG. 46 (sectional view taken along the toe line in FIG. 45) are views showing a modified example of the heat dissipation lead 301a shown in FIG. One end of the heat dissipation lead 301b is extended to the upper part of the heat generating portion of the main surface of the semiconductor chip 1, and the heat dissipation lead 30b
The other end of 1b is extended to the upper outside of the main surface of the semiconductor chip 1 of the package 2.

The extension of the heat dissipation lead 301b is a heat dissipation plate.

Thus, one end of the heat dissipation lead 301b electrically insulated from the semiconductor chip 1 is provided at the center of the side surface in the longitudinal direction of the package so as to extend to the upper portion of the heat generating portion of the main surface of the semiconductor chip 1. The heat dissipation lead 30
Since the other end of 1b is extended to the upper outside of the main surface of the semiconductor chip 1 of the package 2, the semiconductor chip 1
The heat radiation efficiency of the heat of the heat generating portion can be improved.

The portion where the other end of the heat dissipation lead 301b extends to the outer upper part of the main surface of the semiconductor chip 1 of the package 2 is bent as shown by the dotted line in FIG. 46 to reduce the occupied volume. You may

Also, the heat dissipation leads 301a and 30a
The lead frame 1b is made of the same lead frame as the signal lead frame.

(Embodiment 7) A resin-encapsulated semiconductor device according to Embodiment 7 of the present invention is shown in FIG. 49 (partially sectional perspective view) and FIG. 50 (sectional view taken along the line Lily in FIG. 49). ), A plurality of signal inner leads 3A ₁ and a plurality of common inner leads 3A ₂ are electrically insulated from the semiconductor chip 1 on the main surface of the semiconductor chip 1 of the first embodiment shown in FIG. Which is adhered with an adhesive with an insulating film 4 interposed therebetween, the signal inner lead 3A ₁ , the common inner lead 3A ₂ and the semiconductor chip 1 are electrically connected by a bonding wire 5, and a resin-sealed semiconductor In the device, on the main surface of the semiconductor chip 1, the bonding wire 5 and the inner lead 3A shared on the main surface are shared.
_The bonding pad BP is provided so as not to intersect with ₂ .

The element layout and the bonding pad BP of the semiconductor chip 1 of the seventh embodiment are shown in FIG.
(Layout plan view).

That is, the memory cell array (MA) is arranged over substantially the entire surface of the DRAM 1. The DRAM 1 of the seventh embodiment is not limited to this, but the memory cell array is largely composed of eight memory cell arrays 11A to 11H.
Is divided into In FIG. 47, 4 is provided above the DRAM1.
Memory cell arrays 11A, 11B, 11C and 11
D is arranged, and four memory cell arrays 11E,
11F, 11G, and 11H are arranged. Each of the eight divided memory cell arrays 11A to 11H is further subdivided into 16 memory cell arrays (MA) 11. That is, the DRAM 1 has 128 memory cell arrays 11E arranged therein. One memory cell array 11 subdivided into 128 pieces has a capacity of 128 [Kbit].

A sense amplifier circuit (SA) 13 is arranged between each of the two memory cell arrays 11 of the 128 subdivided DRAMs 1. The sense amplifier circuit 13 is composed of a complementary MOSFET (CMOS). A column address decoder circuit (YDEC) 12 is provided at one end on the lower side of each of the memory cell arrays 11A, 11B, 11C and 11D of the eight divided DRAM1.
Is arranged. Similarly, the memory cell array 11E,
A column address decoder circuit (YDEC) 12 is arranged at one upper end of each of 11F, 11G, and 11H.

The memory cell arrays 11A and 11B, the memory cell arrays 11C and 11D, and the memory cell arrays 11E and 11 of the eight divided DRAMs 1 are divided.
A peripheral circuit 17 and an external terminal BP are arranged between F and between the memory cell arrays 11G and 11H, respectively. In addition, the memory cell arrays 11A, 11B, 11C and 11
The lower side of each D and the memory cell arrays 11E, 11F,
The peripheral circuit 17 is provided in the upper region of each of 11G and 11H.
And a peripheral circuit 18 are provided. As the peripheral circuit 17, a main amplifier circuit, an output buffer circuit, a substrate potential generation circuit (Vss generator circuit), and a power supply circuit are arranged.

As the peripheral circuit 18, a row address strobe (RE) system circuit, a write enable (W) system circuit, a data input buffer circuit, a Vcc limiter circuit, an X
Address driver circuit (logical stage), X system redundancy circuit, X address buffer circuit, column address strobe (CE)
System circuit, test circuit, limiter circuit for VDL, Y address driver circuit (logical stage), Y system redundant circuit, Y address buffer circuit, Y address driver circuit (drive stage), X
An address driver circuit (drive stage) and a mat selection signal circuit (drive stage) are arranged (see FIG. 4 and its description).

The external terminal BP is the resin-sealed type fc.
2 has a LOC structure, and the inner lead 3A is extended to the central part of the DRAM 1, so that it is arranged in the central part of the DRAM 1 and on the main surface of the semiconductor chip 1.
The bonding wire 5 wired on the main surface and the common inner lead 3A ₂ are arranged so as not to intersect with each other.

The external terminal BP is connected to the memory cell array 11
A, 11B, 11C, 11D, 11E, 11F, 11G
, And 11H are arranged from the upper end side to the lower end side of the DRAM 1 in the area defined by each. External terminal B
The signal applied to P is the resin-sealed type f shown in FIG.
Since it was explained in c2, the explanation here is omitted.

Basically, since the inner leads 3A to which the reference voltage (Vss) and the power supply voltage (Vcc) are applied extend from the upper end side to the lower end side on the surface of the DRAM 1,
DRAM1 is for the reference voltage (Vss) along the extending direction,
A plurality of external terminals BP for power supply voltage (Vcc) are arranged. That is, the DRAM 1 has a reference voltage (Vss)
It is configured so that the respective power supplies of (Vcc) can be sufficiently supplied.

As described above, according to the seventh embodiment,
On the main surface of the semiconductor chip 1, a bonding pad BP which does not intersect the bonding wire 5 wired on the main surface and the common inner lead 3A ₂ is arranged. Bonding wire 5 for connecting 3A ₁ and semiconductor chip 1
Therefore, it is possible to prevent the common inner lead 3A ₂ from being short-circuited.

Next, the details of the lead frame will be described.

As shown in FIG. 52 (a plan view of the entire lead frame), the lead frame 3 of the seventh embodiment has 20
A signal inner lead 3A ₁ and two shared inner leads 3A ₂ are provided. The inner lead 3
A ₁ is an insulating film (insulator) 4 of the signal inner lead 3A ₁ as shown in FIG.
The distance between the semiconductor chip 1 and the portion on the outer lead 3B side of the portion bonded to the insulating film (insulator) is
The stepped structure is wider than the space between the semiconductor chip 1 and the portion to be joined with the semiconductor chip 1. By thus forming the inner lead 3A with the step structure, the semiconductor chip 1
Since the stray capacitance between the signal and the signal inner lead 3A ₁ is smaller than that of the conventional one, it is possible to improve the signal transmission speed and reduce the electrical noise.

In the seventh embodiment, the arrangement of the bonding pads BP on the main surface of the semiconductor chip 1 and the components other than the lead frame are the same as those in the first embodiment.

Of course, the techniques of the second to sixth embodiments can be applied to the seventh embodiment.

(Embodiment 8) A resin-encapsulated semiconductor device according to an eighth embodiment of the present invention is as shown in FIG.
This is a modification of the lead frame of the first embodiment, in which the inner lead 3C ₁ (suspension lead) that is not energized to fix the side surface opposite to the main surface of the semiconductor chip 1 is bent.

As shown in FIG. 54A (cross-sectional view of semiconductor chip fixing portion) and FIG. 56 (cross-sectional view of signal inner lead portion and common inner lead portion before resin molding), a plurality of signals Inner lead 3
A ₁ shared inner leads 3A ₂ is disposed in a state of being floated from the main surface of the semiconductor chip 1 (FIG. 56) described above, wherein the semiconductor chip 1 in the lead 3C ₁ suspension is bonded and fixed by an adhesive 7 .

The adhesive 7 is an epoxy resin,
It may be any of the above-mentioned adhesives such as a resole resin.

In addition, an insulating film 4 may be interposed between the suspension lead 3C ₁ and the semiconductor chip 1 for adhesion.

In this case, when each of the plurality of signal inner leads 3A ₁ and the common inner lead 3A ₂ is connected to the bonding pad BP of the semiconductor chip 1 by the bonding wire 5, the signal inner lead 3A ₁ and the common inner lead 3A _{1 are} commonly used. The inner lead 3A ₂ is pressed and fixed to the semiconductor chip 1 from above by a jig, and wire bonding is performed. When this wire bonding is completed and the holding jig is removed, the signal inner lead 3A ₁ and the common inner lead 3A ₂ are in the state shown in FIG. 56 due to the springback effect of the suspension lead 3C ₁ .

As shown in FIG. 54B, for example,
The insulating film 4 having a predetermined thickness is interposed between the suspension lead 3C of the lead frame 3 applied to the above-described first embodiment and the main surface of the semiconductor chip 1 and adhesively fixed by the adhesive 7. The signal inner lead 3A ₁ and the shared inner lead 3A ₂ may be arranged in a state of floating from the main surface of the semiconductor chip 1 (FIG. 56). In this case, the thickness of the insulating film 4 is generally about 150 μm, but it is possible to make it more than this.

Further, as shown in FIG. 55 (a sectional view showing a state before resin molding), for example, between the signal inner lead 3A ₁ , common inner lead 3A ₂ and the main surface of the semiconductor chip 1. The insulating plate 40 may be inserted, the signal inner lead 3A ₁ , the common inner lead 3A ₂ and the semiconductor chip 1 may be electrically connected by the bonding wire 5 and sealed with a mold resin.

Further, as shown in FIG. 57 (a sectional view showing a state before resin molding), the insulating plate 40 has _one of the left and right sides of the signal inner lead 3A ₁ and the common inner lead 3A ₂ , for example, the left side. Signal inner lead 3
A ₁ and common inner lead 3 Inserted only between A ₂ and the main surface of the semiconductor chip 1, the inner lead 3 for signals on the right side
A ₁ and the shared inner lead 3A ₂ are electrically connected by a bonding wire 5 to the signal inner lead 3A ₁ , the shared inner lead 3A ₂ and the semiconductor chip 1 while being floated from the main surface of the semiconductor chip 1, and molded. It may be sealed with a resin.

Further, for example, in order to arrange the plurality of signal inner leads 3A ₁ and the common inner leads 3A _{2 in} a state of being floated from the main surface of the semiconductor chip 1 (FIG. 56), FIG. As shown in C, the suspension lead 3C ₁ may be deeply bent to form the suspension lead 3C ₂ , and the suspension lead 3C ₂ may bond and fix the side surface opposite to the main surface of the semiconductor chip 1. By doing so, the suspension leads 3C ₂ are used to dispose the signal inner leads 3A ₁ and the shared inner leads 3A _{2 in} a state of being floated from the main surface of the semiconductor chip 1. Since the side opposite to the surface is adhesively fixed,
The step of adhering the insulating film 4 becomes unnecessary. Also,
The semiconductor chip 1 is firmly fixed. Moreover, since the lead wire is not adhered onto the memory cell, damage to the memory cell can be reduced.

As described above, according to the eighth embodiment,
By not using or minimizing the insulating film 4, moisture absorption can be reduced, so that the solder reflow resistance can be advantageous.

In the eighth embodiment, it is preferable that the α-ray shielding polyimide film is applied over the entire main surface area of the semiconductor chip 1 other than the bonding pads.

(Ninth Embodiment) As shown in FIGS. 58 and 59 (layout diagram on a semiconductor chip), a resin-sealed semiconductor device according to a ninth embodiment of the present invention is bonded to inner leads. Pad BP (solder bump 5
Two semiconductor chips 1A and 1B in which C) is formed in mirror symmetry are provided.

In FIG. 58, the CAS0 terminal (bonding pad BP) and the CAS1 terminal (bonding pad BP) are separated and the other terminals (bonding pad B) are separated.
P) is common. With such a layout, the capacity in the word direction is doubled.

In FIG. 59, the Do terminal and the Di terminal are separated and the other terminals are common. With such a layout, the capacity in the bit direction is doubled.

Then, as shown in FIG. 60 (cross-sectional view for explaining the package), these two semiconductor chips 1A and 1B are
The inner lead 3A and the bonding pad BP of the semiconductor chip 1 with the inner lead 3A sandwiched between their respective main surfaces.
And are electrically connected by the solder bumps 5C and sealed with a mold resin.

As described above, the two semiconductor chips 1A and 1B having the mirror-symmetrical bonding pad BP with the inner lead 3A sandwich the inner lead 3A on the main surface side of each of the inner leads 3A and the semiconductor chip. Since the first bonding pad BP is electrically connected by the solder bump 5C and is sealed with the mold resin, it is possible to mount an element having double the capacitance without changing the outer shape of the package 2.

(Embodiment 10) Embodiment 1 of the present invention
The resin-sealed semiconductor device of No. 0 is shown in FIG.
Of the semiconductor device of the first embodiment, as shown in FIG. 62 (a cross-sectional view taken along the rule line in FIG. 61) of the resin-encapsulated semiconductor device viewed from the side facing the wiring substrate). On the surface of the package 2 facing the substrate, a heat dissipation groove 50 that is open to the outside is provided. In this case, the distance between the bottom surface 50A of the heat dissipation groove 50 and the semiconductor chip 1, that is, the thickness dimension of the molding resin 2A below the semiconductor chip 1 is 0.3 mm or less.

By thus providing the heat dissipation groove 50, as shown in FIGS. 68 and 69 (cross-sectional view showing a state in which the resin-sealed semiconductor device of the tenth embodiment is mounted on a wiring board), The gap 51D between the substrate 51A or 51B and the bottom surface 50A of the heat dissipation groove 50 becomes large, and if air is blown in the direction perpendicular to the paper surface for cooling, air also flows into this gap 51D, so that from the bottom surface 50A of the heat dissipation groove 50. Also, heat is dissipated and the thermal resistance of the semiconductor device is reduced.

In the structure of the present embodiment, the thickness of the molding resin 2A under the semiconductor chip 1 becomes thin and some ingenuity is required at the time of resin molding, but the molding resin 2A having a low melt viscosity at the time of molding is used. For example, as shown in Figure 61,
The package 2 can be formed.

Next, FIG. 63 (cross-sectional view) shows a modification of the resin-sealed semiconductor device of the tenth embodiment.

As shown in FIG. 63, the semiconductor device of this modification is provided with an opening for heat dissipation 53 on the upper surface of the package 2 shown in FIG. Heat dissipation groove 50
The distance between the bottom surface 50A of the semiconductor chip 1 and the bottom surface 53A of the heat dissipation groove 53 and the semiconductor chip 1, that is, the thickness of the molding resin on the lower part of the semiconductor chip 1 is 0.3 mm.
It is as follows.

As described above, the semiconductor chip 1 of the package 2 is
By thinning the mold resin 2A on the upper part of the above, the heat transfer surface is increased and the thermal resistance of the semiconductor device is reduced, so that the overall thermal resistance can be reduced accordingly. Further, as shown in FIG. 69, the semiconductor device is mounted on the substrate 51A and the 51st substrate.
Since the interval for arranging on B can be made shorter by twice the depth dimension of the groove, the mounting density can be increased (details will be described later).

Another modification of the semiconductor device of the tenth embodiment is shown in FIG. 64 or FIG.

In the semiconductor device of this modification, as shown in FIG. 64 or FIG. 65, the lower mold resin 2A of the semiconductor chip 1 of the package 2 shown in FIG. 62 or 63 is removed and the main surface of the semiconductor chip 1 is removed. The surface on the opposite side is exposed.

As described above, the semiconductor chip 1 of the package 2 is
By removing the lower mold resin 2A to expose the surface opposite to the main surface of the semiconductor chip 1, the thermal resistance of the semiconductor device is further reduced, so that the overall thermal resistance can be reduced accordingly. .

As a result, it is possible to prevent the occurrence of cracks due to the temperature cycle from the corner portion of the semiconductor chip 1.

Another modification of the semiconductor device of the tenth embodiment is shown in FIG. 66 or 67.

In the semiconductor device of this modification, as shown in FIG. 66 or 67, the lower mold resin 2A of the semiconductor chip 1 of the package 2 shown in FIGS. 62 and 64 is removed and the main surface of the semiconductor chip 1 is removed. In the case where the surface on the opposite side is exposed, the relationship between the semiconductor chip 1 and the outer leads 3B is reversed.

By doing so, the mounting substrate 51
On the other hand, when the cooling of the upper surface is dominant, the cooling efficiency can be improved.

In the modification shown in FIG. 66 or 67, a heat dissipation groove may be provided on the substrate 51 side of the package 2.

Next, an embodiment of the method of mounting the substrate of the resin-sealed semiconductor device shown in FIGS. 61 to 67 of the present invention will be described.

One embodiment of the method of mounting the resin-encapsulated semiconductor device shown in FIGS. 61 to 67 is, for example, as shown in FIG. 68, resin-encapsulated semiconductor devices 60A to 60H shown in FIG. Are surface-mounted with solder 61 on both surfaces of each of the substrates 51A and 51B.

By mounting the resin-encapsulated semiconductor devices 60A to 60H on the substrates 51A and 51B in this manner, the mounting density of the semiconductor devices can be improved, and heat can also be radiated from the substrates 51A and 51B side of the package 2. Is possible. That is, the resin-sealed semiconductor device 60A
Since the heat radiation from 60H to 60H is performed by the gap 51D between each package 2 and the substrate 51A or 51B on which they are mounted, it is possible to reduce the resistance of air flow and improve the heat radiation efficiency.

Further, as shown in FIG. 69, for example, two substrates are formed by combining the heat dissipation groove 53 and the convex portion 54 in the upper portion of the package 2 of the resin-sealed semiconductor device of the embodiment shown in FIG. 63. It is mounted between 51A and 51B.

By mounting the resin-sealed semiconductor device in this manner, the mounting density of the semiconductor device can be further improved. The substrate 51A or the substrate 51 of the package 2
Heat can be released from the B side as well. That is, the interval when arranging the resin-encapsulated semiconductor devices on the substrate 51A or the substrate 51B can be made shorter by twice the depth dimension of the groove, so that the mounting density can be increased (FIG. 64). Is 1.5 times that of the above example). Further, the heat radiation of the resin-sealed semiconductor device is performed by the package 2 and the substrate 51 on which they are mounted.
Since it is performed by A or the gap 51D with the substrate 51B, the resistance of air blowing can be reduced and the heat dissipation efficiency can be improved.

(Embodiment 11) Embodiment 1 of the present invention
A resin-encapsulated semiconductor device for encapsulating the DRAM of No. 1 is shown in FIG. 70 (overall external perspective view) and FIG. 71 (partial sectional perspective view of FIG. 70).

As shown in FIGS. 70 and 71, a DRAM
(Semiconductor chip) 1 is a ZIP (Zigzag In-line Pak)
age) type resin-sealed package 2. The DRAM 1 has a large capacity of 16 [Mbit] × 1 [bit], and has a planar rectangular shape of 16.48 [mm] × 8.54 [mm]. This DRAM 1 is 450 [mil]
It is sealed in the resin-sealed package 2.

On the main surface of the DRAM 1, as shown in FIG. 71, a memory cell array and peripheral circuits are mainly arranged. The memory cell array will be described in detail later, but 1 [bi
A plurality of memory cells (storage elements) that store the information [t] are arranged in a matrix. The peripheral circuits are arranged as direct peripheral circuits and contact peripheral circuits. The direct peripheral circuit is a circuit that directly controls the information writing operation and the information reading operation of the memory cell. The direct peripheral circuit includes a row address decoder circuit, a column address decoder circuit, a sense amplifier circuit and the like. The joint peripheral circuit is a circuit which jointly controls the operation of the direct peripheral circuit. The connection peripheral circuit includes a clock signal generation circuit, a buffer circuit, and the like.

Inner leads 3A are arranged on the main surface of the DRAM 1, that is, on the surface on which the memory cell array and peripheral circuits are arranged. An insulating film 4 is interposed between the DRAM 1 and the inner lead 3A.
The insulating film 4 is formed of, for example, a polyimide resin film. An adhesive layer (not shown) is provided on each surface of the insulating film 4 on the DRAM 1 side and the inner lead 3A side. As the adhesive layer, for example, polyether amide imide resin or epoxy resin is used. Package 2 of this type employs a LOC (L ead O n C hip ) structure in which the inner leads 3A on DRAM 1. Package 2 which adopts LOC structure,
Since the inner lead 3A can be freely routed without being restricted by the shape of the DRAM 1, the DRAM 1 having a large size can be sealed by the amount corresponding to this routing. In other words, in the package 2 adopting the LOC structure, the sealing size (package size) can be kept small even if the size of the DRAM 1 becomes large due to the increase in capacity, so that the packaging density can be increased.

One end of the inner lead 3A is formed integrally with the outer lead 3B. The signals applied to the outer leads 3B are defined and numbered according to the standard. 70 and 71,
From the left end of the upper row, 1st terminal, 3rd terminal, 5th terminal, ...
The 21st, 23rd and odd numbered terminals are provided in sequence,
From the left end of the lower row, terminal 2, terminal 4, terminal 6, ...
A 22nd terminal, a 24th terminal and an even numbered terminal are sequentially provided. In other words, the package 2 is composed of 12 terminals in the upper stage and 12 terminals in the lower stage, for a total of 24 terminals.

The first terminal is an address signal terminal (A ₉ ),
The second terminal is an empty terminal, the third terminal is a column address strobe signal terminal (CE), the fourth terminal is an empty terminal, the fifth terminal is a data output signal terminal, and the sixth terminal is a reference voltage Vss terminal. The reference voltage Vss is, for example, a circuit operating voltage of 0 [V]. The 7th terminal is a power supply voltage Vcc terminal. The power supply voltage Vcc is, for example, a circuit operating voltage of 5 [V].

No. 8 terminal is a data input signal terminal (D), No. 9 terminal is an empty terminal, No. 10 terminal is a write enable signal terminal (W), No. 11 terminal is a row address strobe signal terminal.
(RE), the 12th terminal is an address signal terminal (A ₁₁ ), and the 13th terminal is an address signal terminal (A ₁₀ ). The 14th terminal is an address signal terminal (A ₀ ), and the 15th terminal is an address signal terminal
(A ₁ ), the 16th terminal is the address signal terminal (A ₂ ), the 17th terminal is the address signal terminal (A ₃ ), and the 18th terminal is the power supply voltage Vc.
It is the c terminal. The power supply voltage Vcc is, for example, a circuit operating voltage of 5 [V].

The No. 19 terminal is a reference voltage Vss terminal, and the reference voltage Vss is, for example, the operating voltage 0 [V] of the circuit.

The 20th terminal is an address signal terminal (A ₄ ), 2
The first terminal is the address signal terminal (A ₅ ), the 22nd terminal is the address signal terminal (A ₆ ), and the 23rd terminal is the address signal terminal (A ₅ ).
₇ ) and 24th terminals are address signal terminals (A ₈ ). The other end side of the inner lead 3A is extended to the center side of the DRAM 1 across the long sides of the rectangular shape of the DRAM 1. The other end of the inner lead 3A is connected to an external terminal (bonding pad) BP arranged in the central portion of the DRAM 1 with a bonding wire 5 interposed. Bonding wire 5 is aluminum
(Al) wire is used. Also, the bonding wire 5
As the material, a gold (Au) wire, a copper (Cu) wire, a coated wire in which the surface of a metal wire is coated with an insulating resin, or the like may be used. The bonding wire 5 is bonded by a bonding method using thermocompression and ultrasonic vibration.

No. 7 terminal of the inner lead 3A,
Each inner lead (Vcc) 3A of the 18th terminal is integrally formed, and the central portion of the DRAM 1 is extended parallel to its long side (this inner lead (Vcc) 3A is a common inner lead or a bus bar inner lead). It is said that). Similarly, the inner leads (Vss) 3A of the 6th terminal and the 19th terminal are integrally formed.
The center portion of the No. 1 is extended parallel to its long side (this inner lead (Vss) 3A is called a common inner lead or a bus bar inner lead). Each of the inner lead (Vcc) 3A and the inner lead (Vss) 3A extends in parallel within a region defined by the other end of the other inner lead 3A. Each of the inner lead (Vcc) 3A and the inner lead (Vss) 3A has a power supply voltage V at any position on the main surface of the DRAM 1.
cc and the reference voltage Vss can be supplied. That is, the package 2 is configured to easily absorb power supply noise, and is configured to increase the operating speed of the DRAM 1.

Chip supporting leads 3C are provided on the rectangular short sides of the DRAM 1.

Each of the inner lead 3A, the outer lead 3B, and the chip supporting lead 3C is cut and molded from the lead frame. The lead frame is, for example, Fe-Ni (for example, Ni content 42 or 50 [%]).
It is made of alloy, Cu, or the like.

The DRAM 1, the bonding wire 5,
The inner lead 3A and the chip supporting lead 3C are sealed with a resin sealing portion 6. The resin sealing portion 6 uses an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added in order to reduce the stress. Silicone rubber has the effect of reducing the coefficient of thermal expansion as well as the elastic modulus of the epoxy resin. The filler is formed of spherical silicon oxide particles, and similarly has a function of lowering the coefficient of thermal expansion.

As can be seen from the above description, according to the eleventh embodiment, the 16 MDRA of the ZIP type package is used.
Since M1 is mounted on the substrate by the vertical mounting method, the mounting density can be improved.

The present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0298]

[Table 1]

[0299]

[Table 2]

[0300]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The optimum insulator can be selected depending on the semiconductor element of the semiconductor device.

(2) In the semiconductor device, the encapsulating material has a lower melt viscosity and a better fluidity of the material than the case of using the square fused silica which has been used for a long time. Au) Deform wires or leads,
Does not flush semiconductor chips. Further, it is possible to fill the narrow gap of the package well.

(3) In the semiconductor device, the thermal expansion of the sealing material can be reduced. Therefore, the package has good crack resistance.

(4) In a semiconductor device, the encapsulating material has a high heat resistance of the molded product, and in particular, the reflow resistance (package crack) or the reflow resistance after reflow when the package is absorbed due to its excellent mechanical strength at high temperature. Moisture resistance reliability and thermal shock resistance can be obtained.

(5) In the semiconductor device, the gap between the semiconductor chip and the lead can be controlled to be constant (same as the filler diameter), and the variation in capacitance between the semiconductor chip and the lead can be reduced.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional perspective view of a resin-sealed semiconductor device that seals a DRAM according to a first embodiment of the present invention.

FIG. 2 is a plan view of FIG.

3 is a cross-sectional view taken along the line EE of FIG.

FIG. 4 is a layout diagram showing a schematic configuration of the DRAM shown in FIG.

5 is an overall plan view of the lead frame shown in FIG. 1. FIG.

6 is a cross-sectional view of essential parts showing the relationship between the inner lead shown in FIG. 1 and a semiconductor chip.

FIG. 7 is a cross-sectional view of essential parts showing the relationship between the inner leads shown in FIG. 1 and a semiconductor chip.

8 is a cross-sectional view showing a schematic configuration of a resin molded body portion which is another embodiment of the insulator shown in FIG.

9 is a cross-sectional view taken along the line of FIG.

FIG. 10 is a diagram showing a bonding portion between the resin molded body of FIG. 8 and a semiconductor chip.

FIG. 11 is an exploded assembly view showing the relationship between the semiconductor chip, the insulator, and the lead frame shown in FIG.

FIG. 12 is a diagram for explaining characteristics of a mold resin material.

FIG. 13 is a diagram for explaining characteristics of a mold resin material.

FIG. 14 is a diagram for explaining characteristics of a mold resin material.

FIG. 15 is a diagram for explaining an optimal package for injecting the mold resin of the resin-encapsulated semiconductor device shown in FIG. 1 into a mold.

FIG. 16 is a diagram for explaining an optimum package for injecting the mold resin of the resin-encapsulated semiconductor device shown in FIG. 1 into a mold.

FIG. 17 is a diagram for explaining an optimum package for injecting the mold resin of the resin-encapsulated semiconductor device shown in FIG. 1 into a mold.

FIG. 18 is a diagram for explaining an optimal package for injecting the mold resin of the resin-encapsulated semiconductor device shown in FIG. 1 into a mold.

FIG. 19 is a diagram for explaining an optimum package for injecting the mold resin of the resin-encapsulated semiconductor device shown in FIG. 1 into a mold.

FIG. 20 is a diagram for explaining a schematic configuration of a resin-encapsulated semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention.

FIG. 21 is a diagram for explaining a schematic configuration of a resin-encapsulated semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention.

FIG. 22 is a diagram for explaining a schematic configuration of a resin-encapsulated semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention.

FIG. 23 is a sectional view showing a schematic configuration of a resin-sealed semiconductor device according to a third embodiment of the present invention.

FIG. 24 is a diagram for explaining a schematic configuration of a resin-encapsulated semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention.

FIG. 25 is a plan view of a wafer of the resin-sealed semiconductor device according to the third embodiment of the present invention.

FIG. 26 is a diagram for explaining the pattern of the insulating film of the resin-encapsulated semiconductor device according to the third embodiment of the present invention.

FIG. 27 is a diagram for explaining the pattern of the insulating film of the resin-encapsulated semiconductor device according to the third embodiment of the present invention.

FIG. 28 is a diagram for explaining the pattern of the insulating film of the resin-encapsulated semiconductor device according to the third embodiment of the present invention.

FIG. 29 is a partial cross-sectional perspective view showing a schematic configuration of a resin-sealed semiconductor device according to a fourth embodiment of the present invention.

30 is a sectional view showing a state before resin molding taken along the line HO of FIG.

31 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment in which the flexible / fluid substance of FIG. 29 is used.

FIG. 32 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment when a flexible / fluid substance is used.

FIG. 33 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment when a flexible / fluid substance is used.

FIG. 34 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment when a flexible / fluid substance is used.

FIG. 35 is a sectional view showing a schematic configuration of a resin-sealed semiconductor device according to a fifth embodiment of the present invention.

36 is a diagram showing a bottom surface and a cross section of a modified example of the semiconductor chip of FIG. 35.

FIG. 37 is a diagram showing a bottom surface and a cross section of a modified example of the semiconductor chip of FIG. 35.

38 is a diagram showing a bottom surface and a cross section of a modified example of the semiconductor chip of FIG. 35.

39 is a diagram showing a bottom surface and a cross section of a modified example of the semiconductor chip of FIG. 35.

40 is a diagram showing a bottom surface and a cross section of a modified example of the semiconductor chip of FIG. 35.

41 is a diagram showing a bottom surface and a cross section of a modified example of the semiconductor chip of FIG. 35.

FIG. 42 is a diagram showing another embodiment of the present invention related to the fifth embodiment.

FIG. 43 is a partial cross-sectional perspective view showing the schematic configuration of the resin-sealed semiconductor device according to the sixth embodiment of the present invention.

44 is a cross-sectional view taken along the line H-H of FIG. 43.

FIG. 45 is a partial cross-sectional perspective view showing the schematic configuration of a resin-encapsulated semiconductor device according to a modification of the sixth embodiment of the present invention.

FIG. 46 is a cross-sectional view taken along the toe line in FIG. 45.

FIG. 47 is a partial cross-sectional perspective view showing the schematic configuration of a resin-encapsulated semiconductor device according to a modification of the sixth embodiment of the present invention.

48 is a cross-sectional view taken along the line of FIG. 47.

FIG. 49 is a partial cross-sectional perspective view showing the schematic configuration of the resin-sealed semiconductor device according to the seventh embodiment of the present invention.

50 is a cross-sectional view taken along the line Lilly of FIG. 49.

51 is a layout plan view of the element layout of the semiconductor chip and the bonding pad BP of the seventh embodiment. FIG.

FIG. 52 is an overall plan view of the lead frame of the seventh embodiment.

FIG. 53 is a plan view showing a schematic configuration of a lead frame of a resin-sealed semiconductor device according to an eighth embodiment of the present invention.

FIG. 54 is a sectional view of a semiconductor chip fixing portion of a resin-sealed semiconductor device according to an eighth embodiment of the present invention.

FIG. 55 is a cross-sectional view showing a state before resin molding of a modified example of the resin-encapsulated semiconductor device of the eighth embodiment of the present invention.

FIG. 56 is a cross-sectional view showing a state before resin molding of a modified example of the resin-encapsulated semiconductor device according to the eighth embodiment of the present invention.

FIG. 57 is a sectional view showing a state before resin molding of a modified example of the resin-encapsulated semiconductor device according to the eighth embodiment of the present invention.

FIG. 58 is a layout diagram on the semiconductor chip of the resin-sealed semiconductor device of the ninth embodiment of the present invention.

FIG. 59 is a layout diagram on the semiconductor chip of the resin-sealed semiconductor device of the ninth embodiment of the present invention.

FIG. 60 is an explanatory sectional view of a package of a resin-sealed semiconductor device according to a ninth embodiment of the present invention.

FIG. 61 is a perspective view of the resin-encapsulated semiconductor device according to the tenth embodiment as viewed from the side facing the wiring board.

62 is a cross-sectional view taken along the rule line of FIG. 61.

FIG. 63 is a sectional view of a modification of the resin-encapsulated semiconductor device of the tenth embodiment.

FIG. 64 is a cross-sectional view of another modification of the semiconductor device of the tenth embodiment.

FIG. 65 is a cross-sectional view of another modification of the semiconductor device of the tenth embodiment.

FIG. 66 is a cross-sectional view of another modification of the semiconductor device of the tenth embodiment.

FIG. 67 is a cross-sectional view of another modification of the semiconductor device of the tenth embodiment.

FIG. 68 is a cross-sectional view showing a state where the resin-sealed semiconductor device of the tenth embodiment is mounted on a wiring board.

FIG. 69 is a cross-sectional view showing a state where the resin-sealed semiconductor device of the tenth embodiment is mounted on a wiring board.

FIG. 70 is an overall external perspective view showing a schematic configuration of a resin-sealed semiconductor device that seals a DRAM according to an embodiment XI of the present invention.

71 is a partial cross-sectional perspective view of FIG. 70. FIG.

[Explanation of symbols]

1 ... DRAM, 2 ... resin-sealed package, 3 ... lead frames, 3A ... inner lead, 3A ₁ ... signal inner leads, 3A ₂ ... shared inner leads, 3B ... outer leads, 3C, 3C ₁ ... supporting leads (Suspension leads) 4, 4A, 4B, 4C, 4D ... Insulating film,
5 ... Bonding wire, 6 ... Resin molding, 7 ... Adhesive agent, 8 ... Alpha ray shielding polyimide film, 9 ... Polyimide film,
10 ... Silicon wafer, 11, 11A, 11B, 11
C, 11D, 11E, 11F, 11G, 11H ... Memory cell array.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/56 H01L 21/60 301B 21/60 301 23/50 G 23/50 (72) Inventor Kunihiko Nishi 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Within the Musashi Factory, Hitachi Ltd. (72) Inventor Ichiro Ayu 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Factory (72) Inventor Asao Nishimura 502 Jinritsu-cho Machinery Research Center, Tsuchiura-shi, Ibaraki Prefecture Hiritsu Seisakusho Co., Ltd. Inventor Akihiro Yaguchi 502 Jinritsucho, Tsuchiura-shi, Ibaraki Machinery Research Institute, Hiritsu Manufacturing Co., Ltd. Machinery Research Institute, Tate Works (72) Masatsugu Ogata 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitate Manufacturing Co., Ltd.Hitachi Research Laboratory, Ltd. (72) Inventor, Koshi Eguchi 4026 Kuji Town, Hitachi City, Ibaraki Nitate Works Co., Ltd. Hitachi Research Laboratory (72) Inventor Hiroyoshi Okazumi 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitate Manufacturing Co., Ltd.Hitachi Research Laboratory (72) Inventor Masanori Segawa 4026 Kuji Town, Hitachi City, Ibaraki Hitachi Research Laboratory Co., Ltd. ( 72) Inventor Hiroyuki Teruoji 4026, Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Takashi Yokoyama 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi Institute, Ltd. (72) Inventor Noriyuki Kaneshiro 4026 Kujimachi, Hitachi City, Ibaraki Prefecture, Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Aizo Kaneda, 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Junichi Saeki Yokohama, Kanagawa Prefecture 292, Yoshida-cho, Totsuka-ku, Hitachi, Ltd., Production Engineering Laboratory, Hitachi, Ltd. (72) Inventor, Shozo Nakamura, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture, Ltd., Production Engineering Laboratory, Hitachi, Ltd. (72) Inventor Akio Hasebe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd., Hitachi, Ltd., Production Technology Research Institute (72) Inventor, Hiroshi Kikuchi 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd., Hitachi, Ltd., Production Technology Research Institute (72) Inventor Isamu Yoshida 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture

Claims (14)

[Claims] 1. A semiconductor device in which a plurality of inner leads electrically connected to a semiconductor chip by a bonding wire and arranged on a circuit forming surface of the semiconductor chip and the semiconductor chip are sealed with a resin. A semiconductor device, wherein the resin material is a resin composition in which a thermosetting resin is mixed with a substantially spherical inorganic filler. 2. The spherical inorganic filler has a particle size distribution of 0.
1 to 100 μm, an average particle diameter of 5 to 20 μm, a maximum packing density of 0.8 or more, and 70% by weight (wt%) or more of this spherical inorganic filler is compounded in the resin composition. 1. The semiconductor device according to 1. 3. The encapsulating resin material is a resin composition containing, as the curable resin, at least one of a phenol-curable epoxy resin, a resole-type phenol resin, and a bismaleimide resin as a main component. The semiconductor device according to claim 1 or 2. 4. The encapsulating resin material contains, as the curable resin, either a resol-type phenol resin or a bismaleimide resin as a main component, and the molded product is 2
The semiconductor device according to any one of claims 1 to 3, wherein the bending strength at 15 ° C is 3 kgf / mm ² or more. 5. The encapsulating resin material as an inorganic filler has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20 μm.
5. The semiconductor device according to claim 1, wherein the semiconductor device is substantially spherical fused silica having m and a maximum packing density of 0.8 or more. 6. The encapsulating resin material as an inorganic filler has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20 μm.
m, the maximum packing density is 0.8 or more, and substantially spherical fused silica is used in an amount of 67.5% by volume (vol.
%) Or more, and the molded product has a linear expansion coefficient of 1.4 × 10
6. The semiconductor device according to each of claims 1 to 5, characterized in that the temperature is not higher than ⁵ / ° C. 7. The encapsulating material, when mixed with 10 times the amount of ion-exchanged water and extracted at 120 ° C. for 100 hours, has a pH of the extract of 3 to 7, an electric conductivity of 200 μS / cm or less, and halogen ions. 2. The extraction amount of ammonia, ammonia ions and metal ions is 10 ppm or less.
The semiconductor device according to claim 6. 8. A method of manufacturing a semiconductor device in which a plurality of inner leads electrically connected to a semiconductor chip by bonding wires and arranged on a circuit formation surface of the semiconductor chip and the semiconductor chip are sealed with a resin, There is a gap between the inner lead and the main surface of the semiconductor chip, and the resin sealing is an upper flow path portion from the outer surface of the sealing body on the main surface side of the semiconductor chip to the surface of the inner lead portion. And a lower flow path portion from the outer surface of the sealing body on the side opposite to the main surface of the semiconductor chip to the back surface of the semiconductor chip, and is formed narrower than the upper flow path portion or the lower flow path portion. A resin set that is injected from the intermediate flow path part of the gap between the inner lead and the main surface of the semiconductor chip, and mixes a thermosetting resin with a substantially spherical inorganic filler as the sealing resin material. Method of manufacturing a semiconductor device characterized by using the object. 9. The spherical inorganic filler has a particle size distribution of 0.
1 to 100 μm, an average particle diameter of 5 to 20 μm, a maximum packing density of 0.8 or more, and 70% by weight (wt%) or more of this spherical inorganic filler is compounded in the resin composition. 8. The method for manufacturing a semiconductor device according to item 8. 10. The encapsulating resin material is a resin composition containing, as the curable resin, at least one of a phenol-curable epoxy resin, a resol-type phenol resin, and a bismaleimide resin as a main component. The method of manufacturing a semiconductor device according to claim 9 or claim 9. 11. The encapsulating resin material contains, as the curable resin, either a resole-type phenol resin or a bismaleimide resin as a main component, and the molded product has a bending strength at 215 ° C. of 3 kgf / mm ^2. 11. The method for manufacturing a semiconductor device according to claim 9, wherein the above is the case. 12. The sealing resin material as an inorganic filler has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20 μm.
12. The method for manufacturing a semiconductor device according to claim 9, wherein the fused silica is substantially spherical and has a m and a maximum packing density of 0.8 or more. 13. The encapsulating resin material as an inorganic filler has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20 μm.
m, the maximum packing density is 0.8 or more, and substantially spherical fused silica is used in an amount of 67.5% by volume (vol.
%) Or more, and the molded product has a linear expansion coefficient of 1.4 × 10
13. The method for manufacturing a semiconductor device according to each of claims 9 to 12, wherein the temperature is not higher than ⁵ / ° C. 14. The encapsulating material, when mixed with 10 times the amount of ion-exchanged water and extracted at 120 ° C. for 100 hours, has a pH of the extract of 3 to 7 and an electric conductivity of 200 μS / cm or less,
14. The method for manufacturing a semiconductor device according to claim 9, wherein the extraction amount of halogen ions, ammonia ions, and metal ions is 10 ppm or less.