JP3048546B2 - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a signal transmission speed and reduce electrical noise, by fixing an inner lead portion to a circuit forming surface by an insulating adhesive partially formed at a portion where a circuit forming surface faces the inner lead portion, thereby reducing stray capacity between the semiconductor chip and the lead. SOLUTION: An interval between a semiconductor chip 1 and a portion at the outer lead side from a portion adhered to an insulating film 4 of an inner lead 3A formed to a lead frame is made wider than the interval between the semiconductor chip 1 and a portion joined to the insulating film 4 by means of a stepped structure. Also, the bonding between the main surface of the semiconductor chip 1 and the insulating film 4 and the bonding between the insulating film 4 and the inner lead 3A is performed through an adhesive 7. By doing this, the stray capacitance between the semiconductor chip and lead can be reduced smaller and the signal transmission speed can be improved and electrical noise can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a technology effective when applied to a package of a large-scale integrated circuit with a high degree of integration.

[0002]

2. Description of the Related Art Conventionally, a semiconductor chip is molded and sealed with a resin in order to protect the semiconductor chip. Before performing this sealing, position the leads on the semiconductor chip,
Several methods have been used to attach.

[0003] For example, a lead frame having a tab in the center is used, and a semiconductor chip is attached and used before sealing. In this prior art, a method of connecting an electrode pad near the periphery of a semiconductor chip to a corresponding inner lead with a bonding wire is known.

[0004] A common problem with prior art semiconductor packages has been the formation of cracks along the mold parting line, which is the exit of the lead wire of the metal lead frame.

[0005] Another problem is that the path through which contamination sources in the environment enter the semiconductor chip from the outside along the metal leads is relatively short.

Another problem is that the bonding wires required to connect the inner leads to the electrode pads of the semiconductor chip are relatively long, and the bonding wires are crossed to alternately assign input / output terminals. Was not possible.

Therefore, in order to solve the above problem, a plurality of inner leads are formed on a circuit forming surface of a semiconductor chip.
In a semiconductor device in which the semiconductor chip and the semiconductor chip are adhered with an adhesive with an insulating film interposed therebetween, the inner leads and the semiconductor chip are electrically connected by bonding wires, and the semiconductor chip is sealed with a mold resin, a circuit formation of the semiconductor chip is performed. A semiconductor device has been proposed in which a common inner lead (bus bar inner lead) is provided near a center line in the longitudinal direction of the surface (Japanese Patent Laid-Open No. 61-241959).

[0008]

However, as a result of studying the above-mentioned conventional semiconductor device, the present inventors have found the following problems.

That is, in the conventional semiconductor device, (1)
On the circuit formation surface of the semiconductor chip, a plurality of inner leads are bonded with an adhesive with the semiconductor chip and an insulating film interposed therebetween, but the floating capacitance between the inner leads and the semiconductor chip increases. However, there has been a problem that the signal transmission speed is reduced by the increase of the stray capacitance and the electrical noise is also increased.

(2) Since the area of the insulating film is large, the amount of moisture absorbed increases, and the moisture absorbed in the reflow vaporizes and expands in the package to cause a package crack.

(3) Since a polyimide-based resin is used as the material of the insulating film, the amount of moisture absorbed becomes large, and the moisture absorbed evaporates and expands in the package during reflow, causing a package crack. There was a problem of doing.

(4) Since an acrylic resin is used as the material of the adhesive, the adhesive is deteriorated by a pressure cooker test or the like, and reliability is reduced due to problems such as electrical leakage between leads and corrosion of aluminum electrodes. However, there is a problem in that the metal is deteriorated.

(5) Since a polyimide resin coating for preventing alpha (α) rays is not coated on the entire circuit forming surface of the semiconductor chip, there is a problem that an error occurs due to alpha (α) rays.

(6) Although the common inner lead (bus bar inner lead) is used as a heat radiating plate, the inner lead is not entirely covered on the element portion having a large heat generating portion.
There has been a problem that heat dissipation is insufficient for an element of 1 watt or more.

(7) Since the area of the insulating film made of the polyimide resin is large, there is a problem that the insulating film is weak against temperature cycling.

(8) Since the wire bonding is performed over the common inner lead (bus bar inner lead), there is a problem that productivity is low.

(9) Since the bonding layer is soft, it is difficult to set the wire bonding conditions, and there is a problem that productivity is poor.

(10) Since the workability for attaching the insulating film to the semiconductor chip is poor, there is a problem that productivity is poor.

(11) Since the semiconductor chip is only fixed by a part of the inner lead, the fixing of the semiconductor chip is insufficient. For this reason, there is a problem that productivity is poor because the semiconductor chip moves during resin sealing (molding).

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

An object of the present invention is to provide a technique in a semiconductor device which can improve a signal transmission speed and reduce electric noise due to a stray capacitance between a semiconductor chip and a lead.

Another object of the present invention is to provide a technique capable of improving the heat dissipation efficiency of heat generated in a semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the influence of heat during reflow in a semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the influence of heat in a temperature cycle in a semiconductor device.

Another object of the present invention is to provide a technique capable of preventing occurrence of molding defects in a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0027]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A plurality of inner leads having a first portion located on a circuit forming surface of the semiconductor chip and a second portion located outside the semiconductor chip and arranged along one side of the semiconductor chip; A semiconductor device in which a plurality of bonding pads formed on a circuit forming surface are electrically connected and sealed with a resin, wherein the inner lead
A first portion along a side of the semiconductor chip.
Are arranged in a plurality of directions, and a second direction orthogonal to the first direction is provided.
In a direction in which the circuit forming surface and the first portions of the plurality of inner leads are opposed to each other by a selectively formed insulating adhesive layer. The first portion of the inner lead and the circuit forming surface are adhered to each other, and the adhesive layer is divided near the first portion of another inner lead adjacent to the first direction and divided. The semiconductor chip is divided into a plurality of adhesive layers along one side. Further, a plurality of signals for a plurality of signals which have a first portion located on the circuit forming surface of the rectangular semiconductor chip and a second portion located outside the semiconductor chip and are arranged along the long side of the semiconductor chip A semiconductor device in which an inner lead and a plurality of bonding pads formed on the circuit formation surface are electrically connected, and the rectangular semiconductor chip and a plurality of signal inner leads are sealed with a resin. A first portion of the inner lead is connected to the semiconductor
Are arranged in a first direction along the long side of the body chip,
On the circuit forming surface in a second direction orthogonal to the first direction.
And at a portion where the circuit forming surface and the first portion of the plurality of signal inner leads face each other,
A first portion of the inner lead and the circuit forming surface are adhered to each other by a selectively formed insulating adhesive layer, and the adhesive layer is formed of another inner adjoining in the first direction. The semiconductor chip is divided near the first portion of the lead and is divided into a plurality of adhesive layers along a long side of the semiconductor chip. Further, a plurality of signals having a first portion located on a circuit forming surface of the semiconductor chip and a second portion located outside the semiconductor chip and arranged in a first direction along one side of the semiconductor chip Inner lead and circuit type of the semiconductor chip
Near the ends of the plurality of signal inner leads on the formed surface
A first portion extending in the first direction and a semiconductor chip
A shared inner lead having a second portion located outside ; the plurality of signal inner leads and a plurality of bonding pads formed on the circuit forming surface are electrically connected to each other; Wherein the first part of the signal inner lead is
A plurality of semiconductor chips are arranged in a first direction along one side of the semiconductor chip.
And the circuit shape in a second direction orthogonal to the first direction.
A first portion of the common inner lead is formed by a selectively formed insulating adhesive layer at a portion where the circuit forming surface and the first portion of the common inner lead face each other; And the circuit forming surface are adhered to each other, and the adhesive layer is divided into a plurality of adhesive layers at predetermined intervals in the first direction . Furthermore, the semiconductor device has a first portion located on the circuit forming surface of the rectangular semiconductor chip and a second portion located outside the semiconductor chip, and is arranged in a first direction along a long side of the semiconductor chip. an inner lead for multiple signals that, the on the circuit formation surface of the semiconductor chip
The vicinity of the ends of the plurality of signal inner leads is referred to as the first position.
A shared inner lead having a first portion extending in the direction and a second portion located outside the semiconductor chip, a plurality of bonding pads formed on the circuit forming surface, and the plurality of signal inner leads. A semiconductor device in which connection means for electrical connection is sealed with a resin, wherein the signal
The first part of the inner lead for the semiconductor chip is
A plurality of first members are arranged in a first direction along the long side.
Extending on the circuit forming surface in a second direction orthogonal to the first direction.
Cage, first the shared inner leads and said circuit forming surface
Is selectively formed in the part opposite to the part
The first portion of the shared inner leads by an insulating adhesive layer and said circuit forming surface is adhered to each other, the adhesive layer is divided into a plurality of adhesive layers at a predetermined interval in the first direction. Furthermore, a first portion located on a circuit forming surface of the rectangular semiconductor chip and a second portion located outside the semiconductor chip have a first portion along a long side of the semiconductor chip .
A second direction which is arranged in the direction of
An inner lead for multiple signals that Mashimasu extend to, the inner Li for the plurality of signals on a circuit forming surface of the semiconductor chip
A common inner lead having a first portion extending in the first direction near the end of the semiconductor chip and a second portion located outside the semiconductor chip; and a plurality of bondings formed on the circuit formation surface. an inner lead pad and the plurality of signals a semiconductor device comprising a connecting means for electrically connecting is sealed with a resin, a first of said signal inner leads
The portion is oriented in a first direction along a long side of the semiconductor chip.
Are arranged on the circuit forming surface in the second direction.
And at a portion where the circuit forming surface and the first portion of the common inner lead are opposed to each other, the first portion of the common inner lead and the first portion of the common inner lead are selectively formed by a plurality of insulating adhesive layers. The circuit forming surface is adhered to each other,
Further, at a portion where the circuit forming surface and the first portion of the plurality of signal inner leads face each other, a plurality of portions formed selectively and near the first portion of the adjacent inner lead are formed. First portions of the plurality of signal inner leads and the circuit forming surface are adhered to each other by an adhesive layer, and the adhesive layer is divided into a plurality of adhesive layers at predetermined intervals in the first direction .

(Function) According to the present invention, the distance between the inner lead and the semiconductor chip on the outer lead side with respect to the portion joined to the insulating film is larger than the distance between the portion joined to the insulating film. Since the step structure is widened, the stray capacitance between the semiconductor chip and the lead is smaller than that of the conventional one, so that the signal transmission speed can be improved and the electric noise can be reduced.

According to the present invention, since the area for bonding the insulating film to the main surface of the semiconductor chip is reduced, the amount of moisture absorbed by the insulating film is minimized. Can reduce the influence of heat. In addition, since the stray capacitance between the semiconductor chip and the lead is smaller than that of the conventional one,
It is possible to improve the signal transmission speed and reduce the electric noise.

According to the present invention, a plurality of inner leads are provided on the main surface of the semiconductor chip and separated (electrically insulated) from the main surface of the semiconductor chip,
Since the surface opposite to the main surface of the semiconductor chip is adhered and fixed at a part of the inner lead via an insulating film, the inner lead is not bonded to the main surface of the semiconductor chip. Can be prevented from being damaged or damaged. Further, since an insulating film is not used on the main surface of the semiconductor chip, the moisture resistance can be improved.

[0032]

Embodiments of the present invention will be specifically described below with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) A resin-encapsulated semiconductor device for encapsulating a DRAM according to Embodiment 1 of the present invention is shown in FIG.
(Partial perspective view), FIG. 2 (plan view) and FIG.
-A cross-sectional view taken along the line A).

As shown in FIG. 1, FIG. 2 and FIG.
AM (semiconductor pellet) 1 SOJ (S mall O ut-line
(J-bend) type resin-sealed package 2. The DRAM 1 has a large capacity of 16 [Mbit] × 1 [bit] and has a planar rectangular shape of 16.48 [mm] × 8.54 [mm]. This DRAM 1 is 400 [m
il] in a resin-sealed package 2.

The main surface of the DRAM 1 is mainly provided with a memory cell array and peripheral circuits. As will be described in detail later, the memory cell array has a plurality of memory cells (storage elements) for storing 1-bit information arranged in a matrix. The peripheral circuit includes a direct peripheral circuit and an indirect peripheral circuit.
The direct peripheral circuit is a circuit that directly controls the information writing operation and the information reading operation of the memory cell. Direct peripheral circuits are row address decoder circuits, column address decoder circuits,
It includes a sense amplifier circuit and the like. The indirect peripheral circuit is a circuit that indirectly controls the operation of the direct peripheral circuit. The indirect peripheral circuit includes a clock signal generation circuit, a buffer circuit, and the like.

An inner lead 3A is arranged on the main surface of the DRAM 1, that is, on the surface on which the memory cell array and the peripheral circuits are arranged. An insulating film 4 is interposed between the DRAM 1 and the inner lead 3A. The insulating film 4 is formed of, for example, a polyimide resin film. An adhesive layer (not shown) is provided on each surface of the insulating film 4 on the DRAM 1 side and the inner lead 3A side. As the adhesive layer, for example, a polyetheramideimide resin or an epoxy resin is used. Resin-sealed package 2 of this kind employs a LOC (L ead O n C hip ) structure in which the inner leads 3A on DRAM 1. The resin-sealed package 2 adopting the LOC structure can freely route the inner leads 3A without being restricted by the shape of the DRAM 1, so that a large-sized DRAM 1 can be sealed by an amount corresponding to the routing. In other words, in the resin-sealed package 2 employing the LOC structure, even if the size of the DRAM 1 is increased due to the increase in capacity, the sealing size can be kept small, so that the mounting density can be increased.

The inner lead 3A has one end integrally formed with the outer lead 3B. Signals to be applied to the outer leads 3B are defined and numbered based on the standard. In FIG. 2, the terminal on the left side is terminal No. 1, and the terminal on the right side is terminal No. 14. The right back side (the terminal number is shown on the inner lead 3A) is the 15th terminal, and the left back side is the 28th terminal. That is, this resin-sealed package 2 has terminals 1 to 6, terminals 9 to 14, and terminals 15 to 2.
It is composed of a total of 24 terminals, the 0th terminal and the 23rd to 28th terminals.

The first terminal is a power supply voltage Vcc terminal.
The power supply voltage Vcc is, for example, an operation voltage 5 [V] of the circuit. Terminal 2 is a data input signal terminal (D), terminal 3 is an empty terminal, terminal 4 is a write enable signal terminal (W), 5
The terminal No. is a row address strobe signal terminal (RE), and the terminal No. 6 is an address signal terminal (A ₁₁ ).

No. 9 terminals are address signal terminals (A ₁₀ ), 10
Terminal No. is an address signal terminal (A ₀ ), Terminal No. 11 is an address signal terminal (A ₁ ), Terminal No. 12 is an address signal terminal
(A ₂ ), the thirteenth terminal is an address signal terminal (A ₃ ). 1
The fourth terminal is a power supply voltage Vcc terminal. The 15th terminal is a reference voltage Vss terminal. The reference voltage Vss is, for example, a reference voltage 0 [V] of the circuit. The 16th terminal is an address signal terminal
(A ₄ ), terminal 17 is an address signal terminal (A ₅ ), terminal 18 is an address signal terminal (A ₆ ), terminal 19 is an address signal terminal (A ₇ ), and terminal 20 is an address signal terminal (A ₈ ).

Terminal 23 is an address signal terminal (A ₉ ), 2
The fourth terminal is an empty terminal, the 25th terminal is a column address strobe signal terminal (CE), the 26th terminal is an empty terminal, and the 27th terminal is a data output signal terminal. The 28th terminal is a reference voltage Vss terminal.

The other end of the inner lead 3A is connected to the DR
It extends across each long side of the rectangular shape of AM1 and extends to the center side of DRAM1. The other end of the inner lead 3A is connected to the DRA with the bonding wire 5 interposed.
It is connected to external terminals (bonding pads) BP arranged at the center of M1. The bonding wire 5 uses an aluminum (Al) wire. Further, as the bonding wire 5, a gold (Au) wire, a copper (Cu) wire, a coated wire in which a surface of a metal wire is coated with an insulating resin, or the like may be used. The bonding wire 5 is bonded by a bonding method using ultrasonic vibration in combination with thermocompression bonding.

No. 1 terminal of the inner lead 3A,
The respective inner leads (Vcc) 3A of the 14th terminal are integrally formed, and a central portion of the DRAM 1 is extended in parallel with its long side. Similarly, the inner leads (Vss) 3A of the 15th terminal and the 28th terminal are integrally formed, and
The central portion of the RAM 1 is stretched in parallel with its long side. Inner lead (Vcc) 3A, inner lead (Vs)
s) Each of 3A extends in parallel in a region defined by the other end of the inner lead 3A. This inner lead (Vcc) 3A, inner lead
Each of the (Vss) 3A is configured to be able to supply the power supply voltage Vcc and the reference voltage Vss at any position on the main surface of the DRAM 1. That is, the resin-encapsulated semiconductor device 2 is configured to easily absorb power supply noise,
The operation speed of M1 is configured to be increased.

The rectangular short side of the DRAM 1 is provided with a pellet supporting lead 3C.

Each of the inner lead 3A, outer lead 3B, and pellet supporting lead 3C is cut and molded from a lead frame. The lead frame is made of, for example, Fe—Ni (for example, Ni content 42 or 50).
[%]) It is formed of an alloy, Cu, or the like.

The DRAM 1, the bonding wire 5,
The inner leads 3A and the pellet supporting leads 3C are sealed with a resin sealing portion 6. The resin sealing portion 6 uses an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added in order to reduce stress. Silicone rubber has the effect of lowering the coefficient of thermal expansion of the epoxy resin. The filler is formed of spherical silicon oxide particles, and similarly has the effect of reducing the coefficient of thermal expansion.

Next, a schematic configuration of the DRAM 1 sealed in the resin-sealed type package 2 is shown in FIG. 3 (chip layout diagram).

As shown in FIG. 3, a memory cell array (MA) 11 is arranged over substantially the entire surface of the DRAM 1.
Although the DRAM 1 of the present embodiment is not limited to this,
The memory cell array 11 is roughly divided into four memory cell arrays 11A to 11D. In FIG.
1, two memory cell arrays 11A and 11B are arranged above, and two memory cell arrays 11C and 11B are arranged below.
1D is arranged. Each of the four divided memory cell arrays 11A to 11D is further subdivided into 16 memory cell arrays (MA) 11E. That is,
The DRAM 1 arranges 64 memory cell arrays 11E. One memory cell array 11E divided into 64 pieces has a capacity of 256 [Kbit].

A sense amplifier circuit (SA) 13 is arranged between two memory cell arrays 11E of the DRAM 1 divided into 64 pieces. The sense amplifier circuit 13 is configured by a complementary MISFET (CMOS). A column address decoder circuit (YDEC) 12 is disposed at one lower end of each of the four memory cell arrays 11A and 11B of the DRAM 1.
Similarly, a column address decoder circuit (YDEC) 12 is provided at one upper end of each of the memory cell arrays 11C and 11D.
Is arranged.

The memory cell arrays 11A and 11C, which are divided into four parts of the DRAM 1, have a word driver circuit (WD) 14, a row address decoder circuit (XDEC) 15, and a unit mat control circuit 16 at one right end. Each is sequentially arranged from left to right. Similarly,
At one end on the left side of each of the memory cell arrays 11B and 11D, a word driver circuit 14, a row address decoder circuit 15, and a unit mat control circuit 16 are sequentially arranged from right to left.

Each of the sense amplifier circuit 13, column address decoder circuit 12, word driver circuit 14, and row address decoder circuit 15 constitutes a direct peripheral circuit among the peripheral circuits of the DRAM 1. This direct peripheral circuit is a circuit for directly controlling the memory cells arranged in the memory cell array 11E obtained by dividing the memory cell array 11.

A peripheral circuit 17 and an external terminal BP are respectively disposed between the memory cell arrays 11A and 11B and between the memory cell arrays 11C and 11D of the DRAM 1 divided into four. Peripheral circuit 17
Amplifier circuit 1701, output buffer circuit 1702, substrate potential generation circuit (Vss generator circuit)
1703 and a power supply circuit 1704 are arranged. A total of 16 main amplifier circuits 1701 are arranged in units of 4. A total of four output buffer circuits 1702 are arranged.

The external terminals BP are formed by forming the resin-encapsulated semiconductor device 2 in a LOC structure and extending the inner leads 3A to the center of the DRAM 1.
1 is located at the center. The external terminal BP is arranged from the upper end side to the lower end side of the DRAM 1 in a region defined by each of the memory cell arrays 11A and 11C, 11B and 11D. Since the signal applied to the external terminal BP has been described in the resin-encapsulated semiconductor device 2 shown in FIG. 2 described above, the description is omitted here. Basically, the inner lead 3A to which the reference voltage (Vss) and the power supply voltage (Vcc) are applied extends from the upper end side to the lower end side on the surface of the DRAM 1, so that the DRAM 1 extends in the extending direction. A plurality of external terminals BP for the reference voltage (Vss) and the power supply voltage (Vcc) are arranged along the line. That is, DRA
M1 is configured to sufficiently supply the respective powers of the reference voltage (Vss) and the power supply voltage (Vcc). Data input signal (D), data output signal (Q), address signal (A ₀ -A
₁₁ ), each of the clock system signal and the control signal is intensively arranged in the central portion of the DRAM 1.

Each of the memory cell arrays 11A and 11C of the DRAM 1 divided into four parts, 11B,
A peripheral circuit 18 is arranged between each of the 11Ds. On the left side of the peripheral circuit 18, a row address strobe (RE) circuit 1801, a write enable (W) circuit 1802, a data input buffer circuit 1803, a VCC limiter circuit 1804, an X address driver circuit (logic stage) 1805, X A system redundancy circuit 1806 and an X address buffer circuit 1807 are arranged. Peripheral circuit 1
8, a column address strobe (CE) circuit 1808, a test circuit 1809, a VDL limiter circuit 1810, a Y address driver circuit (logical stage) 181
1, Y-system redundant circuit 1812, Y address buffer circuit 1
813 are arranged. In the center of the peripheral circuit 18, a Y address driver circuit (drive stage) 1814,
An X address driver circuit (drive stage) 1815 and a mat selection signal circuit (drive stage) 1816 are arranged.

The peripheral circuits 17 and 18 (including 16)
It is used as an indirect peripheral circuit of the RAM 1.

Next, details of the lead frame will be described. As shown in FIG. 1 and FIG. 5 (a plan view of the entire lead frame), the lead frame of the first embodiment is provided with 20 signal inner leads 3A ₁ and two shared inner leads 3A ₂ . . The inner lead 3A
(Signal inner leads 3A ₁ and common inner leads 3A _2), as shown in FIG. 3 and FIG. 6 (cross sectional view showing main) portion for bonding the insulating film (insulator) 4 of the inner lead 3A The gap between the semiconductor chip 1 and the portion closer to the outer leads 3B is wider than the gap between the portion to be joined to the insulating film (insulator) 4 and the semiconductor chip 1. Since the inner lead 3A has the step structure as described above, the stray capacitance between the semiconductor chip and the lead is smaller than that of the conventional one, so that the signal transmission speed can be improved and the electric noise can be reduced. .

The bonding between the main surface of the semiconductor chip 1 and the insulating film 4, the insulating film 4 and the inner leads 3
As shown in FIG. 6, the bonding with A is performed with an adhesive 7. As shown in FIG. 7, the adhesive 7 is not used for bonding the main surface of the semiconductor chip 1 and the insulating film 4 but is used only for bonding the insulating film 4 and the inner leads 3A. Is also good.

[0057] Incidentally, the inner leads 3A can be applied to a package shared inner leads 3A ₂ is not provided the effect described above.

Further, at a predetermined position of the lead frame,
As shown in FIG. 1 and FIG. 5, a chip supporting lead (suspension lead) 3C that is not energized for bonding and fixing the main surface of the semiconductor chip 1 is provided.

As described above, the main surface of the semiconductor chip 1 is bonded and fixed by the suspension leads 3C that are not energized,
Since the semiconductor chip 1 is firmly fixed, the reliability and the moisture resistance of the semiconductor device can be improved.

Next, the details of the insulating film 4 will be described. The area occupied by the insulating film 4 on the main surface of the semiconductor chip 1 is at least １ ／ or less of the area of the semiconductor chip 1. As described above, since the area occupied by the insulating film 4 is at least 面積 or less of the area of the semiconductor chip 1, the amount of moisture absorbed by the insulating film 4 is reduced. The effect of steam generated by heat from the cycle can be prevented. That is, the occurrence of cracks in the package can be prevented, so that the reliability of the semiconductor device can be improved.

Further, since the stray capacitance between the semiconductor chip 1 and the leads is smaller than that of the conventional device, the signal transmission speed can be improved and the electric noise can be reduced.

Further, by setting the area for bonding the insulating film 4 and the main surface of the semiconductor chip 1 to the minimum value that can be manufactured, the above-mentioned effect can be further remarkable. In addition, since an insulating film (insulating film) is used only for a part of the inner lead that adheres to the semiconductor chip, leakage between the leads can be reduced.

As shown in FIG. 8, instead of the insulating film 4 on the main surface of the semiconductor chip 1, a resin molded body 6 including a part of the inner lead 3A is used to The distance between the inner lead 3A and the semiconductor chip 1 may be made sufficiently large to reduce the stray capacitance between the semiconductor chip 1 and the inner lead 3A.

By doing so, the resin molding 6
And the mold resin (for example, resin) 2A are formed of a compatible material, so that separation between the separation interface leads can be reduced.

As shown in FIG. 10, the resin molded body 6 and the semiconductor chip 1 may be bonded with an adhesive 7.

The base material of the insulating film 4 and the resin molding 6
May be one selected from an epoxy resin, a BT (bismaleimide triazine) resin, a phenol resin (such as a resole resin), and a polyimide resin (such as an aromatic polyimide or an alicyclic polyimide containing an ether bond and a carbonyl bond). Alternatively, it is formed by using a plurality of resins as a main component, and adding an inorganic filler or a fiber curing agent, various additives, and the like as necessary.

Other examples of the base material of the insulating film 4 and the material of the resin molding 6 include alicyclic polyimide, polyester, polysulfone, aromatic polyetheramide, aromatic polyesterimide, polyphenylene sulfide, and polyamide. It is formed mainly of a thermoplastic resin such as imide and its modified product, polyetheretherketone, polyethersulfone, and polyetheramideimide, and is formed by adding an inorganic filler or fiber and additives as necessary.

The insulating film 4 or the resin molding 6
For bonding to the inner lead 3A and the semiconductor chip 1 by using an epoxy-based resin, a BT resin, a phenolic resin (such as a resol-based) polyimide-based resin, an isomerane-based resin, a silicone resin, and a plurality of these resins. It can be selected from denatured thermosetting resins or thermoplastic resins such as aromatic polyetheramide, polyetheretherketone, polysulfone, aromatic polyesterimide, polyester, and alicyclic polyimide.

In the case of a surface mount type integrated circuit such as SOJ, a vapor phase reflow soldering method or an infrared reflow soldering method is used for solder mounting on a printed circuit board (PCB). In this case, moisture absorbed in the package is reflowed. At a temperature (215 to 260 ° C.), the resin is vaporized and expanded, the adhesive at the chip interface is peeled off, the internal pressure on the peeled surface is increased, and the sealing resin may crack.

In the LOC structure, since the inner leads 3A and the semiconductor chip 1 are joined by the insulating film 4 or the resin molded body 6, the inner lead 3A and the resin molded body 6 are joined together.
The above phenomenon is accelerated by its own moisture absorption. Therefore,
To reduce this, it is effective to reduce the volume of the insulating film 4 and reduce the amount of moisture absorption.

The lower limit of the bonding area is an area that can withstand the external force received in the wire bonding and resin (resin) molding (sealing) processes.

Here, the material properties of the insulator of the insulating film 4 or the resin molding 6 will be examined.

The semiconductor device having the LOC structure or COL (Ch
As a bonding insulating material between the inner lead 3A and the semiconductor chip 1 in a semiconductor device having an (ip on led) structure, a material that satisfies two or more of the following seven conditions is used.

(1) The saturated moisture absorption rate is equal to or less than that of the sealing resin. This is effective for preventing resin cracks during vapor face soldering (VPS).

(2) Dielectric constant of 4.0 (at 10 ³ H)
z, room temperature to 200 ° C.) or less. This reduces the stray capacitance between the inner leads and the semiconductor chip.

(3) Barcol hardness at 200 ° C. should be 20 or more. This makes the wire bondability good.

(4) The content of U and Th is 1 ppb or less,
The soluble halogen element content after extraction at 120 ° C. for 100 hours is 10 ppm or less. This is effective in preventing soft errors and improving moisture resistance.

(5) Good adhesion to the semiconductor chip and the inner leads. This can ensure wire bondability, improve moisture resistance, prevent current leakage between inner leads, and the like.

(6) The coefficient of linear thermal expansion is 20 × 10 ⁶ / ° C. or less. This reduces the warpage when the insulating material is joined to the inner lead 3A, and improves the workability of joining to the semiconductor chip in the next step.

(7) In the case of a thermoplastic resin, the glass transition temperature Tg must be 220 ° C. or higher. This is because, at a high temperature (215 ° C.) during reflow soldering, a material having a glass transition temperature Tg of 220 ° C. is thermally deformed and package cracks are easily generated, but the above condition has an effect of preventing this.

An embodiment of a material satisfying at least two of the above seven conditions will be described.

For example, both surfaces of Kapton (polyimide film manufactured by DuPont) 500H or Upilex S (polyimide film manufactured by Ube Industries) are roughened, and both surfaces are coated with 25 μm of polyether imide having a glass transition temperature Tg of 220 or more. The film is a material that satisfies the conditions except for the above item (1).

Further, a bismaleimide film or an epoxy film or an epoxy-deformed polyimide film 12 using a high-purity quartz fiber or an aramid fiber as a reinforcing material.
An adhesive selected from an epoxy resin, a resole resin, an isomeramine resin, a phenol-modified epoxy resin, and an epoxy-modified polyimide resin is applied to both surfaces of 5 μm in an amount of 10 to 25.
For films coated and dried with μm, (1)
It is a material satisfying items (6) to (6).

Further, Teflon PFA (DuPont 4)
Fluoroethylene-perfluoroalkoxy copolymer), Teflon EFP (DuPont tetrafluoroethylene-perhexafluoropropylene copolymer), or Kapton F type (Toray Dupont, Kapton film) FEP thinly coated material)
On both surfaces of the film, the adhesiveness is improved by a method such as a plasma treatment, and a film coated with an adhesive selected from an epoxy resin, a resole resin, an aromatic polyetheramide resin, a polyimide precursor, etc. It is characterized in that it satisfies all of the items and has a particularly small moisture absorption and dielectric constant.

Next, a method for bonding and fixing the semiconductor chip 1 using an adhesive with the insulating film 4 interposed in the lead frame 3 will be described.

As shown in FIG. 11 (a developed view showing the relationship between the lead frame 3, the insulating film 4, and the semiconductor chip 1), the signal inner leads 3 on the main surface of the semiconductor chip 1 are formed.
A, the insulating film 4 is divided and attached with an adhesive 7 (FIGS. 1 and 6) on the position facing each of the common inner lead 3A ₂ and the suspension lead 3C. next,
As shown in FIG. 6, the signal inner lead 3A ₁ , the common inner lead 3A ₂ , and the suspension lead 3C of the lead frame 3 are bonded and fixed with an adhesive 7.

The following is an example of the molding resin material (resin). (1) The thermosetting resin has a particle size distribution of 0.1 to 100 μm,
A substantially spherical inorganic filler having an average particle size of 5 to 20 μm and a maximum packing density of 0.8 or more is 70% by weight (wt.
%) The above resin composition is used.

In this case, the resin component may be any of epoxy, resol, and polyimide.

As described above, the molding resin material using the spherical inorganic filler (for example, fused silica) is shown in FIG.
As shown in FIG. 2 (a diagram showing the relationship between the filling density of the filler and the fluidity), the influence on the melt viscosity and the fluidity of the material is small, so that the amount of the compound can be increased to reduce the thermal expansion of the material. Further, FIG. 13 (a diagram showing the relationship between the filler blending amount and the physical properties of the molded product) and FIG. 14 (a diagram showing the relationship between the filler blending amount and the thermal stress) reduce the thermal stress of the molded product by increasing the number of fillers. be able to. Therefore, the package has good crack resistance.

In particular, when a semiconductor device having a delicate structure such as the LOC structure is molded, deformation and damage of the device can be prevented.

(2) A resin composition containing at least one of high-purity phenol-curable epoxy resin, resol-type phenol resin, and bismaleimide resin as a main component is used.

As shown in Table 1 (at the end of the table), the characteristics of the cured product obtained using the unrefined resol resin are as follows. different. In addition, there is a large difference in the electrical conductivity of the extract due to the large amount of ionic impurities.

A method for producing a purified resole resin is, for example, to prepare a flask containing 500 g of phenol and 30% formalin 55%.
0 g and 5 g of zinc acetate as a curing agent are added, and the mixture is gradually heated with stirring, and heated at 90 ° C. for 60 minutes while refluxing. Thereafter, the pressure in the flask was reduced to 20 mmHg to remove condensed water and unreacted components.

Next, 300 g of acetone was added to the reaction product to dissolve the reaction product.
Stir vigorously at 00 ° C. for 30 minutes. After cooling, the strong aqueous layer was removed, the reaction product was dissolved again in 300 g of acetone, pure water was added, and the mixture was vigorously stirred at 50 ° C. for 30 minutes.
After cooling, the upper aqueous layer is removed. This washing operation is repeated five times. After each washing, a part of the reaction product is taken out and dried at 40 ° C. for 48 hours while reducing the pressure to obtain six types of resol-type phenol resins having different degrees of purification.

The number of purifications of the resol-type phenolic resin thus obtained, the melting point of the resin, the curing characteristics, and 50 g of pure water were added to 5 g of these resol-type phenolic resins to obtain 120 g of the resol-type phenolic resin.
The results of analysis of the hydrogen ion concentration (pH), electrical conductivity and extracted ionic impurity concentration of the extracted water after heating at 120 ° C. for 120 hours are summarized in Table 2 (at the last page).

As is clear from Table 2, the phenolic resin of the resole type obtained by repeating the above-mentioned washing operation five times has an extremely small amount of ionic impurities (Japanese Patent Application No. 63-163).
141750).

As described above, the effects of the purification include the moisture resistance reliability of the molded article and the Au / A
(1) The high-temperature life of the junction and the improvement of element characteristics can be achieved.

(3) High-purity resol type phenol resin or bismaleimide resin as a main component,
The molded product has a bending strength at 215 ° C. of 3 kgf / m.
Those having m ² or more, for example, those of Examples 2 and 3 in Table 1 are used.

As described above, a sealing material using a high-purity resol type phenol resin or a polyimide resin has high heat resistance of a molded product and a bending strength at 215 ° C. of 3 kgf / mm ² or more. In this case, the reflow resistance (package crack), the moisture resistance after reflow, and the thermal shock resistance become extremely good.

(4) As the inorganic filler compounded in the base resin of the above item (2) or (3), a particle size distribution of 0.1 to 1
00 μm, average particle size 5-20 μm, maximum packing density is 0.
8 or more substantially spherical fused silica,
For example, any one of Examples 1, 2, and 3 in Table 1 is used.

As described above, since the sealing material using the spherical fused silica has a small effect on the melt viscosity and fluidity of the material, the amount of the compound is increased so that the thermal expansion of the material can be reduced. Therefore, the package has good crack resistance in addition to the effects of the above item (2) or (3).

(5) The resin sealing material has a particle size distribution of 0.1 to 100 μm and an average particle size of 5 to 20 μm as an inorganic filler.
m, a substantially spherical fused silica having a maximum packing density of 0.8 or more, with respect to the whole composition, in an amount of 67.5 volume percent (vol.
%) Or more, and the molded product has a linear expansion coefficient of 1.4 × 10
~ ⁵ / ° C or less. For example, one of Examples 1, 2, and 3 in Table 1 is used.

By doing so, the effect of the spherical fused silica can be made more effective.

(6) When the resin encapsulating material is mixed with 10 times the amount of ion-exchanged water and extracted at 120 ° C. for 100 hours, the pH of the extract is 3 to 7 and the electric conductivity is 200 μS /
cm or less, and the extraction amount of halogen ions, ammonia ions and metal ions is 10 ppm or less, for example, any of Examples 1, 2, and 3 in Table 1 is used.

Next, one experimental example of Examples (1) to (6) of the resin sealing material will be described.

As shown in Table 1, an epoxy resin (conventional example), a resol type phenol resin (Example 1) and a bismaleimide resin (Example 2) were used as thermosetting resins as base resins, and as fillers, Particle size distribution 0.1 ~
Substantially spherical fused silica having a particle diameter of 100 μm, an average particle diameter of 5 to 20 μm, and a maximum packing density of 0.90, various additives are added, and the mixture is heated for 10 minutes by a biaxial roll heated to about 80 ° C. Then, after cooling, pulverization was performed to produce three types of resin sealing materials.

Next, a semiconductor device having the LOC structure shown in FIG. 1, that is, a 16 MDRAM was molded by a transfer molding machine using each resin sealing material. Mold temperature 180 ° C, transfer pressure 70kgf /
mm ² and a molding time of 90 seconds.

According to the above experimental example, the following effects could be obtained.

(1) Particle size distribution as filler: 0.1 to 1
The sealing material using substantially spherical fused silica having a diameter of 00 μm, an average particle diameter of 5 to 20 μm, and a maximum packing density of 0.8 or more is melted as compared with a generally used rectangular fused silica. Since the viscosity is low and the fluidity of the material is good, there is no need to deform the bonding wire 5 such as Au or the lead frame 3 or to flush the semiconductor chip 1 during molding, and to fill the narrow gap of the package well. did.

(2) Since the spherical fused silica has a small effect on the melt viscosity and fluidity of the material, the blending amount can be increased to reduce the thermal expansion of the material. Therefore, the package had good crack resistance.

(3) Epoxy resin is used as a conventional semiconductor encapsulating material, and phenolic resin and polyimide resin have not been put to practical use because of their poor electrical characteristics and moisture resistance reliability due to the large amount of ionic impurities. However, if a high-purity resol-type phenol resin or polyimide resin was used, good reliability could be obtained.

(4) A sealing material using a high-purity resol-type phenol-type resin or a polyimide resin has high heat resistance of a molded product, and particularly, has excellent mechanical strength at high temperatures, and thus has a high resistance to moisture when the package is absorbed by moisture. The reflow property (package crack), the moisture resistance reliability after reflow and the thermal shock resistance were extremely good.

Next, means for preventing the generation of voids, bending of the bonding wires, insufficient filling, and the like will be described in detail when the resin sealing material is injected into the mold.

As shown in FIG. 1, a plurality of inner leads 3A are bonded on the main surface of the semiconductor chip 1 with an adhesive 7 with an insulating film 4 electrically insulated from the semiconductor chip 1 interposed therebetween. Then, the inner leads 3A and the semiconductor chip 1 are electrically connected by bonding wires 5,
In a 16 MDRAM sealed with resin, as shown in FIG.
Distance H ₁ from the portion adhering to the semiconductor chip 1 of the A to the outer wall of the package 2, the package that is larger than the distance of H ₂ up to the outer wall of the package from the opposite side of the circuit forming surface of the semiconductor chip structure To

By using such a package structure, FIG. 16 (a cross-sectional view modeling FIG. 15), FIG.
As shown in FIG. 16 (a cross-sectional view of the haha of FIG. 16) and FIG. 18 (a cross-sectional view of the Nini of FIG. 16), the depths h ₃₁ and h ₃₂ of the flow path above the inner lead 3A and the depth of the inner lead 3A and the semiconductor chip 1 are different. relationship depth h ₁ of the bottom of the channel of depth h _2, and the semiconductor chip 1 of the intermediate portion is represented by each equation.

[0116] h ₁ = h ₂ = _{[h c -t c -2W f t f} / W c ]
÷ [2 (1 + W _f / W _c )] h ₃₁ = h _c −2h _1or2 −t−t _c h ₃₂ = h _1or2 + t where h _c : cavity depth t _c : chip thickness t _f : lead frame the thickness W _c: cavity width W _f: a lead frame length floating from the chip.

FIG. 19 is a graph showing the relationship between the above equations.

As described above, the resin flow path of the package 2 is divided into the upper flow path of the inner lead 3A, the intermediate flow path between the inner lead 3A and the semiconductor chip 1, and the lower flow path of the semiconductor chip 1. By setting the depth of each flow path and the resin flow path structure so that the resin average flow velocity of the flow paths becomes equal, the resin average flow velocity of each flow path shown in FIG. It is possible to prevent the bonding wire (gold wire) 5 from being bent or insufficiently filled.

Further, since the resin average flow velocity in each of the flow paths becomes equal, deformation of the semiconductor chip 1 and the inner leads 3A can be prevented, and a highly reliable package can be obtained.

(Second Embodiment) A semiconductor integrated circuit device according to a second embodiment of the present invention has a structure as shown in FIGS. 20, 21A, 21B, 22A and 22B. the entire surface of the chip closest surface of the opposing surfaces of the semiconductor chip 1 of the embodiment I of the semiconductor chip 1 of the main surface on the pasted insulating film 4 inner leads for the signals 3A ₁ and common inner leads 3A ₂ Alternatively, the insulating film 4A is partially provided.

[0121] That is, the insulating film 4A, for example, as shown in FIG. 20, in the state of the lead frame 3, to the main surface facing the semiconductor chip 1 of the signal inner leads 3A ₁ and common inner leads 3A ₂ The insulating film 4A is previously disposed on the entire surface of the surface closest to the semiconductor chip, and the insulating film 4A and the semiconductor chip 1 are bonded and fixed with an adhesive during assembly.

The lead frame 3 with the insulating film 4A is formed, for example, by coating the insulating film 4 on the entire surface of the thin film for the inner lead, which is opposed to the main surface of the semiconductor chip 1 and is closest to the semiconductor chip 1. paste, molded cut with a press or the like, the signal inner leads 3A ₁ and common inner leads 3A ₂ and insulating film 4A are fabricated at a time.

By doing so, the area of the insulating film 4A can be reduced. It is also possible to perform the position alignment of the signal inner leads 3A ₁ and common inner leads 3A ₂ and the insulating film 4A good. The signal inner leads 3A ₁ shared lead 3
It is possible to prevent leakage therebetween because there is no insulation film 4 between the A _2.

It is to be noted that, when the insulating film 4 is divided into a plurality of sheets, for example, divided into four pieces and affixed, the influence of stress due to heat can be reduced as compared with the case of one insulating film 4. .

[0125] Further, as shown in A of FIG. 21, the among the entire surface of the semiconductor chip 1 of the main surface facing the closest to the semiconductor chip 1 side surface (back surface), a shared read signal inner leads 3A ₁ only disposed an insulating film 4B portion corresponding to the bonding portion of 3A _2, the semiconductor chip 1
Occupied by the insulating film 4B can be minimized.

[0126] insulating film 4B with lead frame 3 the area occupied by the insulating film 4B for the semiconductor chip 1 is minimized, for example, as shown in B of FIG. 21, shared with the signal inner leads 3A ₁ Lead 3A ₂
Semiconductor chip 1 on the surface facing the main surface of semiconductor chip 1
A hole a provided at a predetermined position on the entire surface closest to
Like the insulating film 4 was attached, molded cut with a press or the like, the signal inner leads 3A ₁ and the insulating film 4 only in a position corresponding to the bonding portion of the shared leads 3A ₂
B is affixed.

In this manner, the amount of the insulating film can be further reduced as compared with the embodiment shown in FIG. 20, so that the amount of moisture absorption can be further reduced. In addition, the semiconductor chip 1 can be easily fixed when the suspension leads are aligned.

In the embodiment shown in FIG. 21A, the insulating film 4A is provided only on the portion corresponding to the bonding portion. However, the insulating film 4A is partially provided on other portions as necessary. The film 4A may be provided.

[0129] Further, as shown in A of FIG. 22, the extension portion as the portion of the insulating film 4A shown in FIG. 20, to intersect with the extension portions of the shared inner leads 3A ₂ and signal inner leads 3A ₁ Also, the insulating film 4C is provided.

[0130] The insulating film 4C with inner leads 3A, for example, as shown in B of FIG. 22, the hole such that only the portion corresponding to the signal inner leads 3A ₁ remains b
Is formed, and the insulating film 4 is cut into two parts by cutting along the center line of the insulating film 4 in the long side direction. Produced by pasting the bisected insulating film 4C inner leads 3A ₁ for shared inner leads 3A ₂ and signals.

[0131] it is only in this way advance the insulating film 4 was cut into a predetermined pattern to form an insulating film 4C, pasting an insulating film 4C inner leads 3A ₁ for shared inner leads 3A ₂ and the signal Therefore, the method of manufacturing the insulating film 4C is easy. Also, by doing so, since the paste insulating film 4C inner leads 3A ₁ for shared inner leads 3A ₂ and the signal, it is possible to flatten the tips of signal inner leads 3A _1, subsequent steps Work becomes easier.

[0132] The adhesion of the insulating film 4C and shared inner leads 3A ₂ and signal inner leads 3A _1, when the thermoplastic adhesive is performed at Sennetsu crimping, in the case of using a thermosetting adhesive It is joined by performing hardening after temporary fixing.

It should be noted that FIGS. 20 and 21A and FIG. 22A
The insulating films 4A, 4B, and 4C shown in (1) and (2) may be slightly wider or narrower than the width of the inner leads.

[0134] As understood from the above description, according to the second embodiment, the amount of the insulating film 4 that is disposed between the semiconductor chip 1 and the signal inner leads 3A ₁ shared lead 3A ₂ is , Because it is extremely less than the conventional one,
Even when the semiconductor device is kept in a high-humidity environment for a long time, the amount of moisture absorbed in the semiconductor device can be reduced.

Thus, since the water vapor pressure in the semiconductor device during the solder reflow process can be reduced, a semiconductor device that does not cause resin cracks can be provided.

(Third Embodiment) A semiconductor integrated circuit device according to a third embodiment of the present invention, as shown in FIG. 23, has bonding pads provided on the main surface of the semiconductor chip 1 of the first embodiment. The α-ray shielding polyimide film 8 is coated on the entire main surface area of the semiconductor chip 1 except for the BP, and at least the signal inner leads 3A are formed on the main surface of the semiconductor chip 1.
₁ and an insulating film 4D at a position where the tip of the common inner lead 3A ₂ (not shown in FIG. 23) is bonded.
Are formed.

The thickness of the α-ray shielding polyimide film 8 is as follows:
2.0 μm to 10.0 μm.

The film thickness of the insulating film 4D is 75 μm.
m or more. As the insulating film 4D, a thermosetting resin containing a printable inorganic filler is suitable.

The area occupied by the insulating film 4D is at least 以下 or less of the area of the semiconductor chip 1.

Further, a polyimide film 9 is formed on the surface of the semiconductor chip 1 opposite to the main surface.

Next, the entire area of the main surface of the semiconductor chip 1 other than the bonding pads BP provided on the main surface of the semiconductor chip 1 is covered with the α-ray shielding polyimide film 8. An embodiment of a method of forming an insulating film 4D at a place where at least the signal inner lead 3A ₁ and the tip of the shared inner lead 3A ₂ are bonded to each other is described with reference to FIGS. This will be described with reference to FIGS.

First, an α-ray shielding polyimide film 8 is applied to the entire area of the silicon wafer 10 shown in FIG. 25 (plan view of the main surface of the silicon wafer), semi-cured, and then photo-etched to form bonding pads (external terminals). The BP is exposed (Step 101 in FIG. 24A).

Next, a solvent-peelable dry film A is attached. (Step 102). A predetermined pattern is exposed on the solvent-peelable dry film A (step 10).
3) Develop and form hole B (step 104).

Next, a paste-like insulator (printing paste) C is applied, embedded with a squeegee (embedded with a printing squeegee), and cured (step 105,
106, 107).

Next, the solvent-peelable dry film A is peeled to form an insulating film 4D. Thereafter, dicing is performed along the solid line on the silicon wafer 10 shown in FIG. 25 to complete the semiconductor chip with the insulating film 4D.

Another embodiment of the method of forming the α-ray shielding polyimide film 8 and the insulating film 4D is shown in FIG.
As shown in B of FIG. 4 (manufacturing flow chart and cross-sectional view of a chip in each step), an α-ray shielding polyimide film 8 is applied to the entire region of the silicon wafer 10 and photo-etched to form a bonding pad (external terminal). ) Expose the BP (Step 201 in FIG. 24B).

Next, dry film D for solder resist
(Step 202). A predetermined pattern is exposed on the dry film D for solder resist (step 203), developed and developed to an insulating film 4D (step 2).
04) is formed. Thereafter, dicing is performed along the solid line on the silicon wafer 10 shown in FIG. 25 to complete the semiconductor chip with the insulating film 4D.

Even when the thick insulating film 4D is formed by a silicon wafer process, the silicon wafer 10 does not warp because it is partially formed.

[0149] Further, FIGS. 26 to 28, insulating property and at least a tip of the signal inner leads 3A ₁ and common inner leads 3A ₂ and suspension leads are formed where that is adhered on the main surface of the semiconductor chip 1 7 shows various pattern shapes of the film 4D.

As can be seen from the above description, according to the third embodiment, the entirety of the main surface area other than the bonding pads (external terminals) BP of the semiconductor chip 1 is covered with the α-ray shielding polyimide film 8, since at least the signal inner leads 3A ₁ and common inner leads 3A ₂ tip on the main surface of the chip 1 is an insulating film 4D to place is adhered is formed, the α line circuit shielding polyimide film 8 Α-rays can be shielded to the entire formation region, and the semiconductor chip 1 can be bonded and fixed by the insulating film 4D.

Further, since the insulating film 4D is formed on the main surface of the semiconductor chip 1 at least at the position where the tip of the inner lead 3A and the suspension lead 3C are bonded, the semiconductor chip 1 and the inner lead 3A The stray capacitance between them can be reduced.

Since the insulating film 4D is a thermosetting resin containing a printable inorganic filler,
In the wafer process, high precision insulating film 4D
Can be formed.

Further, by forming the polyimide film 9 on the surface opposite to the main surface of the semiconductor chip 1, the adhesion between the semiconductor chip 1 and the resin is improved, so that a package crack can be prevented.

The insulating film 4D is formed by applying a solvent-peelable dry film A to at least the silicon wafer 10 and passing through a normal exposure and development process, and then applying a paste-like insulator (printing paste) to the squeegee. The insulating film 4D is formed in a batch process with high precision by the wafer process including embedding, heating and curing, and peeling of the solvent peeling type dry film, so that productivity can be improved.

Further, since the insulating film 4D is formed only by exposing and developing the dry film D for solder resist, the productivity can be further improved.

(Embodiment 4) As shown in FIG. 29 (a partial cross-sectional perspective view), a resin-sealed conductor device according to Embodiment 4 of the present invention comprises a semiconductor chip 1 of Embodiment I. on the surface, a plurality of signal inner leads 3A ₁ and common inner leads 3A ₂ is, the bonded semiconductor chip 1 and electrically adhesive interposed an insulating film 4 of insulating, inner for the plurality of signals lead 3A ₁ and common inner leads 3A ₂ and the semiconductor chip 1 and the bonding wire 5
As shown in FIG. 30 (a cross-sectional view taken along a hoho line in FIG. 29 and showing a state before the resin molding) in the semiconductor device electrically connected by the semiconductor chip and sealed with the mold resin 2A, 1 is covered with a material 20 which is more flexible or flowable than the molding resin,
0 covers the entirety of the bonding wire 5,
The outside of the substance 20 is sealed with a resin 2A.

[0157] That is, the dam 21 as flexible, fluid material 20 across the bonding wires 5 are covered across the shared inner leads 3A ₂ provided, consisting of the dam 21, for example, the flow conditions silicone gel flexible The fluid / fluid substance 20 is dropped from above the bonding wire 5,
After curing, the resin is sealed by transfer molding.

The dam 21 is made of, for example, silicone rubber containing high-viscosity silica filler.

The flexible / fluid substance 20 does not necessarily have to be a gel substance as described above, and has such a flexibility or fluidity that the bonding wire 5 can be deformed inside. If so, various materials such as silicone grease and silicone rubber may be used.

By doing so, even when the main surface of the semiconductor chip 1 peels off and the vapor expands during reflow soldering of the package that has absorbed moisture, the bonding wire 5 can freely follow the deformation. In addition, disconnection of the bonding wire 5 can be prevented.

[0161] Further, when the transfer molding of the molded resin 2A, the deformation of the bonding wire 5 is restrained, even longer wire 5 to straddle the shared inner leads 3A _2, the deformation of the bonding wire 5 at the time of mold the or which due to the contact between the bonding wire 5 cross short or bonding wires 5 shared inner leads 3A ₂ can be prevented.

The material covering the bonding wire 5 does not need to be a material having flexibility and fluidity, only for the purpose of preventing the deformation of the bonding wire 5. As long as there is a resin that can be potted on the bonding wires 5 on the main surface of the semiconductor chip 1, an epoxy resin or the like having the same elastic modulus as the transfer-molded resin 2A on the outside may be used.

When the flexible / fluid substance 20 has fluidity, its viscosity needs to be higher than the melt viscosity of the resin 2A during transfer molding.

Further, since the resin 2A is not in direct contact with the bonding wire 5 due to the flexible / fluid substance 20,
At the time of the temperature cycle, the bonding wire 5 is repeatedly deformed by the relative thermal deformation between the semiconductor chip 1 and the mold resin 2A, and is not disconnected due to fatigue.

When the flexible / fluid substance 20 is used, no gap is generated on the surface of the bonding pad BP due to thermal stress, so that aluminum in the bonding pad portion is not corroded by moisture. .

FIG. 31 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment when a flexible / fluid substance 20 is used.

[0167] As shown in FIG. 31, the interface between the signal inner leads 3A ₁ and the resin. 2A, the gap is less likely to occur than the main surface of the semiconductor chip 1, the inner lead signal bonding wires 5 3A The bonding portion on the _first side is unlikely to cause disconnection. Therefore, in this embodiment, disconnection hardly occurs. Therefore, in this embodiment, the flexible / fluid substance 20 is provided only in the vicinity of the bonding portion (first bonding) on the side of the semiconductor chip 1 where disconnection easily occurs. Thereby, the bonding wire 5
If it can be freely deformed, a certain degree of disconnection prevention effect can be obtained.

[0168] Further, this embodiment is to utilize a shared inner leads 3A ₂ instead of the dam 21 of FIG 30.

However, in the case of this embodiment, since the entire bonding wire 5 is not covered with the flexible / fluid substance 20, when the package is subjected to a temperature cycle, the semiconductor chip 1 and the molding resin 2A are not connected. The bonding wire 5 is repeatedly deformed by the relative thermal deformation during the period between the steps of FIG.

In addition, there is a certain effect of preventing deformation of the bonding wire 5 during transfer molding of the resin 2A.

Further, since the amount of the flexible / fluid substance 20 can be reduced and the height can be reduced, not only is the effect of preventing disconnection during reflow soldering and wire deformation during transfer molding, but also an effect on the entire package. Can be reduced in thickness, and the mounting density can be improved.

FIG. 32 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment when a flexible / fluid substance 20 is used.

In this embodiment, as shown in FIG.
The entire main surface of the semiconductor chip 1 is covered with a flexible / fluid substance 20 so that the entire bonding wire 5 is covered.

An effect similar to that of the embodiment shown in FIG. 30 is obtained. Further, since the entire main surface of semiconductor chip 1 is covered with flexible / fluid substance 20, it is possible to further improve the moisture resistance. it can.

However, since the surface area of the flexible / fluid substance 20 becomes large, a gap is generated at the interface with the mold resin 2A during reflow soldering, and when vapor pressure acts, cracks are formed in the upper mold resin 2A. More likely to occur.

FIG. 33 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device of another embodiment when a flexible / fluid substance 20 is used.

In this embodiment, as shown in FIG.
Only the entirety of the bonding wires 5 provided on the main surface of the semiconductor chip 1 was covered with a material 20 having a more flexibility or flowability than the mold resin 2A.

The flexible / fluid substance 20 covering the bonding wires 5 does not have to be raised on the main surface of the semiconductor chip 1, and may be attached only to the surface of the bonding wires 5. Good.

In order to perform such coating, first, a flexible / fluid substance 20 which has been diluted with a solvent to have a low viscosity is dropped on the semiconductor chip 1 and adhered to the bonding wire 5, and then the solvent is applied. Is formed by evaporation.

In this case, as the layer of the flexible / fluid substance 20 on the surface of the bonding wire 5 is thicker, the effect of preventing disconnection and deformation of the bonding wire 5 is greater.

With this configuration, FIG.
Since it is possible to reduce the amount of the flexible / fluid substance 20 for obtaining the same effect as that of the embodiment shown in
The generation of package cracks can be prevented by the vapor pressure generated between the flexible / fluid substance 20 and the mold resin 2A.

FIG. 34 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device according to another embodiment when the flexible / fluid substance 20 is used.

In this embodiment, as shown in FIG.
The bonding wire 5 is covered with a flexible / fluid substance 20, and a hole 22 is made in the mold resin 2A on the surface opposite to the main surface of the semiconductor chip 1, so that a part of the semiconductor chip 1 is substantially exposed.

Here, “substantially” means that the film is easily broken when a vapor pressure is generated inside the package 2 or the thin coating of the molding resin 2A on the surface opposite to the main surface of the semiconductor chip 1 inevitably in the manufacturing process. It is assumed that a resin layer having a small thickness exists.

As described above, the flexible / fluid substance 20 can ensure the moisture resistance of the bonding pad BP without causing breakage of the bonding wire 5 during reflow soldering and temperature cycling, so that the molding resin 2A
Even if the hole 22 is formed in a part of the hole, the moisture resistance does not decrease.

Further, the vapor generated inside the package during the reflow soldering is radiated to the outside through the holes 22, so that the pressure does not increase and the resin crack does not occur.

Also, the surface of the hole 22 opposite to the main surface of the semiconductor chip 1 is not completely exposed, but the mold resin 2A is present as long as the hole 22 can be easily penetrated by vapor pressure. May be.

As can be seen from the above description, according to Embodiment IV, even if the main surface of semiconductor chip 1 is peeled off and the steam expands during reflow soldering, disconnection of bonding wire 5 is prevented. be able to.

Further, at the time of transfer molding, a short circuit between the wires due to the deformation of the bonding wire 5 or the bonding inner lead 3A ₂
Contact can be prevented.

Further, resin cracks during reflow soldering can be prevented without causing poor moisture resistance of the bonding pad BP portion and disconnection of the bonding wire 5 during a temperature cycle.

(Embodiment 5) As shown in FIG. 35 (cross-sectional view), a resin-encapsulated semiconductor device according to Embodiment 5 of the present invention is similar to that of Embodiment 1 described above. The semiconductor chip 1 is provided with a concave portion on the surface opposite to the main surface.

The recess 101 allows the molding resin 2A
Is restrained by the semiconductor chip 1, the stress generated in the mold resin portion at the corner opposite to the main surface of the semiconductor chip 1 where the reflow crack occurs can be reduced, and the reflow crack can be prevented.

The processing of the recess 101 may be etching. Further, another method may be used.

FIG. 36A (a plan view as viewed from the side opposite to the main surface in FIG. 3) and FIG. 36B (a cross-sectional view taken along the horizontal center line in FIG. 36A) show the main part of the semiconductor chip 1. FIG. 8 is a view showing a modification of the concave portion 101 provided on the surface opposite to the surface, and this example shows an annular concave portion 101 on the surface opposite to the main surface of the semiconductor chip 1.
a is provided.

FIGS. 37A (plan view) and 37 B (cross-sectional view) show another modified example of the concave portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1. An example is a rectangular recess 10 on the surface opposite to the main surface of the semiconductor chip 1.
1b.

FIGS. 38A (plan view) and FIG. 38B (side view) show modified examples of the convex portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1. Is provided with a circular convex portion 101c on the surface opposite to the main surface of the semiconductor chip 1.

FIGS. 39A (plan view) and FIG. 39B (side view) are views showing another modification of the projection 101 provided on the surface opposite to the main surface of the semiconductor chip 1. In this example, a rectangular projection 10 is provided on the surface opposite to the main surface of the semiconductor chip 1.
1d.

FIGS. 40A (plan view) and FIG. 40B (side view) show another modified example of the recess 101 provided on the surface opposite to the main surface of the semiconductor chip 1. An example is an elliptical recess 10 on the surface opposite to the main surface of the semiconductor chip 1.
1e.

FIG. 41A (plan view) and FIG. 41B (side view) show modified examples of the concave or convex portion 101 provided on the surface opposite to the main surface of the semiconductor chip 1. In this example, a plurality of grooves are formed on a surface opposite to the main surface of the semiconductor chip 1 to provide a concave portion and a convex portion 101f. This may be provided with grooves in a grid pattern.

As described above, by providing any one of the concave and convex portions 101a to 101f on the surface opposite to the main surface of the semiconductor chip 1, the semiconductor chip 1 is more strongly restrained by the mold resin 2A. be able to.

Further, it is possible to reduce the stress generated in the mold resin 2A due to the corner portion opposite to the main surface of the semiconductor chip 1.

FIG. 42 is a diagram showing another embodiment of the present invention relating to the fifth embodiment.
In the state where the silicon oxide film 102 is left on the surface opposite to the main surface of the semiconductor chip 1, for example, the concave portion or the convex portion 101 is provided on the surface opposite to the main surface of the semiconductor chip 1.

As described above, since the silicon oxide film 102 is left on the surface opposite to the main surface of the semiconductor chip 1,
Since the adhesive force between the silicon oxide film 102 and the mold resin 2A is strong, peeling of the mold resin 2A on the surface opposite to the main surface of the semiconductor chip 1 can be prevented.

Further, the semiconductor chip 1 can be firmly restrained by the mold resin 2A by the concave portions or the convex portions 101.

(Embodiment 6) A resin-encapsulated semiconductor device according to Embodiment 6 of the present invention is shown in FIGS. 43 (partial cross-sectional perspective view) and FIG. 44 (cross-sectional view taken along line F--E in FIG. 43). ), On the main surface of the semiconductor chip 1 of the embodiment I,
A plurality of signal inner leads 3A ₁ and common inner leads 3A _2, the bonded semiconductor chip 1 and electrically insulating insulating film 4 interposed an adhesive, inner leads 3A ₁ and the shared inner for the signal is electrically connected to the lead 3A ₂ and the semiconductor chip 1 through bonding wires 5, in a semiconductor device sealed with mold resin 2A, the center portion of the longitudinal side of the package 2, electrically the semiconductor chip 1 Lead 30 insulated from the heat
1a is provided, one end of which is extended to the upper part of the heat generating portion on the main surface of the semiconductor chip 1, and the other end of the heat radiating lead 301a is extended to the outside lower part of the surface of the package 2 opposite to the main surface of the semiconductor chip 1. Has been extended.

As described above, one end of the heat radiating lead 301a electrically insulated from the semiconductor chip 1 is provided at the center of the side surface in the longitudinal direction of the package so as to extend to the upper part of the heat generating portion on the main surface of the semiconductor chip 1. The heat radiation lead 30
The other end of 1a is extended to the lower part outside of the surface of the package 2 opposite to the main surface of the semiconductor chip 1,
The heat radiation efficiency of the heat generation portion of the semiconductor chip 1 can be improved.

FIGS. 45 (partial cross-sectional perspective view) and FIG. 46 (cross-sectional view taken along the toe line in FIG. 45) are views showing a modification of the heat radiation lead 301a shown in FIG. One end of the heat radiation lead 301b is extended to the upper part of the heat generating portion on the main surface of the semiconductor chip 1, and the heat radiation lead
The other end of 1b is extended to the upper outside of the main surface of the semiconductor chip 1 of the package 2.

An extension of the heat radiation lead 301b is a heat radiation plate.

As described above, at the center of the side surface in the longitudinal direction of the package, one end of the heat radiation lead 301b electrically insulated from the semiconductor chip 1 is provided so as to extend to the upper part of the heat generating portion on the main surface of the semiconductor chip 1. The heat radiation lead 30
The other end of the semiconductor chip 1b is extended to the upper portion outside the main surface of the semiconductor chip 1 of the package 2, so that the semiconductor chip 1
The heat radiation efficiency of the heat of the heat generating portion can be improved.

The portion where the other end of the heat radiation lead 301b is extended to the upper part outside the main surface of the semiconductor chip 1 of the package 2 is bent as shown by the dotted line in FIG. 46 to reduce the occupied volume. It may be.

The heat radiating leads 301a and 301a
The lead frame 1b is manufactured with the same lead frame as the signal lead frame.

(Embodiment 7) A resin-encapsulated semiconductor device according to Embodiment 7 of the present invention is shown in FIGS. 49 (partial cross-sectional perspective view) and FIG. as shown in), on the main surface of the semiconductor chip 1 of the first embodiment shown in FIG. 1, shared with the inner leads 3A ₁ for multiple signal inner leads 3A ₂ is electrically insulated from the semiconductor chip 1 adhesively bonded by interposing an insulating film 4 that, the inner leads 3A ₁ for the signal and common inner leads 3A ₂ and the semiconductor chip 1 are electrically connected by bonding wires 5, a resin sealed semiconductor In the device, the main surface of the semiconductor chip 1 is provided with bonding wires 5 wired on the main surface and the common inner leads 3A.
Bonding pads BP that do not intersect with ₂ are provided.

The element layout and bonding pads BP of the semiconductor chip 1 of the seventh embodiment are shown in FIG.
(Layout plan view).

That is, the memory cell array (MA) is arranged over substantially the entire surface of the DRAM 1. The DRAM 1 of the seventh embodiment is not limited to this, but has a large memory cell array of eight memory cell arrays 11A to 11H.
Is divided into In FIG. 47, 4
Memory cell arrays 11A, 11B, 11C and 11
D are arranged, and four memory cell arrays 11E,
11F, 11G and 11H are arranged. Each of the eight divided memory cell arrays 11A to 11H is further subdivided into 16 memory cell arrays (MA) 11. That is, in the DRAM 1, 128 memory cell arrays 11E are arranged. The one memory cell array 11 subdivided into 128 has a capacity of 128 [Kbit].

A sense amplifier circuit (SA) 13 is arranged between each of the two memory cell arrays 11 of the DRAM 1 divided into 128 pieces. The sense amplifier circuit 13 is composed of a complementary MOSFET (CMOS). A column address decoder circuit (YDEC) 12 is provided at one lower end of each of the memory cell arrays 11A, 11B, 11C and 11D of the DRAM 1 divided into eight.
Is arranged. Similarly, the memory cell arrays 11E,
A column address decoder circuit (YDEC) 12 is arranged at one upper end of each of 11F, 11G and 11H.

The DRAM 1 is divided into eight memory cells between the memory cell arrays 11A and 11B, between the memory cell arrays 11C and 11D, and between the memory cell arrays 11E and 11D.
During the period F, the peripheral circuit 17 and the external terminal BP are arranged between the memory cell arrays 11G and 11H. Further, the memory cell arrays 11A, 11B, 11C and 11
D and the memory cell arrays 11E, 11F,
Peripheral circuits 17 are located in upper regions of 11G and 11H, respectively.
And a peripheral circuit 18. As the peripheral circuit 17, a main amplifier circuit, an output buffer circuit, a substrate potential generation circuit (Vss generator circuit), and a power supply circuit are arranged.

The peripheral circuit 18 includes a row address strobe (RE) circuit, a write enable (W) circuit, a data input buffer circuit, a Vcc limiter circuit,
Address driver circuit (logic stage), X-system redundant circuit, X address buffer circuit, column address strobe (CE)
System circuit, test circuit, VDL limiter circuit, Y address driver circuit (logic stage), Y system redundancy circuit, Y address buffer circuit, Y address driver circuit (drive stage), X
Each of an address driver circuit (drive stage) and a mat selection signal circuit (drive stage) is arranged (see FIG. 4 and its description).

The external terminal BP is connected to the resin sealing type fc.
2 has a LOC structure, and the inner lead 3A is extended to the center of the DRAM 1, so that the inner lead 3A is disposed at the center of the DRAM 1 and the main surface of the semiconductor chip 1
It is arranged so as not to intersect the bonding wires 5 are wired on its main surface and a shared inner leads 3A _2.

The external terminal BP is connected to the memory cell array 11
A, 11B, 11C, 11D, 11E, 11F, 11G
And 11H are arranged from the upper end side to the lower end side of the DRAM 1 in the area defined by each of them. External terminal B
The signal applied to P is the resin sealing type f shown in FIG.
Since the description has been made in c2, the description here is omitted.

Basically, the inner leads 3A to which the reference voltage (Vss) and the power supply voltage (Vcc) are applied extend from the upper end side to the lower end side on the surface of the DRAM 1, respectively.
The DRAM 1 has a reference voltage (Vss) along its extending direction.
A plurality of external terminals BP for the power supply voltage (Vcc) are arranged. That is, the DRAM 1 has the reference voltage (Vss) and the power supply voltage.
(Vcc) so that the respective power supplies can be sufficiently supplied.

As described above, according to the seventh embodiment,
Wherein the main surface of the semiconductor chip 1, since there is no bonding pads BP of intersection with the bonding wires 5 are wired on the main surface and a shared inner leads 3A ₂ is arranged, the inner leads for a plurality of signals Bonding wire 5 for connecting 3A ₁ to semiconductor chip 1
When, it is possible to prevent short-circuiting of the common inner lead 3A _2.

Next, details of the lead frame will be described. As shown in FIG. 52 (overall leadframe plan view), the lead frame 3 according to the seventh embodiment, the inner leads 3A ₁ and two shared inner leads 3A ₂ is provided for twenty signals. The inner lead 3A ₁ is
Wherein as shown in Figure 50 (sectional view), the interval between the portions and the semiconductor chip 1 of the outer leads 3B side than the portion to be bonded to the insulating film (insulator) 4 of the signal inner leads 3A ₁ is, the insulation The structure has a step structure that is wider than the distance between the portion bonded to the conductive film (insulator) 4 and the semiconductor chip 1. Thus, inner lead 3A
The by you stepped structure, since the stray capacitance between the inner leads 3A ₁ semiconductor chip 1 and the signal is smaller than that of the prior art, it is possible to improve and reduce the electrical noise signal transmission speed .

In the seventh embodiment, the arrangement other than the arrangement of the bonding pads BP on the main surface of the semiconductor chip 1 and the lead frame is the same as that of the first embodiment.

Note that the techniques of the second to sixth embodiments can be applied to the seventh embodiment.

(Embodiment 8) As shown in FIG. 53 (a plan view showing a schematic configuration of a lead frame according to Embodiment 8) of a resin-encapsulated semiconductor device of Embodiment 8 of the present invention,
This is a modification of the lead frame of the first embodiment, in which the inner lead 3C ₁ (suspension lead) that is not energized is fixed to fix the side opposite to the main surface of the semiconductor chip 1.

As shown in FIG. 54A (a cross-sectional view of the semiconductor chip fixing portion) and FIG. 56 (a cross-sectional view of the signal inner lead portion and the common inner lead portion before resin molding), a plurality of signal Inner lead 3
A ₁ shared inner leads 3A ₂ is disposed in a state of being floated from the main surface of the semiconductor chip 1 (FIG. 56) described above, wherein the semiconductor chip 1 in the lead 3C ₁ suspension is bonded and fixed by an adhesive 7 .

As the adhesive 7, an epoxy resin,
Any of the above-mentioned adhesives such as a resole-based resin may be used.

[0228] Alternatively, it may be bonded by interposing an insulating film 4 between the hanging lead 3C ₁ and the semiconductor chip 1.

In this case, when each of the plurality of signal inner leads 3A ₁ and the shared inner lead 3A ₂ is connected to the bonding pad BP of the semiconductor chip 1 by the bonding wire 5, the signal inner lead 3A ₁ and the shared inner lead 3A _{1 are} shared. fixedly pressed from above by the jig inner leads 3A ₂ to the semiconductor chip 1, wire bonding is performed. When the wire bonding end off the presser jig, by the suspension spring back effect of the lead 3C _1, signal inner leads 3A ₁ and common inner leads 3A ₂ is in the state shown in FIG. 56.

As shown in FIG. 54B, for example,
The insulating film 4 having a predetermined thickness is interposed between the suspension lead 3C of the lead frame 3 applied to the first embodiment described above and the main surface of the semiconductor chip 1, and the semiconductor chip 1 is bonded and fixed with an adhesive 7. signal inner leads 3A ₁ shared inner leads 3A ₂ is disposed in a state of being floated from the main surface of the semiconductor chip 1 may be (Fig. 56) as. In this case, the thickness of the insulating film 4 is generally about 150 μm, but may be larger.

[0231] Further, as shown in FIG. 55 (cross-sectional view showing a state before resin molding), for example, between the signal inner leads 3A ₁ shared inner leads 3A ₂ and the semiconductor chip 1 of the main surface insulating plate 40 is inserted, the said signal inner leads 3A ₁ and common inner leads 3A ₂ and the semiconductor chip 1 are connected by bonding wires 5 electrically, may be those sealed with a molding resin.

[0232] Further, as shown in FIG. 57 (cross-sectional view showing a state before the resin mold), the insulating plate 40 of the left and right of the shared inner leads 3A ₂ and the inner leads 3A ₁ for the signal contrast, for example, the left Signal inner lead 3
A ₁ and is inserted only between the common inner lead 3A ₂ and the semiconductor chip 1 of the main surface, the inner leads 3 for right-hand signal
A ₁ shared inner leads 3A ₂ is inner leads 3A ₁ and for the signal in a state of being floated from the main surface of the semiconductor chip 1 and the common inner lead 3A ₂ and the semiconductor chip 1 are electrically connected by bonding wires 5, the mold It may be sealed with a resin.

[0233] Also, for example, to the plurality of common signal inner leads 3A ₁ inner leads 3A ₂ is disposed in a state of being floated from the main surface of the semiconductor chip 1 (FIG. 56) As, 54 as shown in and C, the suspension lead 3C ₁ to form a deeply bent suspension leads 3C ₂ and this suspension leads 3C ₂ may be bonded and fixed to opposite side surfaces and the semiconductor chip 1 of the main surface. By doing so, as the signal inner leads 3A ₁ shared inner leads 3A ₂ is disposed in a floating state from the main surface of the semiconductor chip 1, the suspension main lead 3C ₂ of the semiconductor chip 1 Since the opposite side is glued and fixed,
The step of bonding the insulating film 4 becomes unnecessary. Also,
The fixing of the semiconductor chip 1 becomes strong. Further, since the lead wire is not bonded on the memory cell, damage to the memory cell can be reduced.

As described above, according to the eighth embodiment,
By not using or minimizing the insulating film 4, moisture absorption can be reduced, so that solder reflow resistance can be improved.

In the eighth embodiment, it is preferable that an α-ray shielding polyimide film is applied to the entire main surface area other than the bonding pads of the semiconductor chip 1.

(Embodiment 9) As shown in FIGS. 58 and 59 (layout diagram on a semiconductor chip), a resin-sealed semiconductor device according to a ninth embodiment of the present invention has bonding connected to inner leads. Pad BP (solder bump 5
C) are provided with two semiconductor chips 1A and 1B formed mirror-symmetrically.

In FIG. 58, the CAS0 terminal (bonding pad BP) and the CAS1 terminal (bonding pad BP) are separated and the other terminals (bonding pad B) are separated.
P) is common. With such a layout, the capacity in the word direction is doubled.

In FIG. 59, the Do terminal and the Di terminal are separated, and the other terminals are common. With such a layout, the capacity in the bit direction is doubled.

Then, as shown in FIG. 60 (a sectional view for explaining the package), the two semiconductor chips 1A and 1B
And the bonding pad BP of the semiconductor chip 1 with the inner lead 3A interposed between the respective main surfaces.
Are electrically connected to each other by the solder bumps 5C and are sealed with a mold resin.

As described above, the two semiconductor chips 1A and 1B whose bonding pads BP to the inner leads 3A are formed mirror-symmetrically are disposed between the inner leads 3A and the semiconductor chip with the inner leads 3A sandwiched on the respective main surfaces. Since the first bonding pad BP is electrically connected to the first bonding pad BP by the solder bump 5C and sealed with a mold resin, an element having twice the capacity can be mounted without changing the outer shape of the package 2.

(Embodiment 10) Embodiment 1 of the present invention
The resin-encapsulated semiconductor device of FIG.
As shown in FIG. 62 (a cross-sectional view taken along the rule line in FIG. 61) of the semiconductor device of the first embodiment, On the surface of the package 2 facing the substrate, a heat-dissipating groove 50 that is open to the outside is provided. In this case, the distance between the bottom surface 50A of the heat dissipation groove 50 and the semiconductor chip 1, that is, the thickness dimension of the mold resin 2A below the semiconductor chip 1 is set to 0.3 mm or less.

By providing the heat dissipation groove 50 in this manner, as shown in FIGS. 68 and 69 (a cross-sectional view showing a state in which the resin-sealed semiconductor device of the tenth embodiment is mounted on a wiring board), The gap 51D between the substrate 51A or 51B and the bottom surface 50A of the heat dissipation groove 50 becomes large, and if air is blown in the direction perpendicular to the paper surface and cooling is performed, air also flows through this gap 51D. Heat is also released, and the thermal resistance of the semiconductor device is reduced.

In the structure of the present embodiment, the thickness of the molding resin 2A under the semiconductor chip 1 is reduced, and some contrivance is required at the time of resin molding. However, the molding resin 2A having a low melt viscosity at the time of molding is used. For example, as shown in FIG.
The package 2 can be formed.

Next, a modification of the resin-encapsulated semiconductor device of the tenth embodiment is shown in FIG. 63 (cross-sectional view).

In the semiconductor device of this modification, as shown in FIG. 63, a heat radiation groove 53 which is opened is also provided on the upper surface of the package 2 shown in FIG. Heat dissipation groove 50
The distance between the bottom surface 50A of the semiconductor chip 1 and the bottom surface 53A of the heat radiation groove 53 and the semiconductor chip 1, that is, the thickness dimension of the lower and upper mold resins of the semiconductor chip 1 is 0.3 mm.
It is as follows.

As described above, the semiconductor chip 1 of the package 2
By reducing the thickness of the upper mold resin 2A, the heat transfer surface is increased and the thermal resistance of the semiconductor device is reduced, so that the overall thermal resistance can be reduced accordingly. Further, as shown in FIG. 69, the semiconductor device is
Since the interval when arranging on B can be shortened by twice the depth dimension of the groove, the mounting density can be increased (details will be described later).

Another modification of the semiconductor device of the tenth embodiment is shown in FIG. 64 or FIG.

In the semiconductor device of this modification, as shown in FIG. 64 or 65, the lower mold resin 2A of the semiconductor chip 1 of the package 2 shown in FIG. The surface on the opposite side is exposed.

As described above, the semiconductor chip 1 of the package 2
By removing the lower mold resin 2A and exposing the surface opposite to the main surface of the semiconductor chip 1, the thermal resistance of the semiconductor device is further reduced, so that the overall thermal resistance can be reduced accordingly. .

Thus, it is possible to prevent the occurrence of cracks due to temperature cycling from the corners of the semiconductor chip 1.

FIG. 66 or 67 shows another modification of the semiconductor device of the tenth embodiment.

In the semiconductor device of this modification, as shown in FIG. 66 or 67, the lower mold resin 2A of the semiconductor chip 1 of the package 2 shown in FIGS. In this example, the relationship between the semiconductor chip 1 and the outer leads 3B is reversed in the exposed surface.

By doing so, the mounting substrate 51
In contrast, when the cooling of the upper surface is dominant, the cooling efficiency can be improved.

In the modification shown in FIG. 66 or 67, a heat radiation groove may be provided on the substrate 51 side of the package 2.

Next, an embodiment of a method of mounting the substrate of the resin-encapsulated semiconductor device shown in FIGS. 61 to 67 of the present invention will be described.

One embodiment of the method of mounting the substrate of the resin-encapsulated semiconductor device shown in FIGS. 61 to 67 is, for example, as shown in FIG. 68, for example, the resin-encapsulated semiconductor devices 60A to 60H shown in FIG. Are mounted on both surfaces of the substrates 51A and 51B by solder 61.

By mounting the resin-encapsulated semiconductor devices 60A to 60H on the substrates 51A and 51B as described above, the mounting density of the semiconductor device can be improved, and heat can also be radiated from the substrates 51A and 51B of the package 2. Becomes possible. That is, the resin-encapsulated semiconductor device 60A
Since the heat radiation from 60H to 60H is performed by the gap 51D between each package 2 and the substrate 51A or 51B on which these are mounted, the resistance of the air blowing can be reduced and the heat radiation efficiency can be improved.

Further, as shown in FIG. 69, for example, the two heat dissipation grooves 53 and the protrusions 54 on the package 2 of the resin-encapsulated semiconductor device of the embodiment shown in FIG. It is mounted between 51A and 51B.

By mounting the resin-encapsulated semiconductor device in this manner, the mounting density of the semiconductor device can be further improved. The substrate 51A or the substrate 51 of the package 2
Heat can also be dissipated from the B side. That is, the spacing when arranging the resin-encapsulated semiconductor devices on the substrate 51A or 51B can be shortened by twice the depth dimension of the groove, so that the mounting density can be increased (FIG. 64). 1.5 times that of the example).

Further, since the heat radiation of the resin-encapsulated semiconductor device is performed by the gap 51D between the package 2 and the substrate 51A or the substrate 51B on which the package 2 is mounted, it is necessary to reduce the resistance of the air flow and improve the heat radiation efficiency. Can be.

(Embodiment 11) Embodiment 1 of the present invention
A resin-encapsulated semiconductor device for encapsulating the DRAM of No. 1 is shown in FIG. 70 (overall perspective view) and FIG.

As shown in FIGS. 70 and 71, DRAM
(Semiconductor chip) 1 is a ZIP (Zigzag In-line Pak)
age) type resin-sealed package 2. The DRAM 1 has a large capacity of 16 [Mbit] × 1 [bit] and has a planar rectangular shape of 16.48 [mm] × 8.54 [mm]. This DRAM 1 has 450 [mil]
Is sealed in a resin-sealed package 2.

As shown in FIG. 71, a main surface of the DRAM 1 is mainly provided with a memory cell array and peripheral circuits. The memory cell array will be described in detail later.
A plurality of memory cells (storage elements) for storing the information of [t] are arranged in a matrix. The peripheral circuits are arranged as direct peripheral circuits and associated peripheral circuits. The direct peripheral circuit is a circuit that directly controls an information writing operation and an information reading operation of a memory cell. The direct peripheral circuit includes a row address decoder circuit, a column address decoder circuit, a sense amplifier circuit, and the like. The indirect peripheral circuit is a circuit that indirectly controls the operation of the direct peripheral circuit. The associated peripheral circuit includes a clock signal generation circuit, a buffer circuit, and the like.

An inner lead 3A is arranged on the main surface of the DRAM 1, that is, on the surface on which the memory cell array and the peripheral circuits are arranged. An insulating film 4 is interposed between the DRAM 1 and the inner lead 3A.
The insulating film 4 is formed of, for example, a polyimide resin film. An adhesive layer (not shown) is provided on each surface of the insulating film 4 on the DRAM 1 side and the inner lead 3A side. As the adhesive layer, for example, a polyether amide imide resin or an epoxy resin is used. Package 2 of this type employs a LOC (L ead O n C hip ) structure in which the inner leads 3A on DRAM 1. Package 2 adopting the LOC structure
Since the inner leads 3A can be freely routed without being restricted by the shape of the DRAM 1, the DRAM 1 having a large size can be sealed by an amount corresponding to the routing. That is, in the package 2 adopting the LOC structure, even if the size of the DRAM 1 is increased due to the increase in the capacity, the sealing size (package size) can be suppressed small, so that the packaging density can be increased.

The inner lead 3A has one end integrally formed with the outer lead 3B. Signals to be applied to the outer leads 3B are defined and numbered based on the standard. 70 and 71,
1st terminal, 3rd terminal, 5th terminal ...
Terminals 21 and 23 and an odd-numbered terminal are sequentially provided,
2nd terminal, 4th terminal, 6th terminal ...
Terminals 22 and 24 and even-numbered terminals are sequentially provided. In other words, the package 2 has a total of 24 terminals including 12 terminals in the upper stage and 12 terminals in the lower stage.

The first terminal is an address signal terminal (A ₉ ),
The second terminal is an empty terminal, the third terminal is a column address strobe signal terminal (CE), the fourth terminal is an empty terminal, the fifth terminal is a data output signal terminal, and the sixth terminal is a reference voltage Vss terminal. The reference voltage Vss is, for example, an operation voltage 0 [V] of the circuit. The seventh terminal is a power supply voltage Vcc terminal. The power supply voltage Vcc is, for example, an operation voltage 5 [V] of the circuit.

Terminal 8 is a data input signal terminal (D), terminal 9 is an empty terminal, terminal 10 is a write enable signal terminal (W), and terminal 11 is a row address strobe signal terminal.
(RE), the twelfth terminal is an address signal terminal (A ₁₁ ), and the thirteenth terminal is an address signal terminal (A ₁₀ ). Terminal 14 is an address signal terminal (A ₀ ), terminal 15 is an address signal terminal
(A ₁ ), terminal 16 is an address signal terminal (A ₂ ), terminal 17 is an address signal terminal (A ₃ ), and terminal 18 is a power supply voltage Vc.
This is the c terminal. The power supply voltage Vcc is, for example, an operation voltage 5 [V] of the circuit.

The 19th terminal is a reference voltage Vss terminal, and the reference voltage Vss is, for example, the operating voltage 0 [V] of the circuit.

The 20th terminal is an address signal terminal (A ₄ ), 2
Terminal 1 is an address signal terminal (A ₅ ), terminal 22 is an address signal terminal (A ₆ ), and terminal 23 is an address signal terminal (A ₅ ).
_7), the 24th pin is an address signal terminal (A _8).

The other end of the inner lead 3A is connected to the DR
It extends across each long side of the rectangular shape of AM1 and extends to the center side of DRAM1. The other end of the inner lead 3A is connected to the DRA with the bonding wire 5 interposed.
It is connected to external terminals (bonding pads) BP arranged at the center of M1. The bonding wire 5 uses an aluminum (Al) wire. Further, as the bonding wire 5, a gold (Au) wire, a copper (Cu) wire, a coated wire in which a surface of a metal wire is coated with an insulating resin, or the like may be used. The bonding wire 5 is bonded by a bonding method using ultrasonic vibration in combination with thermocompression bonding.

The seventh terminal of the inner lead 3A,
The respective inner leads (Vcc) 3A of the 18th terminal are integrally formed, and the central portion of the DRAM 1 is extended in parallel with its long side (the inner lead (Vcc) 3A is a shared inner lead or a bus bar inner lead). Is said to be). Similarly, the inner leads (Vss) 3A of the 6th terminal and the 19th terminal are integrally formed, and
The central portion of the first lead 1 is extended in parallel with its long side (this inner lead (Vss) 3A is called a common inner lead or a bus bar inner lead). Each of the inner lead (Vcc) 3A and the inner lead (Vss) 3A extends in parallel in a region defined by the other end of the other inner lead 3A. Each of the inner lead (Vcc) 3A and the inner lead (Vss) 3A is connected to the power supply voltage V at any position on the main surface of the DRAM 1.
cc and a reference voltage Vss. That is, the package 2 is configured to easily absorb power supply noise and to increase the operation speed of the DRAM 1.

A chip supporting lead 3C is provided on the rectangular short side of the DRAM 1.

Each of the inner lead 3A, outer lead 3B and chip supporting lead 3C is cut and molded from a lead frame. The lead frame is made of, for example, Fe-Ni (for example, Ni content 42 or 50 [%]).
It is formed of an alloy, Cu, or the like.

The DRAM 1, the bonding wire 5,
The inner leads 3A and the chip supporting leads 3C are sealed with a resin sealing portion 6. The resin sealing portion 6 uses an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added in order to reduce stress. Silicone rubber has the effect of lowering the coefficient of thermal expansion simultaneously with the elastic modulus of the epoxy resin. The filler is formed of spherical silicon oxide particles, and similarly has the effect of reducing the coefficient of thermal expansion.

As can be seen from the above description, according to the eleventh embodiment, the 16-MDRA
Since M1 is mounted on the board by the vertical mounting method, the mounting density can be improved.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say.

[0277]

[Table 1]

[0278]

[Table 2]

[0279]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) The reliability of the semiconductor device can be improved. (2) In a semiconductor device, it is possible to improve a signal transmission speed and reduce electric noise due to a stray capacitance between a semiconductor chip and a lead. (3) In the semiconductor device, occurrence of molding defects can be prevented. (4) In a semiconductor device, productivity can be improved. (5) In the semiconductor device, the moisture resistance can be improved.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional perspective view of a resin-sealed semiconductor device for sealing a DRAM according to a first embodiment of the present invention;

FIG. 2 is a plan view of FIG.

FIG. 3 is a sectional view taken along the line II in FIG. 2;

FIG. 4 is a layout diagram showing a schematic configuration of the DRAM shown in FIG. 1;

FIG. 5 is an overall plan view of the lead frame shown in FIG.

FIG. 6 is a cross-sectional view of a principal part showing a relationship between an inner lead and a semiconductor chip shown in FIG. 1;

FIG. 7 is a cross-sectional view of a principal part showing a relationship between an inner lead and a semiconductor chip shown in FIG. 1;

FIG. 8 is a cross-sectional view illustrating a schematic configuration of a resin molded body that is another embodiment of the insulator illustrated in FIG.

FIG. 9 is a cross-sectional view taken along a roll line in FIG.

FIG. 10 is a view showing an adhesive portion between the resin molded body of FIG. 8 and a semiconductor chip.

11 is an exploded view showing a relationship between the semiconductor chip, the insulator, and the lead frame shown in FIG. 1;

FIG. 12 is a diagram for explaining characteristics of a mold resin material.

FIG. 13 is a diagram for explaining characteristics of a mold resin material.

FIG. 14 is a diagram illustrating characteristics of a mold resin material.

FIG. 15 is a view for explaining an optimal package for injecting a mold resin of the resin-sealed semiconductor device shown in FIG. 1 into a mold.

FIG. 16 is a view for explaining an optimal package for injecting the mold resin of the resin-sealed semiconductor device shown in FIG. 1 into a mold.

FIG. 17 is a view for explaining an optimal package for injecting the mold resin of the resin-sealed semiconductor device shown in FIG. 1 into a mold.

FIG. 18 is a view for explaining an optimal package for injecting the mold resin of the resin-sealed semiconductor device shown in FIG. 1 into a mold.

FIG. 19 is a view for explaining an optimal package for injecting the mold resin of the resin-encapsulated semiconductor device shown in FIG. 1 into a mold.

FIG. 20 is a diagram illustrating a schematic configuration of a resin-sealed semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same.

FIG. 21 is a diagram illustrating a schematic configuration of a resin-sealed semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same.

FIG. 22 is a diagram illustrating a schematic configuration of a resin-sealed semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same.

FIG. 23 is a sectional view illustrating a schematic configuration of a resin-sealed semiconductor device according to a third embodiment of the present invention;

FIG. 24 is a diagram illustrating a schematic configuration of a resin-sealed semiconductor device according to a third embodiment of the present invention and a method for manufacturing the same.

FIG. 25 is a plan view of a wafer of the resin-encapsulated semiconductor device according to the third embodiment of the present invention.

FIG. 26 is a view illustrating a pattern of an insulating film of the resin-encapsulated semiconductor device according to the third embodiment of the present invention;

FIG. 27 is a diagram illustrating a pattern of an insulating film of the resin-encapsulated semiconductor device according to the third embodiment of the present invention;

FIG. 28 is a view illustrating a pattern of an insulating film of the resin-encapsulated semiconductor device according to the third embodiment of the present invention;

FIG. 29 is a partial sectional perspective view showing a schematic configuration of a resin-sealed semiconductor device according to a fourth embodiment of the present invention;

30 is a cross-sectional view showing a state before resin molding, taken along a ho-ho line in FIG. 29;

FIG. 31 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device according to another embodiment when the flexible / fluid substance of FIG. 29 is used.

FIG. 32 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device according to another embodiment when a flexible / fluid substance is used.

FIG. 33 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device according to another embodiment when a flexible / fluid substance is used.

FIG. 34 is a cross-sectional view showing a state before resin molding of a resin-sealed semiconductor device according to another embodiment when a flexible / fluid substance is used.

FIG. 35 is a sectional view showing a schematic configuration of a resin-sealed semiconductor device according to a fifth embodiment of the present invention.

FIG. 36 is a diagram showing a bottom surface and a cross section of a modification of the semiconductor chip of FIG. 35;

FIG. 37 is a diagram showing a bottom surface and a cross section of a modification of the semiconductor chip of FIG. 35;

FIG. 38 is a diagram showing a bottom surface and a cross section of a modification of the semiconductor chip of FIG. 35;

FIG. 39 is a diagram showing a bottom surface and a cross section of a modification of the semiconductor chip of FIG. 35;

FIG. 40 is a diagram showing a bottom surface and a cross section of a modification of the semiconductor chip of FIG. 35;

FIG. 41 is a diagram showing a bottom surface and a cross section of a modification of the semiconductor chip of FIG. 35;

FIG. 42 is a view showing another embodiment of the present invention relating to the fifth embodiment.

FIG. 43 is a partial sectional perspective view showing a schematic configuration of a resin-sealed semiconductor device according to a sixth embodiment of the present invention.

FIG. 44 is a sectional view taken along the line F-F in FIG. 43;

FIG. 45 is a partial cross-sectional perspective view illustrating a schematic configuration of a resin-sealed semiconductor device according to a modification of the sixth embodiment of the present invention.

FIG. 46 is a cross-sectional view taken along a toe line in FIG. 45.

FIG. 47 is a partial cross-sectional perspective view showing a schematic configuration of a resin-sealed semiconductor device according to a modification of the sixth embodiment of the present invention.

FIG. 48 is a cross-sectional view of FIG. 47 cut along a teach line.

FIG. 49 is a partial cross-sectional perspective view showing a schematic configuration of a resin-sealed semiconductor device according to a seventh embodiment of the present invention.

FIG. 50 is a sectional view taken along the line in FIG. 49;

FIG. 51 is an element layout of a semiconductor chip and a layout plan view of a bonding pad BP of the seventh embodiment;

FIG. 52 is an overall plan view of the lead frame according to the seventh embodiment.

FIG. 53 is a plan view illustrating a schematic configuration of a lead frame of a resin-sealed semiconductor device according to an eighth embodiment of the present invention;

FIG. 54 is a sectional view of a semiconductor chip fixing portion of a resin-sealed semiconductor device according to an eighth embodiment of the present invention.

FIG. 55 is a cross-sectional view showing a state before resin molding of a modification of the resin-encapsulated semiconductor device according to the eighth embodiment of the present invention;

FIG. 56 is a cross-sectional view showing a state before resin molding of a modification of the resin-encapsulated semiconductor device according to the eighth embodiment of the present invention;

FIG. 57 is a cross-sectional view showing a state before resin molding of a modification of the resin-encapsulated semiconductor device according to the eighth embodiment of the present invention;

FIG. 58 is a layout diagram on a semiconductor chip of a resin-encapsulated semiconductor device according to a ninth embodiment of the present invention;

FIG. 59 is a layout diagram on a semiconductor chip of a resin-encapsulated semiconductor device according to a ninth embodiment of the present invention;

FIG. 60 is an explanatory sectional view of a package of a resin-sealed semiconductor device according to a ninth embodiment of the present invention;

FIG. 61 is a perspective view of a resin-encapsulated semiconductor device according to a tenth embodiment as viewed from a surface facing a wiring substrate.

FIG. 62 is a sectional view taken along the rule line in FIG. 61.

FIG. 63 is a cross-sectional view of a modification of the resin-encapsulated semiconductor device of the tenth embodiment.

FIG. 64 is a sectional view of another modification of the semiconductor device of the tenth embodiment;

FIG. 65 is a sectional view of another modification of the semiconductor device of the tenth embodiment;

FIG. 66 is a cross-sectional view of another modification of the semiconductor device of the tenth embodiment.

FIG. 67 is a sectional view of another modification of the semiconductor device of the tenth embodiment;

FIG. 68 is a cross-sectional view showing a state where the resin-encapsulated semiconductor device of the tenth embodiment is mounted on a wiring board.

FIG. 69 is a cross-sectional view showing a state where the resin-encapsulated semiconductor device of the tenth embodiment is mounted on a wiring board.

FIG. 70 is an overall external perspective view showing a schematic configuration of a resin-sealed semiconductor device for sealing a DRAM according to Embodiment XI of the present invention;

FIG. 71 is a perspective view, partly in section, of FIG. 70;

[Explanation of symbols]

1 ... DRAM, 2 ... resin-sealed package, 3 ... lead frames, 3A ... inner lead, 3A ₁ ... signal inner leads, 3A ₂ ... shared inner leads, 3B ... outer leads, 3C, 3C ₁ ... supporting leads (Hanging lead), 4, 4A, 4B, 4C, 4D ... insulating film,
5 bonding wire, 6 resin molded article, 7 adhesive, 8 α-ray shielding polyimide film, 9 polyimide film,
10 ... Silicon wafer, 11, 11A, 11B, 11
C, 11D, 11E, 11F, 11G, 11H ... memory cell arrays.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Kunihiko Nishi, Inventor 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Plant, Hitachi, Ltd. (72) Inventor Ichiro Yasuo 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 20 No. 1 Inside the Musashi Plant, Hitachi, Ltd. (72) Inventor Asao Nishimura 502, Kandate-cho, Tsuchiura-shi, Ibaraki Pref. Inside the Machinery Research Laboratory, Hitachi, Ltd. (72) Makoto Kitano 502, Kondo-machi, Tsuchiura-shi, Ibaraki Co., Ltd. Hitachi, Ltd.Mechanical Laboratory (72) Inventor Akihiro Yaguchi 502, Kandate-cho, Tsuchiura-shi, Ibaraki Prefecture Hitachi, Ltd.Mechanical Laboratory (72) Inventor Sueo Kawai 502, Kandachi-cho, Tsuchiura-shi, Ibaraki, Hitachi, Ltd.Mechanical Laboratory ( 72) Inventor Masaji Ogata 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Inventor Shuji Eguchi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroyoshi Okado 4026 Kuji-machi, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Masanori Segawa 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Hiroyuki Horazoji 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. 4026 Hitachi, Ltd.Hitachi Laboratory (72) Inventor Noriyuki Kaneshiro 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Laboratory (72) Inventor Aizo Kaneda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock (72) Inventor Junichi Saeki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd.Production-Technology Research Laboratories (72) Shozo Nakamura Totsuka-ku, Yokohama-shi, Kanagawa 292 Tamachi, Hitachi, Ltd.Production Technology Laboratory (72) Inventor Akio Hasebe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd.Production Technology Laboratory (72) Inventor Hiroshi Kikuchi Yoshida, Totsuka-ku, Yokohama, Kanagawa Prefecture No. 292, Hitachi, Ltd., Production Technology Laboratory (72) Inventor Isamu Yoshida 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Japan Production Technology Laboratory, Hitachi, Ltd. (56) References JP-A-61-241959 (JP, A) JP-A-59-92556 (JP, A) JP-A-52-40062 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 23/50 H01L 21/56 H01L 21 / 60 301 H01L 23/28

Claims (5)

(57) [Claims] 1. A plurality of inner leads having a first portion located on a circuit formation surface of a semiconductor chip and a second portion located outside the semiconductor chip and arranged along one side of the semiconductor chip. A semiconductor device in which a plurality of bonding pads formed on the circuit forming surface are electrically connected and sealed with a resin, wherein a first portion of the inner lead is a semiconductor chip;
Are arranged in a first direction along one side of the first
Extending on the circuit formation surface in a second direction orthogonal to the direction
A first portion of the inner lead and a first surface of the circuit forming surface formed by a selectively formed insulating adhesive layer at a portion where the circuit forming surface and the first portion of the plurality of inner leads face each other. Are bonded to each other, and the adhesive layer is formed on the first inner lead of the other inner lead adjacent in the first direction .
Wherein the semiconductor chip is divided into a plurality of adhesive layers along one side of the semiconductor chip. 2. A first portion located on a circuit forming surface of a rectangular semiconductor chip and a second portion located outside the semiconductor chip.
And a plurality of signal inner leads arranged along a long side of the semiconductor chip and a plurality of bonding pads formed on the circuit forming surface are electrically connected to each other, and the rectangular A semiconductor device in which a semiconductor chip and a plurality of signal inner leads are sealed with a resin, wherein a first portion of the inner lead is a semiconductor chip.
Are arranged in a first direction along the long side of the first
Extending on the circuit formation surface in a second direction orthogonal to the direction
A first portion of the inner lead and a first portion of the circuit are formed by an insulating adhesive layer selectively formed at a portion where the circuit forming surface and the first portion of the plurality of signal inner leads are opposed to each other; The bonding surface is adhered to each other, and the adhesive layer is divided near a first portion of another inner lead adjacent in the first direction and divided into a plurality of adhesive layers along a long side of the semiconductor chip. A semiconductor device characterized by being performed. 3. A semiconductor device comprising: a first portion located on a circuit forming surface of a semiconductor chip; and a second portion located outside the semiconductor chip, and arranged in a first direction along one side of the semiconductor chip. A plurality of signal inner leads and the semiconductor chip;
Of the plurality of signal inner leads on the circuit forming surface of the
A first portion and a half extending in the first direction near the end;
A shared inner lead having a second portion located outside the conductive chip , wherein the plurality of signal inner leads and a plurality of bonding pads formed on the circuit forming surface are electrically connected to each other; Is a semiconductor device sealed with resin, wherein a first portion of the signal inner lead is
A plurality of chips are arranged in a first direction along one side of the chip.
On the circuit forming surface in a second direction orthogonal to the first direction
A portion where the circuit forming surface and the first portion of the common inner lead face each other, the first portion of the common inner lead and the first portion of the common inner lead are formed by an insulating adhesive layer selectively formed. A semiconductor device, wherein a circuit formation surface is adhered to each other, and the adhesive layer is divided into a plurality of adhesive layers at predetermined intervals in the first direction . 4. A first portion located on a circuit forming surface of a rectangular semiconductor chip and a second portion located outside a semiconductor chip.
And a first portion along a long side of the semiconductor chip .
An inner lead for a plurality of signals are arranged in a direction, the inner for the plurality of signals on a circuit forming surface of the semiconductor chip
A first portion extending in the first direction near the end of the lead;
And a connecting means for electrically connecting the plurality of bonding pads formed on the circuit forming surface and the plurality of signal inner leads to each other. Is a semiconductor device sealed with a resin, wherein a first portion of the signal inner lead is
A plurality of chips are arranged in a first direction along the long side of the chip.
On the circuit forming surface in a second direction orthogonal to the first direction
A portion where the circuit forming surface and the first portion of the common inner lead face each other, the first portion of the common inner lead and the first portion of the common inner lead are formed by an insulating adhesive layer selectively formed. A semiconductor device, wherein a circuit formation surface is adhered to each other, and the adhesive layer is divided into a plurality of adhesive layers at predetermined intervals in the first direction . 5. A first portion located on a circuit forming surface of a rectangular semiconductor chip and a second portion located outside a semiconductor chip.
And a first portion along a long side of the semiconductor chip .
In a second direction orthogonal to the first direction
Extending the inner leads for a plurality of signals that Mashimasu, the plurality of signal inner leads on the circuit formation surface of the semiconductor chip
A common inner lead having a first portion extending in the first direction near the end of the semiconductor chip and a second portion located outside the semiconductor chip; and a plurality of bonding pads formed on the circuit forming surface. And a connecting means for electrically connecting the signal inner leads to the plurality of signal inner leads, wherein the first portion of the signal inner leads is a semiconductor device.
A plurality of chips arranged in a first direction along a long side of the chip;
A plurality of insulating portions selectively formed at a portion extending on the circuit forming surface in a second direction and opposing the circuit forming surface and the first portion of the common inner lead. The first portion of the common inner lead and the circuit forming surface are adhered to each other by the adhesive layer, and further, at a portion where the circuit forming surface and the first portion of the plurality of signal inner leads face each other. A plurality of adhesive layers formed selectively in the vicinity of the first portions of the adjacent inner leads by a plurality of adhesive layers;
And the circuit formation surface is adhered to each other, and the adhesive layer is divided into a plurality of adhesive layers at predetermined intervals in the first direction .