JPH0595072A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0595072A
JPH0595072A JP3255431A JP25543191A JPH0595072A JP H0595072 A JPH0595072 A JP H0595072A JP 3255431 A JP3255431 A JP 3255431A JP 25543191 A JP25543191 A JP 25543191A JP H0595072 A JPH0595072 A JP H0595072A
Authority
JP
Japan
Prior art keywords
semiconductor device
pad
inner lead
wire
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3255431A
Other languages
Japanese (ja)
Inventor
Yuugo Koyama
裕吾 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3255431A priority Critical patent/JPH0595072A/en
Publication of JPH0595072A publication Critical patent/JPH0595072A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To embody a semiconductor device which prevents wire contact by means of a level difference on a wire produced by a level difference between a pad and an inner lead. CONSTITUTION:There is provided a level difference between each adjacent outer terminal which is a pad 2 on a semiconductor device 1. A level difference is also provided between each adjacent inner lead 3 where the pads 2 are connected to the inner leads 3 by means of wires 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
パッドの面積の小さい半導体素子を有する半導体装置、
隣合うパッドの間隔の狭い半導体素子を有する半導体装
置、或いは半導体素子チップと、リードの半導体素子と
接続される側（インナーリード）とを接続するワイヤの
長さが長い半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor element having a small pad area.
The present invention relates to a semiconductor device having a semiconductor element in which adjacent pads are closely spaced, or a semiconductor device in which a wire connecting a semiconductor element chip and a side of a lead connected to a semiconductor element (inner lead) is long.

【０００２】[0002]

【従来の技術】半導体装置の一形態として、集積回路が
形成された半導体素子上の入出力端子であるボンディン
グパッドとこれに対応したリードフレームの各インナー
リード部とが結線され、ついで各リードの先端部（アウ
ターリード）を残して射出成型機等によりプラスチック
などで一体的に成型されているものがある。その際、ボ
ンディングパッドとインナーリードとの接続の一方式と
してワイヤ（導電性金属細線）を用いたものがある。2. Description of the Related Art As one form of a semiconductor device, a bonding pad, which is an input / output terminal on a semiconductor element on which an integrated circuit is formed, and each inner lead portion of a lead frame corresponding to the bonding pad are connected to each other. There is one that is integrally molded of plastic or the like by an injection molding machine or the like except for the tip portion (outer lead). At that time, there is a method using a wire (conductive thin metal wire) as one method of connecting the bonding pad and the inner lead.

【０００３】上記のような半導体装置は高集積化、高機
能化等ニーズによる半導体素子のＩ／Ｏピン数（入出力
端子数）増大に伴い半導体装置自体の外部との入出力端
子数も増大する傾向にある。これに伴って半導体素子と
リードフレームとを接続するワイヤの本数も増大してゆ
く。従って半導体装置の基板実装密度は益々増大する傾
向にある。In the semiconductor device as described above, the number of I / O pins (the number of input / output terminals) of the semiconductor element is increased due to the needs for higher integration and higher functionality, and the number of input / output terminals with the outside of the semiconductor device itself is also increased. Tend to do. Along with this, the number of wires connecting the semiconductor element and the lead frame also increases. Therefore, the board mounting density of the semiconductor device tends to increase more and more.

【０００４】[0004]

【発明が解決しようとする課題】上記のような半導体装
置の方向性を踏まえると、半導体チップ上のパッド部分
の面積縮小化、隣合うパッド同士の間隔の縮小化、それ
に伴うインナーリード部分の隣合う者同士の間隔の縮小
化を進めなければならない。その際パッド部分とインナ
ーリード部分とを接続するワイヤの本数が増えるため、
接続後の樹脂封止の際のワイヤ同士の接触という問題が
生じる。また上記細密化に伴いワイヤのパッド部側の端
子部同士の接触という問題も生じてくる。以上のような
問題点は、基板実装の高密度化を妨げる大きな要因とな
り得る。In view of the above-mentioned directivity of the semiconductor device, the area of the pad portion on the semiconductor chip is reduced, the distance between the adjacent pads is reduced, and the adjacent inner lead portion is adjacent. It is necessary to reduce the distance between people who fit together. At that time, since the number of wires connecting the pad portion and the inner lead portion increases,
There is a problem that the wires contact each other when the resin is sealed after the connection. In addition, the problem of contact between the terminal portions on the pad portion side of the wire also occurs due to the above-mentioned miniaturization. The above problems can be a major factor that hinders high-density board mounting.

【０００５】[0005]

【課題を解決するための手段】本発明による半導体装置
は、半導体装置のチップと半導体装置のチップの周囲に
配されたインナーリードと、半導体装置のチップとイン
ナーリードとをワイヤによりボンディングしている、樹
脂封止された半導体装置において、半導体装置のチップ
上の回路の入出力端であるパッドとインナーリードとを
ワイヤボンディングしているワイヤに高低の差があるこ
とを特徴とする。In a semiconductor device according to the present invention, a chip of a semiconductor device and an inner lead arranged around the chip of the semiconductor device, and a chip of the semiconductor device and an inner lead are bonded by a wire. In a resin-sealed semiconductor device, there is a difference in height between wires for wire-bonding a pad which is an input / output terminal of a circuit on a chip of the semiconductor device and an inner lead.

【０００６】[0006]

【実施例】図１は本発明の一実施例を示す要部の図であ
る。１は半導体チップ、２は半導体チップ上の回路の外
部端子であるパッド電極、３はリードフレームのインナ
ーリード、４はパッドとインナーリードとを接続するワ
イヤである。また、図２に図１の半導体チップ上のパッ
ド部の断面図を示す。５は半導体チップ、６はパッド電
極、７はパッドとインナーリードとを接続するワイヤで
ある。半導体チップのパッド部に図１、図２で示す隣合
うパッドの高さが相異なるものが形成されている。隣合
うパッドの高さが異なるため、半導体チップ上のパッド
上にボンディングされたワイヤの端子の隣合う者同士の
高さも異なってきている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram of a main part showing an embodiment of the present invention. Reference numeral 1 is a semiconductor chip, 2 is a pad electrode which is an external terminal of a circuit on the semiconductor chip, 3 is an inner lead of a lead frame, and 4 is a wire which connects the pad and the inner lead. 2 is a sectional view of the pad portion on the semiconductor chip of FIG. Reference numeral 5 is a semiconductor chip, 6 is a pad electrode, and 7 is a wire connecting the pad and the inner lead. In the pad portion of the semiconductor chip, adjacent pads having different heights shown in FIGS. 1 and 2 are formed. Since the heights of the adjacent pads are different, the heights of the adjacent terminals of the wire bonded on the pads on the semiconductor chip are also different.

【０００７】図３は図１のインナーリードをチップ側上
方から見た図である。８はインナーリード、９はパッド
とインナーリードとを接続するワイヤ、１０はインナー
リードの横ずれを防ぐためのテープである。図３のよう
にインナーリードの先端部が一つおきに変形していて、
隣合うインナーリード同士の高さが相異なるようになっ
ている。隣合うインナーリードの先端部の高さが相異な
るためインナーリードの先端部上にボンディングされた
ワイヤの端子の隣合う者同士の高さも異なっている。FIG. 3 is a view of the inner lead shown in FIG. 1 viewed from above the chip side. Reference numeral 8 is an inner lead, 9 is a wire connecting the pad and the inner lead, and 10 is a tape for preventing lateral displacement of the inner lead. As shown in Figure 3, every other tip of the inner lead is deformed,
The inner leads adjacent to each other have different heights. Since the heights of the tips of the inner leads adjacent to each other are different, the heights of the terminals of the wires bonded on the tips of the inner leads are also different from each other.

【０００８】図２と図３を組み合わせたのが図１であ
る。高低差がある半導体チップ上のパッド部の高い方と
高低差があるインナーリード先端部の高い方とがワイヤ
で接続され、またパッド部の低い方とインナーリード部
の低い方とがワイヤで接続されている。ここからパッド
部とインナーリードの先端部とを接続しているワイヤの
両端子部の、それぞれ隣合う者同士に高低差が生まれて
いる。またパッド部とインナーリード部とを接続してい
るワイヤ自体も両端子部の高低差のため、隣合うもの同
士に高低差が生まれている。FIG. 1 is a combination of FIG. 2 and FIG. The upper part of the pad on the semiconductor chip that has a height difference and the higher part of the inner lead tip that has a height difference are connected by a wire, and the lower pad part and the lower inner lead part are connected by a wire. Has been done. From this, a difference in height is created between adjacent terminals of both terminal portions of the wire connecting the pad portion and the tip portion of the inner lead. Further, the wire itself connecting the pad portion and the inner lead portion also has a height difference between both terminal portions, so that a height difference occurs between adjacent wires.

【０００９】[0009]

【発明の効果】従来はパッド部の構造が平面的であった
ため隣合うパッド部間隔が狭くなると隣合うパッド部上
のワイヤ端子同士が接触してしまう恐れがあった。また
隣合うパッド部間隔が狭くなりまた隣合うインナーリー
ド同士の間隔が狭くなるとワイヤ同士が接触してしまう
恐れがあった。本発明はパッド部とインナーリード部と
を接続するワイヤの隣合うもの同士に高低差がついてい
ることでワイヤ同士、またワイヤ端子部同士の接触を防
ぐ効果がある。Since the structure of the pad portion is planar in the related art, there is a possibility that the wire terminals on the adjacent pad portions may come into contact with each other when the space between the adjacent pad portions becomes narrow. Further, if the space between the adjacent pad portions becomes narrow and the space between the adjacent inner leads becomes narrow, the wires may come into contact with each other. The present invention has an effect of preventing contact between the wires and between the wire terminal portions because the adjacent wires connecting the pad portion and the inner lead portion have a height difference.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体装置の一実施例を示す要部の
図。FIG. 1 is a diagram of a main portion showing an embodiment of a semiconductor device of the present invention.

【図２】図１の半導体チップ上のパッド部の断面図。FIG. 2 is a sectional view of a pad portion on the semiconductor chip of FIG.

【図３】図１のインナーリードをチップ側上方から見た
図。FIG. 3 is a view of the inner lead of FIG. 1 viewed from above the chip side.

【符号の説明】[Explanation of symbols]

１，５， 半導体チップ ２，６， パッド ３，８， インナーリード ４，７，９， ワイヤ １０， テープ 1, 5, semiconductor chip 2, 6, pad 3, 8, inner lead 4, 7, 9, wire 10, tape

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】半導体装置のチップと半導体装置のチップ
の周囲に配されたインナーリードと、半導体装置のチッ
プとインナーリードとをワイヤ（導電性金属細線）によ
り結線（ボンディング）している、樹脂封止された半導
体装置において、半導体装置のチップ上の回路の入出力
端であるパッドとインナーリードとをボンディングして
いるワイヤに高低の差があることを特徴とする半導体装
置。1. A resin, in which a semiconductor device chip and inner leads arranged around the semiconductor device chip and a semiconductor device chip and inner leads are connected (bonded) by a wire (conductive thin metal wire). In a sealed semiconductor device, there is a difference in height between a wire bonding a pad which is an input / output terminal of a circuit on a chip of the semiconductor device and an inner lead.
JP3255431A 1991-10-02 1991-10-02 Semiconductor device Pending JPH0595072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3255431A JPH0595072A (en) 1991-10-02 1991-10-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3255431A JPH0595072A (en) 1991-10-02 1991-10-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0595072A true JPH0595072A (en) 1993-04-16

Family

ID=17278676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3255431A Pending JPH0595072A (en) 1991-10-02 1991-10-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0595072A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021150513A (en) * 2020-03-19 2021-09-27 株式会社東芝 Semiconductor chip and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021150513A (en) * 2020-03-19 2021-09-27 株式会社東芝 Semiconductor chip and semiconductor device

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