JPS5821180Y2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5821180Y2 JPS5821180Y2 JP1976082382U JP8238276U JPS5821180Y2 JP S5821180 Y2 JPS5821180 Y2 JP S5821180Y2 JP 1976082382 U JP1976082382 U JP 1976082382U JP 8238276 U JP8238276 U JP 8238276U JP S5821180 Y2 JPS5821180 Y2 JP S5821180Y2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- semiconductor device
- assembly
- leads
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置に関し、特に半導体装置の大きさを
変更することなく機能を増大した半導体装置の構造を提
供することを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly aims to provide a structure of a semiconductor device with increased functionality without changing the size of the semiconductor device.
−例の半導体装置にＩＣ，ＬＳＩ（大規模集積回路装置
）がある。- Examples of semiconductor devices include ICs and LSIs (large-scale integrated circuit devices).
これらは数十個の素子を含んでなるが、これを保護する
ことや、取扱い上ある程度の大きさに組立てをする必要
があり、大きさの分布は長さｌＱｍｍないし６０ｍｍに
なる。Although these devices include several dozen elements, they must be protected and assembled to a certain size for handling purposes, and the size distribution ranges from 1Q mm to 60 mm in length.
−例の形状を第１図ａ−ｃにて示す。- Example shapes are shown in Figures 1a-c.
図ａは直方体型の樹脂パッケージの両側面から突出した
外部リードが約９０’折曲して平行に一方向に延びたい
わゆるＤＩＰ型リード、図すは単列にて一方向に突出し
たリード、図Ｃは外囲器の１面の円周上から突出したリ
ード、にて上記はいづれも多く適用されているリードの
配置である。Figure a shows a so-called DIP type lead in which the external leads protruding from both sides of a rectangular parallelepiped resin package are bent approximately 90' and extend parallel to each other in one direction. Figure C shows the leads protruding from the circumference of one side of the envelope, and the above-mentioned lead arrangements are often used.
次には一応現在の半導体装置がその大きさにおいて取扱
上、または組立て上好適したものであるためにこれに収
めたい要望と、半導体装置の機能の倍加に対する要望と
に応えるために本考案はなされたものである。Next, the present invention was developed in order to meet the needs of the current semiconductor devices, which are suitable for handling and assembly due to their size, and the desire to double the functions of semiconductor devices. It is something that
本考案は従来の構造の半導体装置に対する要望を充たす
ためになされたもので、半導体装置の大きさを変えるこ
となく機能を倍加する如く改良された構造を提供するも
のである。The present invention was developed to satisfy the need for a semiconductor device having a conventional structure, and provides an improved structure that doubles the functionality without changing the size of the semiconductor device.
本考案の半導体装置はフレーム状リードに半導体チップ
を配設した組立体を、半導体チップが外側になるように
フレームリードを対面させて対に、かつ、フレームリー
ドの間に電気絶縁板を介して１体に樹脂モールド形成さ
れたものである。The semiconductor device of the present invention is an assembly in which a semiconductor chip is arranged on a frame-like lead, and the assembly is arranged in pairs with the frame leads facing each other so that the semiconductor chip is on the outside, and an electrically insulating plate is interposed between the frame leads. It is molded into a single piece of resin.
以下に本考案を一実施例の半導体装置につき図面を参照
して詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings for an embodiment of a semiconductor device.
第２図に示すところは薄金属板でなるフレーム状リード
１に半導体チップ２を配設した組立体３の上面図で４，
４′・・・・・・は半導体チップにおける電極とリード
とを接続する金属細線である。FIG. 2 shows a top view of an assembly 3 in which a semiconductor chip 2 is arranged on a frame-shaped lead 1 made of a thin metal plate.
4'... are thin metal wires connecting electrodes and leads on the semiconductor chip.
か・る組立体を第３図に示す如く一例として半導体チッ
プを外側にフレームリードを対面せしめて支持し、この
間に電気絶縁板５を介挿してこれに密接せしめ第４図に
側面の断面図で示す如くなる。As an example of such an assembly, as shown in FIG. 3, a semiconductor chip is supported with the frame leads facing each other on the outside, and an electrically insulating plate 5 is inserted between them and brought into close contact therewith, and FIG. 4 is a side sectional view. It becomes as shown.
次に第４図において点線で示した内部をプラスチックの
如き合成樹脂でモールディング（ｍｏｌｄｉｎｇ）を施
し樹脂封止の外囲器６を形成し第５図ａに上面図で、ま
た同図すに側面図で示す如く形成される。Next, the interior indicated by the dotted line in FIG. 4 is molded with a synthetic resin such as plastic to form a resin-sealed envelope 6, and the top view is shown in FIG. 5a, and the side view is shown in FIG. It is formed as shown in the figure.
あるいは上記モールディング後第６図ａに上面図で、ま
た同図すに側面図で示す如くリードに折曲を施してもよ
い。Alternatively, after the above molding, the leads may be bent as shown in the top view in FIG. 6a and in the side view in the same figure.
第６図に示す形状はＤＩＰ型ＩＣを背中合わせに配置し
たものとほぼ同大で、機能面では倍加されている。The shape shown in FIG. 6 is approximately the same size as DIP type ICs arranged back to back, but has double the functionality.
さらにモールディング前に両方の組立体の所要部分に接
続を施すこともでき、回路配線を簡単にできる利点もあ
る。Furthermore, connections can be made to the required parts of both assemblies before molding, which has the advantage of simplifying circuit wiring.
本考案の上記実施例においては樹脂を用いたパツケージ
を例示したが同じ容量でキャンパッケージすることも容
易である。In the above embodiment of the present invention, a package using resin is illustrated, but it is also easy to use a can package with the same capacity.
さらにＩＣに限らずダイオード、ＳＣＲ等についても可
能である。Furthermore, it is possible to apply not only ICs but also diodes, SCRs, etc.
本考案によれば現用の半導体装置にほぼその大きさを変
えることなく機能を増大することができ、半導体装置の
取扱上、または組立て上にも極めて好適する利点を備え
る。According to the present invention, it is possible to increase the functionality of an existing semiconductor device without substantially changing its size, and it has the advantage that it is extremely suitable for handling and assembling the semiconductor device.
さらにこの考案の構造の特徴である半導体チップを外側
に、フレームリードを内側に対に配置するとともにフレ
ームリードの間に電気絶縁板を介挿させ対面させる構造
により、半導体チップ相互の電気的干渉、発振等による
悪影響を接地電位になっているフレームリードで遮蔽し
防止できる利点がある。Furthermore, the structure of this invention is characterized by arranging the semiconductor chips on the outside and the frame leads on the inside in pairs, and interposing an electrically insulating plate between the frame leads so that they face each other, thereby preventing mutual electrical interference between the semiconductor chips. There is an advantage that the negative effects caused by oscillation etc. can be shielded and prevented by the frame lead which is at ground potential.
また、外囲器形成のための樹脂モールド（トランスファ
モールド）はモールド型内に組立体を保持させ、ここに
高粘性のモールド樹脂を圧入するのできわめて変型を生
じやすい。Furthermore, the resin mold (transfer mold) for forming the envelope is extremely susceptible to deformation because the assembly is held within the mold and a highly viscous mold resin is press-fitted therein.
本考案は電気絶縁板を介して対のフレームリードを固定
するので相互の変型が防止され、さらに双方のフレーム
リードの接地電位が異なっている場合にも有効である。The present invention fixes a pair of frame leads through an electrically insulating plate, thereby preventing mutual deformation, and is also effective even when the ground potentials of both frame leads are different.
第１図ａないしＣは従来の半導体装置の外形を示すいづ
れも斜視図、第２図は本考案の一実施例の半導体装置の
組立体の正面図、第３図から第６図までは本考案の一実
施例の半導体装置の製造順序を示す図で第３図および第
４図は断面図、第５図および第６図は夫々の図ａは上面
図、図すは側面図である。
１・・・・・・フレームリード、２・・・・・・半導体
チップ、３・・・・・・組立体、５・・・・・・電気絶
縁板、６・・・・・・外囲器。FIGS. 1A to 6C are perspective views showing the external shape of a conventional semiconductor device, FIG. 2 is a front view of an assembly of a semiconductor device according to an embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views, and in each of FIGS. 5 and 6, a is a top view and a is a side view. DESCRIPTION OF SYMBOLS 1...Frame lead, 2...Semiconductor chip, 3...Assembly, 5...Electric insulating board, 6...Outer enclosure vessel.
Claims (1)
半導体チップが外側になるようにフレームリードを対面
させて対に、かつ、フレームリードの間に電気絶縁板を
介して１体に樹脂モールド形成された半導体装置。An assembly in which a semiconductor chip is placed on a frame-shaped lead,
A semiconductor device that is resin-molded into a pair with frame leads facing each other so that the semiconductor chip is on the outside, and an electrically insulating plate interposed between the frame leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976082382U JPS5821180Y2 (en) | 1976-06-23 | 1976-06-23 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976082382U JPS5821180Y2 (en) | 1976-06-23 | 1976-06-23 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53762U JPS53762U (en) | 1978-01-06 |
| JPS5821180Y2 true JPS5821180Y2 (en) | 1983-05-04 |
Family
ID=28562853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1976082382U Expired JPS5821180Y2 (en) | 1976-06-23 | 1976-06-23 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821180Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4929974A (en) * | 1972-07-19 | 1974-03-16 | ||
| JPS5029163A (en) * | 1973-07-17 | 1975-03-25 | ||
| JPS5148168A (en) * | 1974-10-22 | 1976-04-24 | Matsushita Electric Ind Co Ltd | KONSEISHUSEKIKAIROSOCHI |
-
1976
- 1976-06-23 JP JP1976082382U patent/JPS5821180Y2/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4929974A (en) * | 1972-07-19 | 1974-03-16 | ||
| JPS5029163A (en) * | 1973-07-17 | 1975-03-25 | ||
| JPS5148168A (en) * | 1974-10-22 | 1976-04-24 | Matsushita Electric Ind Co Ltd | KONSEISHUSEKIKAIROSOCHI |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53762U (en) | 1978-01-06 |
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