JPH04150065A - Semiconductor package lead frame - Google Patents

Semiconductor package lead frame

Info

Publication number
JPH04150065A
JPH04150065A JP27460090A JP27460090A JPH04150065A JP H04150065 A JPH04150065 A JP H04150065A JP 27460090 A JP27460090 A JP 27460090A JP 27460090 A JP27460090 A JP 27460090A JP H04150065 A JPH04150065 A JP H04150065A
Authority
JP
Japan
Prior art keywords
island
semiconductor package
lead frame
plane
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27460090A
Other languages
Japanese (ja)
Inventor
Hiroshi Nishida
宏 西田
Toshihiko Sato
敏彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP27460090A priority Critical patent/JPH04150065A/en
Publication of JPH04150065A publication Critical patent/JPH04150065A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance yield by placing a fixed angle to a wider plane of an island at the tip opposite to the island of an internal lead and by forming a recessed part on the tip of the island in the central part with regards to a vertical direction to the flat plane of the island. CONSTITUTION:An internal lead terminal 1 of a lead frame is connected with a bonding pad 5 on a semiconductor chip 2 bonded with an island of the lead frame by means of a bonding wire 3 where the tip opposite to the island 4 is recessed in shape in the central part vertically on the plane of the island 4. Moreover, a wider plane of the island 4 is bent so as to keep a fixed angle. This construction makes it possible to prevent the generation of contact and disconnection of each bonding wire during the sealing of resin.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封入型半導体装置に適する半導体パッケー
ジ用リードフレームに関し、特に内部リート・端子の形
状を改良したリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor package suitable for a resin-encapsulated semiconductor device, and more particularly to a lead frame with improved shapes of internal leads and terminals.

〔従来の技術〕[Conventional technology]

従来の半導体パッケージ用リードフレームについて図面
を用いて説明する。第３図（ａ）は従来の半導体チップ
取付後の半導体用リードフレームの上面図、同図（ｂ）
はそのＢ１−８２横断面図である。リードフレームの内
部リード端子すは、リードフレームのアイランドつと同
一平面上にあり、その先端形状は角形かつ平坦である。A conventional lead frame for a semiconductor package will be explained with reference to the drawings. Figure 3 (a) is a top view of a conventional semiconductor lead frame after mounting a semiconductor chip, and Figure 3 (b)
is its B1-82 cross-sectional view. The internal lead terminals of the lead frame are on the same plane as the islands of the lead frame, and their tips are square and flat.

内部リード端子６とアイランド９上に接合された半導体
チップ７のポンディングパッド１０との間はボンディン
グワイヤ８で接続されている。Bonding wires 8 connect internal lead terminals 6 and bonding pads 10 of semiconductor chip 7 bonded on island 9 .

第４図は、この従来のリードフレームを用いた樹脂封止
型の半導体装置の半導体パッケージ形成工程を説明する
ための半導体パッケージの内部状態図である。半導体パ
ッケージ３０を形成する際に樹脂３１を矢印の方向に流
すと、アイランド９に接合されている半導体チップ７上
の複数のボンディングパット１０と複数の内部リード端
子６との間にそれぞれ接続されているホンティングワイ
ヤ８は、樹脂３１の流れにより隣接のボンディングワイ
ヤ８と接触する恐れがあった。FIG. 4 is an internal state diagram of a semiconductor package for explaining the process of forming a semiconductor package of a resin-sealed semiconductor device using this conventional lead frame. When the resin 31 is flowed in the direction of the arrow when forming the semiconductor package 30, the resin 31 is connected between the plurality of bonding pads 10 on the semiconductor chip 7 bonded to the island 9 and the plurality of internal lead terminals 6, respectively. There was a risk that the bonding wire 8 in the bonding wire 8 would come into contact with the adjacent bonding wire 8 due to the flow of the resin 31.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

この従来の半導体パッケージ用リードフレームては、樹
脂封入型の半導体装置の製造において、半導体パッケー
ジ形成工程である樹脂封入の際、封入される樹脂によっ
てボンディングワイヤが隣接のボンディングワイヤと接
触して不良となり、半導体パッケージ形成における歩留
りが低下するという問題点があった。In this conventional lead frame for semiconductor packages, during resin encapsulation, which is a semiconductor package forming process, in the manufacture of resin-encapsulated semiconductor devices, bonding wires come into contact with adjacent bonding wires due to the encapsulated resin, resulting in defects. However, there was a problem in that the yield in semiconductor package formation was reduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による半導体パッケージ用リードフレームは、ア
イランドと複数の内部リード端子を含む半導体パッケー
ジ用リードフレームにおいて、前記内部リード端子の前
記アイランドに対向した先端部は前記アイランドの平面
に垂直な方向に関して中央部か凹状とされ、かつ前記内
部リード端子の先端部は前記アイランドの底面に対し一
定の角度か付けられている。A lead frame for a semiconductor package according to the present invention includes an island and a plurality of internal lead terminals, in which the tip of the internal lead terminal facing the island is located at the center in the direction perpendicular to the plane of the island. The inner lead terminal has a concave shape, and the tip of the inner lead terminal is formed at a certain angle with respect to the bottom surface of the island.

〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）は本発明の一実施例の上面図であり、半導
体チップ取付後の半導体パッケージ用リードフレームを
示している。第１図（ｂ）はそのＡｌ−Ａ２横断面図で
ある。リードフレームの内部リート端子１は、リードフ
レームのアイランド４に接合された半導体チップ２上の
ポンディングパッド５にホンティングワイヤ３によって
接続される。ここて、各々の内部リード端子１のアイラ
ンド４に対向した先端部は、アイランド４の平面に垂直
な方向に関して中央部が凹状とされ、且つアイランド４
の広面に関して一定の角度になるように折り曲げられて
いる。FIG. 1(a) is a top view of one embodiment of the present invention, showing a lead frame for a semiconductor package after a semiconductor chip is attached. FIG. 1(b) is a cross-sectional view of the Al-A2. The internal lead terminals 1 of the lead frame are connected by honting wires 3 to bonding pads 5 on the semiconductor chip 2 bonded to the islands 4 of the lead frame. Here, the tip of each internal lead terminal 1 facing the island 4 has a concave center portion in a direction perpendicular to the plane of the island 4, and
It is bent at a certain angle with respect to the wide surface of the

第２図は、本実施例による半導体装置の半導体パッケー
ジ形成工程を説明するための半導体パッケージの内部状
態図である。半導体パッケージ２０を形成するためには
、内部リード端子１とアイランド４からなる半導体パッ
ケージ用リードフレームに鋳型（図示せず）を装着し、
樹脂２１を矢印方向に封入する。このとき、樹脂２１の
流動によって内部リード端子１とボンディングパット５
との間に接続されたボンディングワイヤ３に負担はかか
るが、内部リード端子１の先端の形状、及び角度の効果
によりボンディングワイヤ１は拘束され、複数のボンデ
ィングワイヤ１同志の接触を抑えることができる。FIG. 2 is an internal state diagram of a semiconductor package for explaining the process of forming a semiconductor package of a semiconductor device according to this embodiment. In order to form the semiconductor package 20, a mold (not shown) is attached to a semiconductor package lead frame consisting of the internal lead terminals 1 and the island 4.
The resin 21 is sealed in the direction of the arrow. At this time, the internal lead terminal 1 and bonding pad 5 are connected to each other by the flow of the resin 21.
Although a load is placed on the bonding wires 3 connected between the internal lead terminals 1, the bonding wires 1 are restrained due to the shape and angle of the tips of the internal lead terminals 1, and contact between the plurality of bonding wires 1 can be suppressed. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体パッケージ用リー
ドフレームの各内部リード端子のアイランドに対向する
先端部にアイランドの広面に関し一定の角度を付け、か
つ先端部の形状はアイランドの平面に垂直な方向に関し
中央部を凹状にしたのて、半導体パッケージ形成工程に
おける樹脂封入の際に生じるボンディングワイヤ同志の
接触あるいは断線を防止し、半導体パッケージ形成にお
ける歩留りが向上できるという効果を有している。As explained above, the present invention provides that the tip of each internal lead terminal of a lead frame for a semiconductor package facing the island is angled at a certain angle with respect to the wide surface of the island, and the shape of the tip is perpendicular to the plane of the island. By making the central part concave, it is possible to prevent the bonding wires from coming into contact with each other or to break during resin encapsulation in the semiconductor package forming process, thereby improving the yield in forming the semiconductor package.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の一実施例の上面図、同図（ｂ）
はその横断面図、第２図は本発明の一実施例における半
導体パッケージ形成工程を説明するための内部状態図、
第３図（ａ）は従来の半導体パッケージ用リードフレー
ムの半導体パッケージ取付は後の上面図、同図（ｂ）は
その横断面図、第４図は従来の半導体パッケージ形成工
程を説明するための内部状態図である。 １．６・・・内部リード端子、２，７・・・半導体チッ
プ、３．８・・ホンディングワイヤ、４．９・・・アイ
ランド、５，１０・・ポンディングパッド、２０゜３０
・・・半導体パッケージ、２１．３１・・・樹脂。FIG. 1(a) is a top view of an embodiment of the present invention, and FIG. 1(b) is a top view of an embodiment of the present invention.
is a cross-sectional view thereof, and FIG. 2 is an internal state diagram for explaining the semiconductor package forming process in an embodiment of the present invention.
FIG. 3(a) is a top view of a conventional semiconductor package lead frame after the semiconductor package is attached, FIG. 3(b) is a cross-sectional view thereof, and FIG. 4 is a diagram for explaining the conventional semiconductor package forming process. It is an internal state diagram. 1.6...Internal lead terminal, 2,7...Semiconductor chip, 3.8...Honding wire, 4.9...Island, 5,10...Ponding pad, 20°30
...Semiconductor package, 21.31...Resin.

Claims (1)

【特許請求の範囲】 １、アイランドと複数の内部リード端子を含む半導体パ
ッケージ用リードフレームにおいて、前記内部リード端
子の前記アイランドに対向した先端部は前記アイランド
の平面に垂直な方向に関して中央部が凹状とされ、かつ
前記内部リード端子の先端部は前記アイランドの広面に
対し一定の角度が付けられていることを特徴とする半導
体パッケージ用リードフレーム。 ２、請求項１記載の半導体パッケージ用リードフレーム
を用いたことを特徴とする半導体パッケージ。[Scope of Claims] 1. In a lead frame for a semiconductor package including an island and a plurality of internal lead terminals, the tip of the internal lead terminal facing the island has a concave central portion in a direction perpendicular to the plane of the island. A lead frame for a semiconductor package, characterized in that the tip of the internal lead terminal is at a certain angle with respect to the wide surface of the island. 2. A semiconductor package using the lead frame for a semiconductor package according to claim 1.
JP27460090A 1990-10-12 1990-10-12 Semiconductor package lead frame Pending JPH04150065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27460090A JPH04150065A (en) 1990-10-12 1990-10-12 Semiconductor package lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27460090A JPH04150065A (en) 1990-10-12 1990-10-12 Semiconductor package lead frame

Publications (1)

Publication Number Publication Date
JPH04150065A true JPH04150065A (en) 1992-05-22

Family

ID=17543996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27460090A Pending JPH04150065A (en) 1990-10-12 1990-10-12 Semiconductor package lead frame

Country Status (1)

Country Link
JP (1) JPH04150065A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115910974A (en) * 2023-02-21 2023-04-04 厦门捷昕精密科技股份有限公司 High-density semiconductor integrated circuit lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115910974A (en) * 2023-02-21 2023-04-04 厦门捷昕精密科技股份有限公司 High-density semiconductor integrated circuit lead frame

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