CN115910974A - High-density semiconductor integrated circuit lead frame - Google Patents
High-density semiconductor integrated circuit lead frame Download PDFInfo
- Publication number
- CN115910974A CN115910974A CN202310140998.4A CN202310140998A CN115910974A CN 115910974 A CN115910974 A CN 115910974A CN 202310140998 A CN202310140998 A CN 202310140998A CN 115910974 A CN115910974 A CN 115910974A
- Authority
- CN
- China
- Prior art keywords
- lead
- pin
- frame
- lead wire
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a high-density semiconductor integrated circuit lead frame, which comprises a plurality of lead frame units, wherein the lead frame units are arranged in parallel along the longitudinal direction and the transverse direction; the lead frame unit includes frame even muscle, a plurality of pin, a plurality of lead wire tip, a plurality of lead wire base island, the outer end of a plurality of pin all is connected on frame even muscle, and the inner at a plurality of pin is installed respectively with a plurality of lead wire base islands to a plurality of lead wire tip, and a plurality of lead wire tip are relative and establish with a plurality of lead wire base islands, form the lead wire clearance between a plurality of lead wire tip and a plurality of lead wire base island. Aiming at the defect of insufficient packaging reliability caused by rebound of materials in the packaging process, the invention designs the compensation angles of 0-3 degrees and 0-2 degrees at the lead base island and the lead end part, thereby effectively improving the reliability of packaged products.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-density semiconductor integrated circuit lead frame.
Background
The integrated circuit lead frame, which is used as a chip carrier for an integrated circuit, is a key structural member for forming an electrical circuit, and plays a role of a bridge connected with an external wire. With the increase of packaging density, the packaging volume is reduced, the lead density is rapidly increased, and the market demands for lead frames are developing towards the directions of high precision, multiple pins and small spacing. As shown in fig. 1 to 3, in the prior art, there is a semiconductor micro discrete device lead frame 10, which includes a plurality of lead frame units 101, the lead frame units 101 include a frame connecting rib 1011, five lead pins 1012, three lead ends 1013, and a lead base island 1014, the three lead ends 1013 are connected to the lead base island 1014, and the product is made by punching a 0.1mm iron-nickel alloy material. Such a lead frame 10 has the following disadvantages:
1. the single-step distance B of the lead frame 10 in the length direction is 9.0mm, and the problem of insufficient density exists in the product structure;
2. the width of the lead frame unit 101 is 8.2mm, and the problem of insufficient density exists in the product structure.
3. Such a lead frame 10 can only realize a single chip package.
4. Such a lead frame 10 has no compensation angle design, and the package reliability is insufficient due to material bounce during the package wire bonding process.
5. Such a leadframe 10 enables only surface mount discrete semiconductor device packaging.
Aiming at the defects of the lead frame, the inventor develops a novel high-density semiconductor integrated circuit lead frame structure with multiple rows and small space between multiple chip carriers, aims to achieve the integrated circuit packaging of the product structure of the novel integrated circuit product with thinness, multiple rows, small space, multiple chip carriers and the high-density semiconductor integrated circuit lead frame, and the scheme is produced by the integrated circuit packaging structure.
Disclosure of Invention
The invention aims to provide a high-density semiconductor integrated circuit lead frame with high density and good packaging reliability.
In order to achieve the purpose, the technical solution of the invention is as follows:
the invention relates to a high-density semiconductor integrated circuit lead frame, which comprises a plurality of lead frame units, wherein the lead frame units are arranged in parallel along the longitudinal direction and the transverse direction; the lead frame unit includes that frame even muscle, a plurality of pin, a plurality of lead terminal portion, a plurality of lead wire base island, the outer end of a plurality of pin all connects on frame even muscle, and the inner at a plurality of pin is installed respectively with a plurality of lead wire base islands to a plurality of lead terminal portions, and a plurality of lead terminal portions and a plurality of lead wire base island are relative and establish, form the lead gap between a plurality of lead terminal portions and a plurality of lead wire base island.
The lead pins connected with the lead base islands are obliquely intersected with the frame connecting ribs to form a compensation angle of the lead base islands, and the compensation angle of the lead base islands is 0-2 degrees; the lead pin connected with the lead end is obliquely intersected with the frame connecting rib to form a compensation angle of the lead end, and the compensation angle of the lead end is 0-3 degrees.
The lead frame unit comprises five lead pins, three lead end parts and two lead base islands; the three lead end parts and the two lead base islands are respectively arranged at the inner ends of the five lead pins, and the three lead end parts are arranged opposite to the two lead base islands.
The width of each lead pin is 0.25mm; the lead gap between the end of the lead and the lead base island is 0.100mm; the center distance of the terminal pins between the terminal pins provided with the lead ends is 0.65mm.
The lead frame unit comprises a frame connecting rib and two groups of lead units; the two groups of lead units are arranged side by side and connected to the inner sides of the frame connecting ribs; the lead wire unit comprises five lead pins, three lead wire end parts and two lead wire base islands, wherein the outer ends of the three lead pins are connected to one side of the frame connecting rib, the inner ends of the three lead pins are connected with the lead wire end parts respectively, the outer ends of the other two lead pins are connected to the other side of the frame connecting rib, the inner ends of the two lead pins are connected with the lead wire base islands respectively, the lead wire end parts are opposite to the lead wire base islands and are arranged, and lead wire gaps are formed between the lead wire end parts and the lead wire base islands.
After the scheme is adopted, the invention has the following advantages:
1. the invention realizes the multi-chip semiconductor integrated circuit packaging by the original single-chip semiconductor discrete device packaging, simultaneously reduces the single step pitch of the product and the unit width of the product, reduces the width of the lead pins, reduces the center distance of the outer lead pins of the product, achieves the aim of high-density packaging, realizes more product quantity and more product pin quantity in the unit area with the same material, improves the utilization rate of the product material and reduces the manufacturing cost of the product.
2. Aiming at the defect of insufficient packaging reliability caused by rebound of materials in the packaging process, compensation angles of 0-3 degrees and 0-2 degrees are designed at the lead base island and the lead end part, so that the reliability of a packaged product is effectively improved.
The invention is further described with reference to the following figures and specific embodiments.
Drawings
FIG. 1 is a front view of a conventional semiconductor micro discrete device lead frame;
fig. 2 is a front view of a lead frame unit in a conventional semiconductor micro discrete device lead frame;
FIG. 3 is a side view of a lead frame unit in a conventional semiconductor micro discrete device lead frame;
FIG. 4 is a front view of the first embodiment of the present invention;
fig. 5 is a front view of a lead frame unit according to a first embodiment of the present invention;
FIG. 6 is a side view of a lead frame unit according to a first embodiment of the present invention;
FIG. 7 is a front view of a second embodiment of the present invention;
fig. 8 is a front view of a lead frame unit according to a second embodiment of the present invention;
fig. 9 is a side view of a lead frame unit according to a second embodiment of the present invention;
fig. 10 is a schematic diagram of a bonding wire for semiconductor package according to the present invention.
Description of the preferred embodiment
As shown in fig. 4 to 6, a lead frame for a high-density semiconductor integrated circuit according to a first embodiment of the present invention includes 360 lead frame units 1, and the 360 lead frame units 1 are arranged in parallel in the longitudinal and transverse directions and are arranged in 60 × 6 rows.
The lead frame unit 1 comprises a frame connecting rib 11 and two groups of lead units 10; the two groups of lead units 10 are arranged side by side and connected to the inner side of the frame connecting rib 11; the lead unit 10 includes five lead pins 12, three lead end portions 13, and two lead pads 14, wherein the outer ends of the three lead pins 12 are connected to one side of the frame connecting rib 11, the inner ends of the three lead pins 12 are connected to the lead end portions 13, respectively, the outer ends of the other two lead pins 12 are connected to the other side of the frame connecting rib 11, the inner ends of the two lead pins 12 are connected to the lead pads 14, the lead end portions 13 are disposed opposite to the lead pads 14, and a lead gap A1 is formed between the lead end portions 13 and the lead pads 14.
The width of the terminal pin 12 is 0.25mm; a lead gap A1 between the lead end 13 and the lead base island 14 is 0.100mm; the pin center distance A2 between the pins 12 to which the lead end portions 13 are attached is 0.65mm.
The pin 12 connected with the lead base island 14 is obliquely intersected with the frame connecting rib 11 to form a compensation angle a1 of the lead base island 14, and the compensation angle a1 of the lead base island 14 is 0-2 degrees; the terminal pin 12 connected with the terminal portion 13 obliquely intersects with the frame connecting rib 11 to form a compensation angle a2 of the terminal portion 13, and the compensation angle a2 of the terminal portion 13 is 0-3 degrees.
In this embodiment, there are 360 lead frame units 1 and 1800 leadfingers 12 in one lead frame.
The working principle of the invention is as follows:
1. the invention relates to a lead frame structure of a multi-row, small-spacing, multi-chip carrier and high-density integrated circuit, which is a frame body made of a high-strength iron-nickel alloy through stamping, wherein a lead frame unit 1 comprises a lead base island 14 for placing a plurality of chips and a plurality of lead pins 12 capable of realizing connection with an external circuit.
2. The X-direction single step B is reduced from 9.0mm to 7.2mm under the condition of the same material width.
3. The width of the terminal pin 12 is reduced from 0.4mm to 0.25mm.
4. The product lead gap A1 is reduced from 0.18mm to 0.100mm.
5. The pin center distance A2 of the product pin 12 is reduced from 1.9mm to 0.65mm.
6. In the packaging process of the product, due to the rebound of materials, the packaging reliability is insufficient, so that the compensation angles of 0-3 degrees and 0-2 degrees are realized on the lead base island 14 and the lead end part 13, and the reliability of the packaged product is effectively improved.
7. The number of the products is increased from 288 to 360 in the range of 216mm strip length, and the number of the lead pins of the products is increased from 864 to 1800 and 2160.
As shown in fig. 10, the present invention is mounted on a semiconductor package bonding process base 2, a semiconductor package bonding process pressing plate 3 is pressed on the top surface of the present invention, a chip is attached to a lead base 14, and bonding wires are bonded to lead terminals 13.
Referring to fig. 7 to 9, a second embodiment of a high-density semiconductor integrated circuit lead frame according to the present invention is shown, in which a lead frame 2A includes 360 lead frame units 1a,360 lead frame units 1 are arranged in parallel in longitudinal and lateral directions and arranged in 60 × 6 rows.
The lead frame unit 1A comprises a frame connecting rib 11A and two groups of lead units 10A; the two groups of lead units 10A are arranged side by side and connected to the inner side of the frame connecting rib 11A; the lead unit 10A includes six lead pins 12, four lead end portions 13A, and two lead islands 14A, wherein the outer ends of the three lead pins 13A are connected to one side (upper portion) of the frame connecting rib 11A, the inner ends of the three lead pins 13A are respectively connected to the two lead end portions 13A and one lead island 14A, and the two lead end portions 13A and the one lead island 14A are sequentially disposed; the outer ends of the three lead pins 13A are connected to the other side (lower part) of the frame connecting rib 11A, respectively, the inner ends of the three lead pins 13A are connected to one lead pad 14A and two lead end portions 13A, one lead pad 14A is disposed between the two lead end portions 13A, the two lead end portions 13A on the right side are disposed to face the two lead pad portions 14A, and a lead gap B1 is formed between the lead end portions 13A and the lead pad portions 14A.
The width of the lead pin 12A is 0.25mm; a lead gap B1 between the lead end 13A and the lead base island 14A is 0.100mm; the pin center distance B2 between the pins 12A to which the lead end portions 13A are attached is 0.65mm.
The lead pin 12A connected with the lead base island 14A is obliquely intersected with the frame connecting rib 11A to form a compensation angle b1 of the lead base island 14, and the compensation angle b1 of the lead base island 14 is 0-2 degrees; the terminal pin 12A connected with the terminal portion 13A is obliquely intersected with the frame connecting rib 11A to form a compensation angle b2 of the terminal portion 13A, and the compensation angle b2 of the terminal portion 13A is 0-3 degrees.
In the present embodiment, there are 360 lead frame units 1A and 2160 lead pins 12A in one lead frame.
The above description is only a preferred embodiment of the present invention, and therefore should not be taken as limiting the scope of the invention, which is defined by the appended claims and their equivalents and modifications within the scope of the description.
Claims (5)
1. A high-density semiconductor integrated circuit lead frame characterized in that: the multi-lead frame unit comprises a plurality of lead frame units which are arranged in parallel along the longitudinal direction and the transverse direction; the lead frame unit includes that frame even muscle, a plurality of pin, a plurality of lead terminal portion, a plurality of lead wire base island, the outer end of a plurality of pin all connects on frame even muscle, and the inner at a plurality of pin is installed respectively with a plurality of lead wire base islands to a plurality of lead terminal portions, and a plurality of lead terminal portions and a plurality of lead wire base island are relative and establish, form the lead gap between a plurality of lead terminal portions and a plurality of lead wire base island.
2. The high-density semiconductor integrated circuit lead frame according to claim 1, wherein: the lead pin connected with the lead base island is obliquely intersected with the frame connecting rib to form a compensation angle of the lead base island, and the compensation angle of the lead base island is 0-2 degrees; the lead pin connected with the lead end is obliquely intersected with the frame connecting rib to form a compensation angle of the lead end, and the compensation angle of the lead end is 0-3 degrees.
3. The high-density semiconductor integrated circuit lead frame according to claim 1, wherein: the lead frame unit comprises five lead pins, three lead end parts and two lead base islands; the three lead end parts and the two lead base islands are respectively arranged at the inner ends of the five lead pins, and the three lead end parts are arranged opposite to the two lead base islands.
4. The high-density semiconductor integrated circuit lead frame according to claim 1, wherein: the width of each lead pin is 0.25mm; the lead gap between the end of the lead and the lead base island is 0.100mm; the center distance of the terminal pins between the terminal pins provided with the terminal parts of the leads is 0.65mm.
5. The high-density semiconductor integrated circuit lead frame according to claim 1, wherein: the lead frame unit comprises a frame connecting rib and two groups of lead units; the two groups of lead units are arranged side by side and connected to the inner side of the frame connecting rib; the lead wire unit includes five pin, three pin tip, two lead wire bases, and wherein, the outer end of three pin is connected in one side of frame even muscle and the inner of this three pin is connected with pin tip respectively, and the outer end of two pin is connected respectively in the opposite side of frame even muscle and the inner of these two pin is connected with the lead wire base in addition, and pin tip is relative and establishes with the lead wire base, forms the lead wire clearance between pin tip and lead wire base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310140998.4A CN115910974B (en) | 2023-02-21 | 2023-02-21 | High density semiconductor integrated circuit lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310140998.4A CN115910974B (en) | 2023-02-21 | 2023-02-21 | High density semiconductor integrated circuit lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115910974A true CN115910974A (en) | 2023-04-04 |
| CN115910974B CN115910974B (en) | 2023-05-30 |
Family
ID=85742785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310140998.4A Active CN115910974B (en) | 2023-02-21 | 2023-02-21 | High density semiconductor integrated circuit lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115910974B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02298057A (en) * | 1989-05-12 | 1990-12-10 | Sanyo Electric Co Ltd | Lead frame and its processing; manufacture of semiconductor device |
| JPH04150065A (en) * | 1990-10-12 | 1992-05-22 | Nec Corp | Semiconductor package lead frame |
| JP2007294884A (en) * | 2006-03-29 | 2007-11-08 | Sanyo Electric Co Ltd | Semiconductor device |
| CN202996822U (en) * | 2012-12-05 | 2013-06-12 | 四川金湾电子有限责任公司 | Lead frame |
| CN203826370U (en) * | 2014-05-07 | 2014-09-10 | 宁波华龙电子股份有限公司 | Lead framework for small power device |
| CN204011409U (en) * | 2014-08-25 | 2014-12-10 | 铜陵丰山三佳微电子有限公司 | Improve the SOP 8L 12R lead frame of stock utilization |
| CN105185759A (en) * | 2015-10-26 | 2015-12-23 | 武汉光迅科技股份有限公司 | Butterfly optical device and pin shaping device thereof |
| CN110600450A (en) * | 2019-10-25 | 2019-12-20 | 山东晶导微电子股份有限公司 | Lead frame for arranging chip, packaging body and power supply module |
| CN210575936U (en) * | 2019-12-06 | 2020-05-19 | 深圳市诚芯微科技有限公司 | Metal lead frame and semiconductor packaging structure |
| CN213692036U (en) * | 2020-11-18 | 2021-07-13 | 宁波德洲精密电子有限公司 | High-density ten-pin integrated circuit lead frame |
| CN213692035U (en) * | 2020-11-18 | 2021-07-13 | 宁波德洲精密电子有限公司 | Intensive integrated circuit lead frame |
| CN218482238U (en) * | 2022-11-03 | 2023-02-14 | 深圳市信展通电子股份有限公司 | SOT23 lead frame structure |
-
2023
- 2023-02-21 CN CN202310140998.4A patent/CN115910974B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02298057A (en) * | 1989-05-12 | 1990-12-10 | Sanyo Electric Co Ltd | Lead frame and its processing; manufacture of semiconductor device |
| JPH04150065A (en) * | 1990-10-12 | 1992-05-22 | Nec Corp | Semiconductor package lead frame |
| JP2007294884A (en) * | 2006-03-29 | 2007-11-08 | Sanyo Electric Co Ltd | Semiconductor device |
| CN202996822U (en) * | 2012-12-05 | 2013-06-12 | 四川金湾电子有限责任公司 | Lead frame |
| CN203826370U (en) * | 2014-05-07 | 2014-09-10 | 宁波华龙电子股份有限公司 | Lead framework for small power device |
| CN204011409U (en) * | 2014-08-25 | 2014-12-10 | 铜陵丰山三佳微电子有限公司 | Improve the SOP 8L 12R lead frame of stock utilization |
| CN105185759A (en) * | 2015-10-26 | 2015-12-23 | 武汉光迅科技股份有限公司 | Butterfly optical device and pin shaping device thereof |
| CN110600450A (en) * | 2019-10-25 | 2019-12-20 | 山东晶导微电子股份有限公司 | Lead frame for arranging chip, packaging body and power supply module |
| CN210575936U (en) * | 2019-12-06 | 2020-05-19 | 深圳市诚芯微科技有限公司 | Metal lead frame and semiconductor packaging structure |
| CN213692036U (en) * | 2020-11-18 | 2021-07-13 | 宁波德洲精密电子有限公司 | High-density ten-pin integrated circuit lead frame |
| CN213692035U (en) * | 2020-11-18 | 2021-07-13 | 宁波德洲精密电子有限公司 | Intensive integrated circuit lead frame |
| CN218482238U (en) * | 2022-11-03 | 2023-02-14 | 深圳市信展通电子股份有限公司 | SOT23 lead frame structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115910974B (en) | 2023-05-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6710430B2 (en) | Resin-encapsulated semiconductor device and method for manufacturing the same | |
| US20020121670A1 (en) | Lead frame | |
| USRE41510E1 (en) | Lead frame | |
| US7008824B2 (en) | Method of fabricating mounted multiple semiconductor dies in a package | |
| US9087827B2 (en) | Mixed wire semiconductor lead frame package | |
| JPH0546045U (en) | Semiconductor package | |
| JP3046024B1 (en) | Lead frame and method of manufacturing resin-encapsulated semiconductor device using the same | |
| US20110084374A1 (en) | Semiconductor package with sectioned bonding wire scheme | |
| US20020149090A1 (en) | Lead frame and semiconductor package | |
| JP3072291B1 (en) | Lead frame, resin-encapsulated semiconductor device using the same and method of manufacturing the same | |
| JP4547086B2 (en) | Semiconductor device | |
| US5808872A (en) | Semiconductor package and method of mounting the same on circuit board | |
| JPH06132456A (en) | Insulating lead frame for semiconductor package | |
| KR20040108582A (en) | Seniconductor device and method for fabricating the same | |
| CN115910974B (en) | High density semiconductor integrated circuit lead frame | |
| JP2001024133A (en) | Lead frame, resin sealed semiconductor device employing it and manufacture thereof | |
| CN115995440A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| US20200321228A1 (en) | Method of manufacturing a lead frame, method of manufacturing an electronic apparatus, and electronic apparatus | |
| US20200168531A1 (en) | Integrated circuit package including inward bent leads | |
| KR0119757Y1 (en) | Semiconductor package | |
| KR100340862B1 (en) | Stack package and its manufacturing method | |
| CN218160365U (en) | Packaging structure | |
| JP4651218B2 (en) | Manufacturing method of semiconductor device | |
| JPS6242552A (en) | Semiconductor device | |
| US20090079045A1 (en) | Package structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |