JPH01238128A - Resin seal type semiconductor device - Google Patents
Resin seal type semiconductor deviceInfo
- Publication number
- JPH01238128A JPH01238128A JP63066446A JP6644688A JPH01238128A JP H01238128 A JPH01238128 A JP H01238128A JP 63066446 A JP63066446 A JP 63066446A JP 6644688 A JP6644688 A JP 6644688A JP H01238128 A JPH01238128 A JP H01238128A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- inner leads
- semiconductor
- lead
- electrode pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 229920005989 resin Polymers 0.000 title claims abstract description 11
- 239000011347 resin Substances 0.000 title claims abstract description 11
- 239000000853 adhesive Substances 0.000 claims abstract description 9
- 230000001070 adhesive effect Effects 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 claims abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 210000001331 nose Anatomy 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000725 suspension Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000010626 work up procedure Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に関し、特に半導体素子
のマウント構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a mounting structure for a semiconductor element.
従来、この種の半導体装置は、第３図の平面図（＆）お
よびそのｘ−ｘ’線断面図（ｂ）に示すように、半導体
素子３１をリードフレームの吊りリード３２に連なる素
子搭載部３３にＡｇペーストまたはＡｎ−５ｉ共品合金
法等により固着し、金線３４により半導体素子３１の電
極３５と外部へ導出するリード３６の内部リード３６Ａ
とをワイヤポンディングにより結線し、エポキシ樹脂３
７等により封止した構造を有している。Conventionally, in this type of semiconductor device, as shown in the plan view (&) of FIG. The inner lead 36A of the lead 36 is fixed to the electrode 33 using Ag paste or the An-5i alloy method, etc., and is led to the electrode 35 of the semiconductor element 31 and the outside using the gold wire 34.
are connected by wire bonding, and the epoxy resin 3
It has a structure sealed by 7 etc.
上述した従来の樹脂封止型半導体装置は、半導体素子の
大きさに応じた素子搭載部を有するリードフレームを使
用しないと、ワイヤポンディング工程や樹脂封止工程で
発生するポンディングワイヤのだれや変形によって、素
子搭載部とポンディングワイヤとのショート不良を起こ
すという欠点があった。このため種々の半導体素子の大
きさに適合したリードフレームが必要となり、設計−製
作のコストアップを生じていた。The above-mentioned conventional resin-sealed semiconductor devices are prone to sagging of the bonding wires that occur during the wire bonding process and the resin encapsulation process unless a lead frame is used that has an element mounting part that corresponds to the size of the semiconductor element. There was a drawback that the deformation caused a short circuit between the element mounting portion and the bonding wire. For this reason, lead frames that are compatible with the sizes of various semiconductor elements are required, resulting in an increase in design and manufacturing costs.
また、特にＳ ＯＰ （Ｓｍａｌｌ ０ｕｔｌｉｎｅ
Ｐａｃｋａｇｅ）。Also, especially S OP (Small 0utline
Package).
Ｑ Ｆ Ｐ （Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
等の表面実装パッケージの場合は、プリント基板実装時
に赤外線リフローソルダリングやペイパー・フエイズφ
ソルダリング等、バー２ケージ全体が高温に加熱される
実装方法を用いるが、パッケージ内部の素子搭載部はか
なり大面積の板であるため、１４止樹脂との熱膨張の差
が大きく、素子搭載部端部に樹脂クラックが生じ、その
ため半導体装置の耐湿性が劣化し不良を発生するという
問題点があった。Q F P (Quad Flat Package)
For surface mount packages such as
A mounting method such as soldering is used in which the entire bar 2 cage is heated to a high temperature, but since the element mounting part inside the package is a fairly large plate, there is a large difference in thermal expansion from the 14-stop resin, making it difficult to mount the element. There is a problem in that resin cracks occur at the end portions of the semiconductor device, which deteriorates the moisture resistance of the semiconductor device and causes defects.
上記の問題点をさけるために、素子ＮＳＳ郡部廃＋ｉ−
，Ｌ 、直接に内部リード先端部に接着剤で固着するこ
とが考えられる。しかし、゛ト導体素子を正しく位置ぎ
めすることは難しく、また半導体素子を支える内部リー
ドの面積が小さいので、電極バットにワイヤポンディン
グしたときの押圧が半導体素子に不適切に印加し、半導
体素子の接点等からクラックが生ずることがあり、実用
されていない。In order to avoid the above problems, the element NSS
, L may be directly fixed to the tip of the internal lead with adhesive. However, it is difficult to position the conductive element correctly, and the area of the internal lead that supports the semiconductor element is small, so the pressure when wire bonding to the electrode butt may be inappropriately applied to the semiconductor element, causing the semiconductor element to Cracks may occur from the contacts, etc., so it is not put into practical use.
本発明の目的は、上記の欠点を除去し、大きさの異なる
半導体装子に対し、リードフレームとして共用のものが
使用できるように素子搭載部を用いず、しかも半導体装
ｆ−のマウテイング、ワイヤポンディングの点で信頼性
のある半導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks, and to enable the use of a common lead frame for semiconductor devices of different sizes, without using an element mounting section, and in addition, to eliminate the need for mounting and wiring of semiconductor devices. The object of the present invention is to provide a semiconductor device that is reliable in terms of bonding.
本発明の半導体装置は、樹脂封止部内の目合せパターン
を有する内部リードの先端部上に。The semiconductor device of the present invention has an alignment pattern on the tip of the internal lead within the resin sealing portion.
゛ト導体素子が絶縁性接着剤により固着され、前記半導
体素子の各電極パッドが相対向する内部リードの半一導
体素子固着位置の上方投影領域内に位置しているように
したものである。A conductor element is fixed with an insulating adhesive, and each electrode pad of the semiconductor element is located in an upper projection area of the semiconductor element fixing position of the opposing inner lead.
本発明では、リードフレームは、従来の素子搭載部をも
たず、半導体素子は直接内部り“−ドの先端部に取付け
られるが、その際、内部リードは取付は位置を示す目合
せパターンを有するノテ、このパターンを利用し、さら
に半導体素子の電極パッドが半導体素子を内部リードに
固着する部位の上方投影領域内に来るように半導体素子
を配置して、内部リードに接着しである。したがってワ
イヤポンディングの際に、電極パッドに＃撃抑圧が加わ
るが、半導体素子は内部リードによりＦ方から止しく支
えられるので、半導体素子の接着部からクラックが発生
することがない。In the present invention, the lead frame does not have a conventional element mounting part, and the semiconductor element is directly attached to the tip of the internal lead. Using this pattern, the semiconductor element is further placed so that the electrode pad of the semiconductor element is within the upper projection area of the part where the semiconductor element is fixed to the inner lead, and the semiconductor element is bonded to the inner lead. During wire bonding, # impact suppression is applied to the electrode pad, but since the semiconductor element is firmly supported from the F direction by the internal leads, no cracks will occur from the bonded portion of the semiconductor element.
以下、図面を参照して本発明の実施例につき説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）は、未発【ｇｌの第１の実施例の平面図、
第１図（ｂ）は第１図（ａ）のｘ−ｘ’線断面図である
。外部導出リード１６に連なる内部リード１６Ａがお互
いに接触しない程度に中心部迄延長されていて、その先
端部に半導体素子１１が絶縁性接着剤１８により固着さ
れている。FIG. 1(a) is a plan view of the first embodiment of the unexploded [GL].
FIG. 1(b) is a sectional view taken along line xx' in FIG. 1(a). Internal leads 16A connected to external leads 16 are extended to the center to such an extent that they do not touch each other, and the semiconductor element 11 is fixed to the tips of the internal leads 16A with an insulating adhesive 18.
内部リード１６Ａの先端には、半導体素子１１の接着面
と反対側に、半導体素子１１より１法がやや大きく、半
導体素子１１の周縁部に該当する枠状のリード支持片が
目合せパターン１９として固着されている。この［１合
せ）くターン１９は、半導体素子１１の固着の際のし１
合せになるばかりでなく、隣接する内部リート１６Ａの
先端の間隔を正しく維持するのにも役立っている。半導
体素子１１は、その電極パッド１５が、内部リード１６
Ａの半導体素子固着部位上方の投影領域内に位置するよ
うに、配置されているから、電極パッド１５と内部リー
ド１６Ａとを金＆！１４でワイヤポンディングにより接
続するときに、半導体素子１１に衝撃が４えたれても、
半導体素子１１は内部リード１６Ａによって正しく支持
され、半導体素子１１にクラックが生ずることはない、
なお、１７はエポキシ樹脂で、１２はリードフレームの
吊りリードである。吊リード１２は、樹脂封止工程まで
は作業上必要であるが、完成品としては特に機能はもっ
ていない。At the tip of the internal lead 16A, on the side opposite to the bonding surface of the semiconductor element 11, a frame-shaped lead support piece is provided as an alignment pattern 19, which is slightly larger in one dimension than the semiconductor element 11 and corresponds to the peripheral edge of the semiconductor element 11. It is fixed. This [1 alignment] turn 19 is a
Not only do they fit together, but they also serve to maintain the proper spacing between the tips of adjacent internal reams 16A. The semiconductor element 11 has an electrode pad 15 connected to an internal lead 16.
Since the electrode pads 15 and internal leads 16A are arranged so as to be located within the projection area above the semiconductor element fixing area of Even if a shock is applied to the semiconductor element 11 when connecting by wire bonding at 14,
The semiconductor element 11 is correctly supported by the internal leads 16A, and no cracks occur in the semiconductor element 11.
Note that 17 is an epoxy resin, and 12 is a suspension lead of the lead frame. Although the suspension lead 12 is necessary for the work up to the resin sealing process, it has no particular function as a finished product.
次に、第２実施例につき説明する。この実施例は内部リ
ード２６Ａに０．５鵬脂〜１．０腸量程度の一定間隔に
エツチングあるいはプレスによって、図示のように半導
体素子形状に合わせてきざみをつけ目合せパターン２９
としたものである。半導体素子２１の寸法が変った場合
に、この１．１合せパターン２９は位置確認表示として
きわめて有効である。半導体素子２１を絶縁性接着剤２
８で内部リード２６Ａに固着し、金線２４で、電極パッ
ド２５と内部リード２６Ａとの間をワイヤポンディング
により結合した後、エポキシ樹脂２７で封止することは
第１実施例と同一である。Next, a second embodiment will be explained. In this embodiment, the internal leads 26A are etched or pressed at regular intervals of about 0.5 to 1.0 mm to match the shape of the semiconductor element as shown in the figure, and an alignment pattern 29 is formed.
That is. When the dimensions of the semiconductor element 21 change, this 1.1 alignment pattern 29 is extremely effective as a position confirmation display. Semiconductor element 21 is bonded with insulating adhesive 2
8, the electrode pad 25 and the internal lead 26A are bonded by wire bonding using the gold wire 24, and then sealed with the epoxy resin 27, which is the same as in the first embodiment. .
さらにこの実施例では、吊りリード２２もワイヤポンデ
ィングするようにして有効ピンとして使用している。Further, in this embodiment, the suspension lead 22 is also used as an effective pin by wire bonding.
以上説明したように本発明は、樹脂刃止部内の内部リー
ド上に絶縁性接着剤を介して半導体素子上の電極パッド
が内部リードの固着部位の上方投影領域内に存在するよ
うに固着し、内部リード上にリード支持片やハーフエッ
チあるいはプレスパターン等により目合せパターンを形
成するようにしたものである。As explained above, the present invention fixes the electrode pads on the semiconductor element onto the internal leads in the resin blade retaining part via an insulating adhesive so that they are present in the upper projection area of the fixed part of the internal leads, An alignment pattern is formed on the internal leads using a lead support piece, a half-etch pattern, a press pattern, or the like.
本発明では従来の素子搭載部を用いないので、半導体素
子の大きさが異なっても、共通のリードフレームを用い
ることができる利点がある。さらに、従来は素子搭載部
の大きい面積の金属板と樹脂との高温における８膨張差
が大きいので、す７０−ンルダリングのようにパッケー
ジ全体を高温に加熱する実装方法では、従来品で樹脂ク
ラックが生ずることがあったが、本発明品ではこのよう
なことがない。Since the present invention does not use a conventional device mounting section, there is an advantage that a common lead frame can be used even if the semiconductor devices have different sizes. Furthermore, since there is a large expansion difference at high temperatures between the large-area metal plate of the element mounting area and the resin, conventional mounting methods that heat the entire package to a high temperature, such as 70-n-rudaring, can cause resin cracks in conventional products. However, this does not occur with the product of the present invention.
内部リードに半導体素子を固着する作業は、内部リード
に設けた目合せパターンを利用することで容易に行なう
ことができる。また電極パッドの位置が内部リードの固
着位置の上方投影領域内にあるので、ポンディング時（
７）押圧ニヨる衝撃があっても、半導体素子のクラック
発生を低減できる。The work of fixing the semiconductor element to the internal leads can be easily carried out by using the alignment pattern provided on the internal leads. In addition, since the electrode pad is located within the upper projection area of the internal lead fixing position, during bonding (
7) Even if there is a pressure impact, the occurrence of cracks in the semiconductor element can be reduced.
第１図、第２図は本発明の第１実施例、第２実施例のそ
れぞれの（ａ）平面図・（ｂ）断面図、第３図は従来例
の（ａ）平面図・（ｂ）断面図である。
１１．２１・・・半導体素子。
１４．２４・・・金線。
１５．２５・・・電極パッド、
１６Ａ、２６Ａ・・・内部リード。
１８．２８・・・絶縁性接着剤。
１９・・・目合せパターン（リード支持片）、２９・・
・目合せパターン。
特許出願人 日本電気株式会社
代理人 弁理士 内 原 晋第１図
木巳１１佃へ九−會ｊ
第２図
フ１
第３図1 and 2 are (a) a plan view and (b) a sectional view of the first embodiment and the second embodiment of the present invention, respectively, and FIG. 3 is a (a) plan view and (b) a sectional view of the conventional example. ) is a sectional view. 11.21...Semiconductor element. 14.24...Gold wire. 15.25... Electrode pad, 16A, 26A... Internal lead. 18.28...Insulating adhesive. 19... Alignment pattern (lead support piece), 29...
- Alignment pattern. Patent Applicant NEC Corporation Representative Patent Attorney Susumu Uchihara Figure 1Kimi 11 Tsukudahe9-kai Figure 2 F1 Figure 3
Claims (1)
先端部上に、半導体素子が絶縁性接着剤により固着され
、前記半導体素子の各電極パッドが相対向する内部リー
ドの半導体素子固着位置の上方投影領域内に位置してい
ることを特徴とする樹脂封止型半導体装置。A semiconductor element is fixed with an insulating adhesive onto the tip of an internal lead having an alignment pattern in the resin sealing part, and an upward projection of the semiconductor element fixed position of the inner lead where each electrode pad of the semiconductor element faces each other. A resin-sealed semiconductor device characterized by being located within a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066446A JP2602278B2 (en) | 1988-03-18 | 1988-03-18 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066446A JP2602278B2 (en) | 1988-03-18 | 1988-03-18 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01238128A true JPH01238128A (en) | 1989-09-22 |
| JP2602278B2 JP2602278B2 (en) | 1997-04-23 |
Family
ID=13316009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63066446A Expired - Lifetime JP2602278B2 (en) | 1988-03-18 | 1988-03-18 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2602278B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04324662A (en) * | 1991-04-03 | 1992-11-13 | Samsung Electron Co Ltd | Semiconductor package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS5684360U (en) * | 1979-11-29 | 1981-07-07 | ||
| JPS61240U (en) * | 1984-06-06 | 1986-01-06 | 日本電気株式会社 | semiconductor equipment |
-
1988
- 1988-03-18 JP JP63066446A patent/JP2602278B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS5684360U (en) * | 1979-11-29 | 1981-07-07 | ||
| JPS61240U (en) * | 1984-06-06 | 1986-01-06 | 日本電気株式会社 | semiconductor equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04324662A (en) * | 1991-04-03 | 1992-11-13 | Samsung Electron Co Ltd | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2602278B2 (en) | 1997-04-23 |
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