JP2602278B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2602278B2 JP2602278B2 JP63066446A JP6644688A JP2602278B2 JP 2602278 B2 JP2602278 B2 JP 2602278B2 JP 63066446 A JP63066446 A JP 63066446A JP 6644688 A JP6644688 A JP 6644688A JP 2602278 B2 JP2602278 B2 JP 2602278B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- inner leads
- semiconductor
- electrode pads
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関し、特に半導体素
子のマウント構造に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly, to a semiconductor element mounting structure.
従来、この種の半導体装置は、第３図の平面図（ａ）
およびそのＸ−Ｘ′線断面図（ｂ）に示すように、半導
体素子31のリードフレームの吊りリード32に連なる素子
搭載部33にAgペーストまたはAn−Si共晶合金法等により
固着し、金線34により半導体素子31の電極35と外部へ導
出するリード36の内部リード36Aとをワイヤボンディン
グにより結線し、エポキシ樹脂37等により封止した構造
を有している。Conventionally, this type of semiconductor device is shown in a plan view of FIG.
Then, as shown in the cross-sectional view (b) of FIG. The electrode 35 of the semiconductor element 31 and the internal lead 36A of the lead 36 leading out to the outside are connected by wire 34 by wire bonding, and are sealed with an epoxy resin 37 or the like.
上述した従来の、樹脂封止型半導体装置は、半導体素
子の大きさに応じた素子搭載部を有するリードフレーム
を使用しないと、ワイヤボンディング工程や樹脂封止工
程で発生するボンディングワイヤのたれや変形によっ
て、素子搭載部とボンディングワイヤとのショート不良
を起こすという欠点があった。このため種々の半導体素
子の大きさに適合したリードフレームが必要となり、設
計・製作のコストアップを生じていた。The conventional resin-encapsulated semiconductor device described above requires the use of a lead frame having an element mounting portion corresponding to the size of a semiconductor element, or the sagging or deformation of bonding wires generated in a wire bonding step or a resin encapsulation step. As a result, there is a drawback that a short circuit failure occurs between the element mounting portion and the bonding wire. For this reason, lead frames suitable for the sizes of various semiconductor elements are required, resulting in an increase in design and manufacturing costs.
また、特にSOP（Small Outline Package）,QFP（Quad
Flat Package）等の表面実装パッケージの場合は、プ
リント基板実装時に赤外線リフローソルダリングやベイ
パー・フェイズ・ソルダリング等、パッケージ全体が高
温に加熱される実装方法を用いるが、パッケージ内部の
素子搭載部はかなりの大面積の板であるため、封止樹脂
との熱膨張の差が大きく、素子搭載部端部に樹脂クラッ
クが生じ、そのため半導体装置の耐湿性が劣化し不良を
発生するという問題点があった。In particular, SOP (Small Outline Package), QFP (Quad
In the case of a surface mount package such as a flat package, a mounting method is used in which the entire package is heated to a high temperature, such as infrared reflow soldering or vapor phase soldering when mounting the printed circuit board. Since the board has a considerably large area, the difference in thermal expansion from the sealing resin is large, and a resin crack occurs at the end of the element mounting portion, which deteriorates the moisture resistance of the semiconductor device and causes a problem. there were.
上記の問題点をさけるために、素子搭載部を廃止し、
直接に内部リード先端部に接着剤で固着することが考え
られる。しかし、半導体素子を正しく位置ぎめすること
は難しく、また半導体素子を支える内部リードの面積が
小さいので、電極パッドにワイヤボンディングしたとき
の押圧が半導体素子に不適切に印加し、半導体素子の接
点等からクラックが生ずることがあり、実用されていな
い。In order to avoid the above problems, the element mounting part was abolished,
It is conceivable that the adhesive is directly fixed to the tip of the internal lead with an adhesive. However, it is difficult to correctly position the semiconductor element, and since the area of the internal lead supporting the semiconductor element is small, the pressure when wire bonding to the electrode pad is improperly applied to the semiconductor element, and the contact of the semiconductor element, etc. Cracks may occur from the surface and are not practically used.
本発明の目的は、上記の欠点を除去し、大きさの異な
る半導体素子に対し、リードフレームとしての共用のも
のが使用できるように素子搭載部を用いず、しかも半導
体素子のマウンティング、ワイヤボンディングの点で信
頼性のある半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned disadvantages, and to use a device mounting portion so that a semiconductor device having a different size can be used as a common lead frame. It is an object of the present invention to provide a semiconductor device which is reliable in that respect.
本発明の半導体装置は、目合わせパターンを用いて樹
脂封止部内の内部リードの先端部上に、半導体素子が絶
縁性接着剤により固着され、前記半導体素子のボンディ
ング接続されるべきすべての電極パッドの直下に前記内
部リードを夫々位置せしめ、すべてのワイヤボンディン
グが前記内部リードの直上にて行われるようにしたもの
である。In the semiconductor device of the present invention, the semiconductor element is fixed on the tip of the internal lead in the resin sealing portion using an alignment pattern with an insulating adhesive, and all the electrode pads to be connected to the semiconductor element by bonding are provided. , The internal leads are respectively positioned immediately below the internal leads, and all wire bonding is performed immediately above the internal leads.
本発明では、リードフレームは、従来の素子搭載部を
もたず、半導体素子は直接内部リードの先端部に取付け
られるが、その際、内部リードは取付け位置を示す目合
せパターンを有するので、このパターンを利用し、さら
に半導体素子のワイヤボンディングするすべての電極パ
ッドが半導体素子を内部リードに固着する部位の上方投
影領域内に来るように半導体素子が配置して、内部リー
ドに装着してある。したがってワイヤボンディングの際
に、電極パッドに衝撃押圧が加わるが、半導体素子は内
部リードにより下方から正しく支えられるので、半導体
素子の接着部からクラックが発生することがない。In the present invention, the lead frame does not have a conventional element mounting portion, and the semiconductor element is directly mounted on the tip of the internal lead. At this time, the internal lead has a registration pattern indicating the mounting position. The semiconductor element is mounted on the internal lead by using a pattern such that all the electrode pads to be wire-bonded of the semiconductor element are located within an upper projected area of a portion where the semiconductor element is fixed to the internal lead. Therefore, during the wire bonding, an impact pressure is applied to the electrode pad, but the semiconductor element is correctly supported from below by the internal lead, so that no crack is generated from the bonding portion of the semiconductor element.
以下、図面を参照して本発明の実施例につき説明す
る。第１図（ａ）は、本発明の第１の実施例の平面図、
第１図（ｂ）は第１図（ａ）のＸ−Ｘ′線断面図であ
る。外部導出リード16に連なる内部リード16Aがお互い
に接触しない程度に中心部迄延長されていて、その先端
部に半導体素子11が絶縁性接着剤18により固着されてい
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 (a) is a plan view of a first embodiment of the present invention,
FIG. 1 (b) is a cross-sectional view taken along line XX 'of FIG. 1 (a). The internal leads 16A connected to the external lead-out leads 16 extend to the center so that they do not come into contact with each other, and the semiconductor element 11 is fixed to the leading end thereof with an insulating adhesive 18.
内部リード16Aの先端には、半導体素子11の接着面と
反対側に、半導体素子11より寸法がやや大きく、半導体
素子11の周縁部に該当する枠状のリード支持片が目合せ
パターン19として固着されている。この目合せパターン
19は、半導体素子11の固着の際の目合せになるばかりで
なく、隣接する内部リード16Aの先端の間隔を正しく維
持するのにも役立っている。半導体素子11は、そのワイ
ヤボンディングするすべての電極パッド15が、内部リー
ド16Aの半導体素子固着部位上方の投影領域内に位置す
るように、配置されているから、電極パッド15と内部リ
ード16Aとを金線14でワイヤボンディングにより接続す
るときに、半導体素子11に衝撃が与えたれても、半導体
素子11は内部リード16Aによって正しく支持され、半導
体素子11にクラックが生ずることはない。なお、17はエ
ポキシ樹脂で、12はリードフレームの吊りリードであ
る。吊りリード12は、樹脂封止工程までは作業上必要で
あるが、完成品としては特に機能はもっていない。At the end of the internal lead 16A, on the side opposite to the bonding surface of the semiconductor element 11, a frame-shaped lead support piece, which is slightly larger in size than the semiconductor element 11 and corresponds to the periphery of the semiconductor element 11, is fixed as a matching pattern 19 Have been. This matching pattern
The reference numeral 19 serves not only for alignment when the semiconductor element 11 is fixed, but also for properly maintaining the interval between the tips of the adjacent internal leads 16A. Since the semiconductor element 11 is arranged such that all the electrode pads 15 to be wire-bonded are located in the projection area above the semiconductor element fixing portion of the internal lead 16A, the electrode pad 15 and the internal lead 16A are connected. When the semiconductor element 11 is shocked when the semiconductor element 11 is connected by wire bonding with the gold wire 14, the semiconductor element 11 is correctly supported by the internal leads 16A and the semiconductor element 11 does not crack. 17 is an epoxy resin, and 12 is a suspension lead of the lead frame. The suspension lead 12 is necessary for the operation up to the resin sealing step, but has no particular function as a finished product.
次に、第２実施例につき説明する。この実施例は内部
リード26Aに0.5mm〜1.0mm程度の一定間隔にエッチング
あるいはプレスによって、図示のように半導体素子形状
に合わせてきざみをつけ目合せパターン29としたもので
ある。半導体素子21の寸法が変った場合に、この目合せ
パターン29は位置確認表示としてきわめて有効である。
半導体素子21を絶縁性接着剤28で内部リード26Aに固着
し、金線24で、電極パッド25と内部リード26Aとの間を
ワイヤボンディングにより結合した後、エポキシ樹脂27
で封止することは第１実施例と同一である。Next, a second embodiment will be described. In this embodiment, an internal lead 26A is etched or pressed at a constant interval of about 0.5 mm to 1.0 mm to form a mating pattern 29 according to the shape of a semiconductor element as shown in the figure. When the dimensions of the semiconductor element 21 change, the alignment pattern 29 is extremely effective as a position confirmation display.
After the semiconductor element 21 is fixed to the internal lead 26A with an insulating adhesive 28, and the electrode pad 25 and the internal lead 26A are bonded by wire bonding with a gold wire 24, the epoxy resin 27
Is the same as in the first embodiment.
さらにこの実施例では、吊りリード22もワイヤボンデ
ィングするようにして有効ピンとして使用している。Further, in this embodiment, the suspension leads 22 are also used as effective pins by wire bonding.
以上説明したように本発明は、樹脂封止部内の内部リ
ード上に絶縁性接着剤を介して半導体素子上のワイヤボ
ンディングするすべての電極パッドが内部のリードの固
着部位の上方投影領域内に存在するように固着し、内部
リード上にリード支持片やハーフエッチあるいはプレス
パターン等により目合せパターンを形成するようにした
ものである。As described above, according to the present invention, all the electrode pads to be wire-bonded on the semiconductor element via the insulating adhesive on the internal leads in the resin sealing portion are present in the upper projected area of the internal lead fixing portion. Then, a registration pattern is formed on the internal leads by a lead support piece, a half etch, a press pattern, or the like.
本発明では従来の素子搭載部を用いないので、半導体
素子の大きさが異なっても、共通のリードフレームを用
いることができる利点がある。さらに、従来は素子搭載
部の大きい面積の金属板と樹脂との高温における熱膨張
差が大きいので、リフローソルダリングのようにパッケ
ージ全体を高温に加熱する実装方法では、従来品で樹脂
クラックが生ずることがあったが、本発明品ではこのよ
うなことがない。Since the present invention does not use the conventional element mounting portion, there is an advantage that a common lead frame can be used even if the sizes of the semiconductor elements are different. Furthermore, since the difference in thermal expansion between the metal plate having a large area of the element mounting portion and the resin and the resin at a high temperature is large in the past, a resin crack occurs in a conventional product in a mounting method in which the entire package is heated to a high temperature such as reflow soldering. However, this is not the case with the product of the present invention.
内部リードに半導体素子を固着する作業は、内部リー
ドに設けた目合せパターンを利用することで容易に行な
うことができる。またボンディングワイヤが接続された
すべての電極パッドの位置が内部リードの固着位置の上
方投影領域内にあるので、ボンディング時の押圧による
衝撃があっても、半導体素子のクラック発生を低減でき
る。The operation of fixing the semiconductor element to the internal lead can be easily performed by using the alignment pattern provided on the internal lead. Further, since the positions of all the electrode pads to which the bonding wires are connected are located in the upper projected area of the positions where the internal leads are fixed, the occurrence of cracks in the semiconductor element can be reduced even if there is an impact due to the pressing during bonding.
第１図、第２図は本発明の第１実施例、第２実施例のそ
れぞれの（ａ）平面図・（ｂ）断面図、第３図は従来例
の（ａ）平面図・（ｂ）断面図である。 11,21……半導体素子、 14,24……金線、 15,25……電極パッド、 16A,26A……内部リード、 18,28……絶縁性接着剤、 19……目合せパターン（リード支持片）、 29……目合せパターン。1 and 2 are (a) plan view and (b) sectional view of the first and second embodiments of the present invention, and FIG. 3 is (a) plan view and (b) of a conventional example. FIG. 11,21 …… Semiconductor element, 14,24… Gold wire, 15,25 …… Electrode pad, 16A, 26A …… Internal lead, 18,28 …… Insulating adhesive, 19 …… Matching pattern (Lead (Supporting piece), 29 ... Matching pattern.
Claims (1)
内部リードの先端部上に、半導体素子が絶縁性接着剤に
固着され、前記半導体素子のボンディング接続されるべ
きすべての電極パッドの直下に前記内部リードを夫々位
置せしめ、すべてのワイヤボンディングが前記内部リー
ドの直上にて行われるようにしたことを特徴とする樹脂
封止型半導体装置。A semiconductor element is fixed to an insulating adhesive on an end of an internal lead in a resin sealing portion by using an alignment pattern, and is directly under all electrode pads of the semiconductor element to be bonded and connected. Wherein said internal leads are respectively positioned so that all wire bonding is performed immediately above said internal leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066446A JP2602278B2 (en) | 1988-03-18 | 1988-03-18 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066446A JP2602278B2 (en) | 1988-03-18 | 1988-03-18 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01238128A JPH01238128A (en) | 1989-09-22 |
| JP2602278B2 true JP2602278B2 (en) | 1997-04-23 |
Family
ID=13316009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63066446A Expired - Lifetime JP2602278B2 (en) | 1988-03-18 | 1988-03-18 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2602278B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940007649B1 (en) * | 1991-04-03 | 1994-08-22 | 삼성전자 주식회사 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS5684360U (en) * | 1979-11-29 | 1981-07-07 | ||
| JPS61240U (en) * | 1984-06-06 | 1986-01-06 | 日本電気株式会社 | semiconductor equipment |
-
1988
- 1988-03-18 JP JP63066446A patent/JP2602278B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01238128A (en) | 1989-09-22 |
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