JP2800806B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP2800806B2
JP2800806B2 JP8289409A JP28940996A JP2800806B2 JP 2800806 B2 JP2800806 B2 JP 2800806B2 JP 8289409 A JP8289409 A JP 8289409A JP 28940996 A JP28940996 A JP 28940996A JP 2800806 B2 JP2800806 B2 JP 2800806B2
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
package
semiconductor chip
package base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8289409A
Other languages
Japanese (ja)
Other versions
JPH10135245A (en
Inventor
潔 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8289409A priority Critical patent/JP2800806B2/en
Publication of JPH10135245A publication Critical patent/JPH10135245A/en
Application granted granted Critical
Publication of JP2800806B2 publication Critical patent/JP2800806B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/54466—Located in a dummy or reference die
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体チップをワイ
ヤボンディングを用いることなくパッケージする半導体
装置とその製造方法に関する。The present invention relates to a semiconductor device for packaging a semiconductor chip without using wire bonding and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】従来、半導体チップのパッケージ構造と
して、ワイヤボンディングを用いる構造やワイヤボンデ
ィングを用いない構造が提案されている。前者の構造の
製造方法を図４を用いて説明する。先ず、図４（ａ）の
ように、半導体素子及びボンディングパッド１１１の形
成が完了している半導体基板１１０を、スクライブまた
はダイシング加工技術により切断分離し、図４（ｂ）の
ように個々の半導体チップ１１４を形成する。次に、図
４（ｃ）のように、リードフレーム１２０上にＡｕＳｎ
１２１を搭載し３２０℃で加熱してＡｕＳｎ１２１を溶
解する。その後、溶解したＡｕＳｎ１２１上に半導体チ
ップ１１４をマウントして常温まで冷却し、半導体チッ
プ１１４をリードフレーム１２０上に固定する。次に、
図４（ｄ）のように、リードフレーム１２０の各リード
と半導体チップ１１４上のボンディングパッドを電気的
に接続するため、Ａｕワイヤ１２２を用いてボンディン
グを行う。最後に、樹脂モールド１２３で半導体チップ
１１４をリードフレーム１２０と一緒に封止し、図４
（ｅ）のようなパッケージが完成される。2. Description of the Related Art Hitherto, as a package structure of a semiconductor chip, a structure using wire bonding or a structure not using wire bonding has been proposed. A method for manufacturing the former structure will be described with reference to FIG. First, as shown in FIG. 4A, the semiconductor substrate 110 on which the formation of the semiconductor element and the bonding pad 111 is completed is cut and separated by a scribe or dicing processing technique, and as shown in FIG. A chip 114 is formed. Next, as shown in FIG. 4C, the AuSn
The AuSn 121 is dissolved by heating at 320.degree. Thereafter, the semiconductor chip 114 is mounted on the melted AuSn 121 and cooled to room temperature, and the semiconductor chip 114 is fixed on the lead frame 120. next,
As shown in FIG. 4D, in order to electrically connect each lead of the lead frame 120 to a bonding pad on the semiconductor chip 114, bonding is performed using an Au wire 122. Finally, the semiconductor chip 114 is sealed together with the lead frame 120 with a resin mold 123, and FIG.
A package as shown in (e) is completed.

【０００３】また、ワイヤボンディングを用いない後者
の構造、例えば、フリップチップ構造の製造方法を図５
を用いて説明する。先ず、図５（ａ）のように、スクラ
イブまたはダイシング加工技術によりチップ化された半
導体チップ２１４上のボンディングパッド２１１上に、
図５（ｂ）のように、Ａｕまたは半田により接続用バン
プ２１３を形成する。次に、図５（ｃ）のように、リー
ドフレーム２２０上に半導体チップ２１４の表面を下に
してフリップチップ実装を行い、リードフレーム２２０
と半導体チップ２１４の電気的な接続を行う。最後に、
リードフレーム２２０にメタルキャップ２２３を被せて
半導体チップ２１４を封止し、図５（ｄ）のようなパッ
ケージが完成される。FIG. 5 shows a method of manufacturing the latter structure without using wire bonding, for example, a flip chip structure.
This will be described with reference to FIG. First, as shown in FIG. 5A, on bonding pads 211 on a semiconductor chip 214 chipped by a scribe or dicing technique,
As shown in FIG. 5B, the connection bump 213 is formed of Au or solder. Next, as shown in FIG. 5C, flip chip mounting is performed on the lead frame 220 with the surface of the semiconductor chip 214 facing down.
And the semiconductor chip 214 are electrically connected. Finally,
The semiconductor chip 214 is sealed by covering the lead frame 220 with the metal cap 223, and the package as shown in FIG. 5D is completed.

【０００４】[0004]

【発明が解決しようとする課題】近年、半導体素子にお
いては製造コストの低減が大きな課題となっており、特
に製造工程数の削減におけるコストダウンの効果は最も
大きい。これは、半導体基板上に半導体素子を製造する
前工程はもちろん、後工程と呼ばれる半導体素子の実装
工程においても同様である。しかし、前記した従来技術
では、半導体素子をチップ化する工程、リードフレーム
等に半導体チップをマウントする工程、半導体チップと
リードフレームをワイヤボンディングやバンプ等で電気
的に接続する工程、樹脂あるいは金属キャップ等で半導
体チップを封止する工程と、少なくとも４工程を必要と
しており、特に、半導体チップのマウント工程において
は、切断分離された個々の半導体チップをそれぞれマウ
ントする必要があるために、半導体チップの数だけの工
程が必要であり、工程数が極めて多いものとなる。さら
に、化合物半導体のように半導体自身の機械的強度が弱
い場合には、半導体チップの小型化に伴い、チップハン
ドリングの際に応力を加えたり破壊してしまい、実装時
点での歩留まり低下等の問題点が生じていた。In recent years, reduction of manufacturing cost has become a major issue in semiconductor devices, and the effect of cost reduction in reducing the number of manufacturing steps is the greatest. This applies not only to a pre-process of manufacturing a semiconductor element on a semiconductor substrate but also to a post-process of mounting a semiconductor element. However, in the above-described prior art, a step of forming a semiconductor element into a chip, a step of mounting a semiconductor chip on a lead frame or the like, a step of electrically connecting the semiconductor chip and the lead frame by wire bonding, bumps, or the like, a resin or metal cap And the like, and at least four steps are required. Particularly, in the mounting step of the semiconductor chip, it is necessary to mount each of the cut and separated semiconductor chips. The number of steps is required, and the number of steps is extremely large. Furthermore, when the mechanical strength of the semiconductor itself is weak, such as in a compound semiconductor, stress or breakage occurs during chip handling due to the miniaturization of the semiconductor chip, resulting in a problem such as a decrease in yield at the time of mounting. A point had arisen.

【０００５】本発明の目的は、半導体チップの製造から
パッケージの完成までの工程数を削減し、かつ製造歩留
りを高めることが可能な半導体装置とその製造方法を提
供することにある。An object of the present invention is to provide a semiconductor device capable of reducing the number of steps from the production of a semiconductor chip to the completion of a package and increasing the production yield, and a method for producing the same.

【０００６】[0006]

【課題を解決するための手段】本発明は、パッケージベ
ース上に半導体チップが搭載され、このパッケージベー
スに設けられた外部接続用の電極と前記半導体チップと
が電気接続されてなる半導体装置において、パッケージ
ベースと半導体チップが同一平面形状及び平面寸法に形
成されていることを特徴とする。また、半導体チップと
パッケージベースとは樹脂で封止されていてもよい。According to the present invention, there is provided a semiconductor device in which a semiconductor chip is mounted on a package base, and an external connection electrode provided on the package base is electrically connected to the semiconductor chip. The package base and the semiconductor chip are formed in the same plane shape and plane dimensions. Further, the semiconductor chip and the package base may be sealed with a resin.

【０００７】また、本発明の半導体装置の製造方法は、
複数の半導体チップに相当する素子が形成されている半
導体基板を、前記半導体チップを個々に搭載可能な電極
及び外部接続用電極が形成されているパッケージ基板に
搭載し、前記半導体基板とパッケージ基板とを相互に電
気接続する工程と、前記半導体基板とパッケージ基板と
を一体的に切断して複数個の半導体チップとパッケージ
ベースとに分離する工程とを含むんでいる。この場合、
切断分離された半導体チップとパッケージベースとをそ
れぞれ樹脂で封止する工程を含んでもよい。また、半導
体基板の一部に目合わせマークを形成し、パッケージ基
板の対応する箇所には目合わせ窓を形成し、半導体基板
をパッケージ基板に搭載する際にこれら目合わせマーク
と目合わせ窓を利用して両者の位置決めを行うことが好
ましい。Further, a method of manufacturing a semiconductor device according to the present invention
A semiconductor substrate on which elements corresponding to a plurality of semiconductor chips are formed is mounted on a package substrate on which electrodes on which the semiconductor chips can be individually mounted and electrodes for external connection are formed. And a step of integrally cutting the semiconductor substrate and the package substrate to separate them into a plurality of semiconductor chips and a package base. in this case,
The method may include a step of sealing each of the cut and separated semiconductor chip and the package base with a resin. In addition, a registration mark is formed on a part of the semiconductor substrate, and a registration window is formed on the corresponding portion of the package substrate, and the registration mark and the registration window are used when the semiconductor substrate is mounted on the package substrate. Then, it is preferable to perform both positioning.

【０００８】[0008]

【発明の実施の形態】次に、本発明の実施形態について
図面を参照して説明する。図１は本発明にかかる第１の
実施形態の製造方法を工程順に示す断面図である。ま
た、図２（ａ），（ｂ）は半導体基板と、パッケージ用
のセラミックス基板の平面図である。先ず、図１（ａ）
及び図２（ａ）のように、シリコン等の半導体基板１０
には、多数個のチップとなるべき所要の素子１３が形成
されており、その表面上には電気接続用のボンディング
パッド１１が形成されている。ここで、前記半導体基板
１０の一部、ここでは２箇所には前記セラミックス基板
に対する半導体基板１０の位置合わせを行うための目合
わせマーク１２が形成されている。この実施形態では、
この目合わせマーク１２は、前記ボンディングパッド１
１と同じ配線を利用した矩形パターンとして形成されて
いる。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a manufacturing method according to a first embodiment of the present invention in the order of steps. FIGS. 2A and 2B are plan views of a semiconductor substrate and a ceramic substrate for a package. First, FIG.
And a semiconductor substrate 10 such as silicon as shown in FIG.
Are formed with required elements 13 to be a large number of chips, and bonding pads 11 for electrical connection are formed on the surface thereof. Here, alignment marks 12 for aligning the semiconductor substrate 10 with respect to the ceramic substrate are formed at a part of the semiconductor substrate 10, here at two places. In this embodiment,
The alignment mark 12 is formed on the bonding pad 1.
1 is formed as a rectangular pattern using the same wiring.

【０００９】そして、この半導体基板１０は、図１
（ｂ）に示すように、その表面を下方に向けて前記セラ
ミックス基板２０の上に搭載される。このセラミックス
基板２０は、その裏面には図２（ｂ）のようにＩ／Ｏピ
ン２１が形成されており、その表面にはポリイミド膜２
２が成膜されており、このポリイミド膜２２に設けられ
た開口に接続用電極２３が露呈されている。さらに、セ
ラミックス基板２０の平面２箇所には、前記半導体基板
１０の目合わせマーク１２に対応する位置に目合わせ窓
２４が基板の厚さ方向に貫通された状態で開口されてい
る。そして、前記半導体基板１０をセラミックス基板２
０に搭載する際には、セラミックス基板２０の裏面側か
ら目合わせ窓２４内にレーザ等の光を投射し、この光が
半導体基板１０上の目合わせマーク１２で反射された反
射光を検出することで半導体基板１０とセラミックス基
板２０の位置合わせを行う。次いで、図１（ｃ）のよう
に、位置合わせが完了した半導体基板１０上のボンディ
ングパッド１１とセラミックス基板２０の接続用電極２
３を公知の熱圧着等の接続技術を用いて接続し、フリッ
プチップ法によるボンディングを実行する。The semiconductor substrate 10 is formed as shown in FIG.
As shown in (b), the substrate is mounted on the ceramic substrate 20 with its surface facing downward. The ceramic substrate 20 has I / O pins 21 formed on the back surface as shown in FIG. 2B, and the polyimide film 2 on the surface.
2 is formed, and the connection electrode 23 is exposed in an opening provided in the polyimide film 22. Further, at two locations on the plane of the ceramic substrate 20, a matching window 24 is opened at a position corresponding to the matching mark 12 of the semiconductor substrate 10 in a state penetrating in the thickness direction of the substrate. Then, the semiconductor substrate 10 is replaced with the ceramic substrate 2.
When mounted on the semiconductor substrate 10, light such as a laser is projected into the alignment window 24 from the back surface side of the ceramic substrate 20, and this light is reflected by the alignment mark 12 on the semiconductor substrate 10 to detect reflected light. Thus, the semiconductor substrate 10 and the ceramic substrate 20 are aligned. Next, as shown in FIG. 1C, the bonding pad 11 on the semiconductor substrate 10 and the connecting electrode 2 between the ceramic substrate 20 are aligned.
3 is connected using a known connection technique such as thermocompression bonding, and bonding is performed by a flip chip method.

【００１０】しかる上で、図１（ｄ）のように、一体化
された半導体基板１０とセラミックス基板２０を公知の
ダイシング技術により同時に切断する。これにより、半
導体基板１０では各半導体チップ１４として個々に切断
分離され、同時にセラミックス基板２０も半導体チップ
１４と同一形状、同一寸法のパッケージベース２５とし
て切断分離される。その上で、これら切断分離された半
導体チップ１４とパッケージベース２５に対し樹脂モー
ルド１５を施し、各半導体チップ１４とパッケージベー
ス２５を封止して個々のパッケージが完成される。Then, as shown in FIG. 1D, the integrated semiconductor substrate 10 and ceramic substrate 20 are simultaneously cut by a known dicing technique. As a result, the semiconductor substrate 10 is cut and separated individually as each semiconductor chip 14, and at the same time, the ceramic substrate 20 is also cut and separated as a package base 25 having the same shape and the same dimensions as the semiconductor chip 14. Then, a resin mold 15 is applied to the cut and separated semiconductor chip 14 and package base 25, and each semiconductor chip 14 and package base 25 are sealed to complete an individual package.

【００１１】このように、半導体基板１０をセラミック
ス基板２０に対して搭載し、その後に半導体基板１０を
セラミックス基板２０と共に各半導体チップ１４及びパ
ッケージベース２５として切断分離する製造方法を採用
することで、従来、半導体チップ単位で行っていたマウ
ント、ボンディングの工程を１回のマウント、ボンディ
ング工程で実現できる。したがって、これらの工程数
を、従来の半導体チップの個数に相当する回数から１回
に低減でき、その製造工程数を大幅に低減することがで
きる。また、化合物半導体のように半導体自身の機械的
強度が弱い場合においても、チップハンドリングの工程
を必要としないため、半導体チップに応力を加えたり、
破壊したりすることによる歩留まり低下の問題点が解消
できる。As described above, by adopting a manufacturing method in which the semiconductor substrate 10 is mounted on the ceramic substrate 20, and then the semiconductor substrate 10 is cut and separated as the respective semiconductor chips 14 and the package base 25 together with the ceramic substrate 20, The mounting and bonding process conventionally performed for each semiconductor chip can be realized by a single mounting and bonding process. Therefore, the number of these steps can be reduced from the number corresponding to the number of conventional semiconductor chips to one, and the number of manufacturing steps can be greatly reduced. Also, even when the mechanical strength of the semiconductor itself is weak, such as a compound semiconductor, a chip handling step is not required, so that stress is applied to the semiconductor chip,
The problem of lowering the yield due to breakage can be solved.

【００１２】次に、本発明にかかる第２の実施形態の半
導体装置とその製造方法を図３を用いて説明する。な
お、前記第１の実施形態と等価な部分には同一符号を付
してある。先ず、図３（ａ）のように、表面上に接続用
のボンディングパッド１１及び目合わせマーク１２の形
成されている半導体基板１０を形成する。この半導体基
板１０は前記第１の実施形態と同じものでよい。次に、
図１（ｂ）のように、裏面にＡｕまたは半田により接続
用バンプ２６が形成されており、その表面にポリイミド
膜２２が成膜されており、接続用電極２３の上部が開口
されているＡｌＮ等の熱伝導率の高いセラミックス基板
２０Ａを形成する。また、ここでは、前記接続用バンプ
２６の間には、放熱用バンプ２７を形成している。この
セラミックス基板２０Ａに前記半導体基板１０をその表
面を下方に向けて搭載する。この搭載に際しては、セラ
ミックス基板２０Ａに形成されている目合わせ窓２４よ
りレーザ等の光を半導体基板１０上の目合わせマーク１
２に照射し、その反射光を検出することで半導体基板１
０とセラミックス基板２０Ａの位置合わせを行うことは
第１の実施形態と同じである。Next, a semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to FIG. Note that parts equivalent to those in the first embodiment are denoted by the same reference numerals. First, as shown in FIG. 3A, a semiconductor substrate 10 having a bonding pad 11 for connection and a registration mark 12 formed on a surface is formed. This semiconductor substrate 10 may be the same as that of the first embodiment. next,
As shown in FIG. 1B, a connection bump 26 is formed on the back surface by Au or solder, a polyimide film 22 is formed on the surface, and an AlN in which the upper portion of the connection electrode 23 is opened. The ceramic substrate 20A having a high thermal conductivity, such as, for example, is formed. Further, here, a heat radiation bump 27 is formed between the connection bumps 26. The semiconductor substrate 10 is mounted on the ceramic substrate 20A with its surface facing downward. At the time of this mounting, light such as a laser is emitted from the alignment window 24 formed in the ceramic substrate 20A to the alignment mark 1 on the semiconductor substrate 10.
2 to the semiconductor substrate 1 by detecting the reflected light.
The alignment between the ceramic substrate 20A and the ceramic substrate 20A is the same as in the first embodiment.

【００１３】これら半導体基板１０とセラミックス基板
２０Ａの位置合わせが完了した後、図３（ｃ）のよう
に、半導体基板１０上のボンディングパッド１１とセラ
ミックス基板２０Ａの接続用電極２３を公知の熱圧着等
の接続技術を用いて接続する。さらに、半導体基板１０
とセラミックス基板２０Ａをダイシング技術により同時
に切断し、半導体基板１０とセラミックス基板２０Ａと
を複数の半導体チップ１４とパッケージベース２５に切
断分離し、個々のパッケージを完成する。After the alignment between the semiconductor substrate 10 and the ceramic substrate 20A is completed, as shown in FIG. 3C, the bonding pads 11 on the semiconductor substrate 10 and the connection electrodes 23 of the ceramic substrate 20A are bonded by a known thermocompression bonding. The connection is made using such a connection technique. Further, the semiconductor substrate 10
And the ceramic substrate 20A are simultaneously cut by a dicing technique, and the semiconductor substrate 10 and the ceramic substrate 20A are cut and separated into a plurality of semiconductor chips 14 and a package base 25, thereby completing individual packages.

【００１４】この実施形態のパッケージ構造では、セラ
ミックス基板２０Ａの裏面に形成されている接続用バン
プ２６を図外のプリント基板の電極等に直接接続するこ
とで、半導体装置の実装が実現される。また、この実施
形態では、セラミックス基板２０ＡがＡｌＮ等の熱伝導
率の優れた材質であり、かつセラミックス基板２０Ａの
裏面に設けられた放熱用バンプ２７がプリント基板に接
触されることで、その放熱性が高められる。したがっ
て、低熱抵抗化が必要な高出力ＦＥＴ等（出力がおおよ
そ３〜４Ｗ程度）の半導体チップの実装についても適応
できる。また、この場合には、半導体基板１０及びセラ
ミックス基板２０Ａを個々に切断分離した後の樹脂封止
工程が不要であるため、製造工程数を前記第１の実施形
態よりもさらに低減することができる。In the package structure of this embodiment, the mounting of the semiconductor device is realized by directly connecting the connection bumps 26 formed on the back surface of the ceramic substrate 20A to electrodes and the like of a printed board (not shown). In this embodiment, the ceramic substrate 20A is made of a material having excellent thermal conductivity, such as AlN, and the heat radiation bumps 27 provided on the back surface of the ceramic substrate 20A are brought into contact with the printed circuit board, so that the heat radiation is achieved. Sex is enhanced. Therefore, the present invention can be applied to mounting of a semiconductor chip such as a high-output FET or the like (the output is about 3 to 4 W) which requires a low thermal resistance. Further, in this case, since the resin sealing step after cutting and separating the semiconductor substrate 10 and the ceramic substrate 20A individually is unnecessary, the number of manufacturing steps can be further reduced as compared with the first embodiment. .

【００１５】[0015]

【発明の効果】以上説明したように本発明は、半導体基
板をパッケージ基板に搭載した後に、半導体基板とパッ
ケージ基板とを一体的に切断して複数個の半導体チップ
とパッケージ基板とに分離して個々の半導体装置を形成
しているので、従来、半導体チップの個数分の回数だけ
必要とされていたマウント及びボンディングの各工程を
１回の工程に短縮することが可能になり、半導体装置の
製造工程を大幅に低減することができる。また、化合物
半導体のように半導体自身の機械的強度が弱い場合にお
いても、半導体チップ自身のハンドリングを行わないた
め、応力を加えたりあるいは破壊したりすることがなく
なるため、実装時点で生じていた不良を回避することが
でき、製品の歩留まりを１０％以上向上させることが可
能になる。As described above, according to the present invention, after a semiconductor substrate is mounted on a package substrate, the semiconductor substrate and the package substrate are cut integrally to separate them into a plurality of semiconductor chips and a package substrate. Since individual semiconductor devices are formed, each mounting and bonding process, which was conventionally required as many times as the number of semiconductor chips, can be reduced to one process. The number of steps can be greatly reduced. In addition, even when the mechanical strength of the semiconductor itself is weak, such as a compound semiconductor, the semiconductor chip itself is not handled, so that stress is not applied or destroyed. Can be avoided, and the product yield can be improved by 10% or more.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態を製造工程順に示す断
面図である。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

【図２】本発明にかかる半導体基板とセラミックス基板
の各平面図である。FIG. 2 is a plan view of each of a semiconductor substrate and a ceramic substrate according to the present invention.

【図３】本発明の第２の実施形態を製造工程順に示す断
面図である。FIG. 3 is a cross-sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

【図４】従来の製造方法の一例を製造工程順に示す断面
図である。FIG. 4 is a cross-sectional view showing an example of a conventional manufacturing method in the order of manufacturing steps.

【図５】従来の製造方法の他の例を製造工程順に示す断
面図である。FIG. 5 is a cross-sectional view showing another example of a conventional manufacturing method in the order of manufacturing steps.

【符号の説明】[Explanation of symbols]

１０ 半導体基板 １１ ボンディングパッド １２ 目合わせマーク １３ 素子 １４ 半導体チップ ２０，２０Ａ セラミックス基板 ２１ ＩＯピン ２２ ポリイミド膜 ２３ 接続用電極 ２４ 目合わせ窓 ２５ パッケージベース ２６ 接続用バンプ ２７ 放熱用バンプ Reference Signs List 10 semiconductor substrate 11 bonding pad 12 alignment mark 13 element 14 semiconductor chip 20, 20A ceramic substrate 21 IO pin 22 polyimide film 23 connection electrode 24 alignment window 25 package base 26 connection bump 27 heat radiation bump

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 パッケージベース上に半導体チップが搭
載され、前記パッケージベースに設けられた外部接続用
の電極と前記半導体チップとが電気接続されてなる半導
体装置において、前記パッケージベースと半導体チップ
が同一平面形状及び平面寸法に形成されていることを特
徴とする半導体装置。1. A semiconductor device having a semiconductor chip mounted on a package base and an external connection electrode provided on the package base electrically connected to the semiconductor chip, wherein the package base and the semiconductor chip are the same. A semiconductor device having a planar shape and planar dimensions. 【請求項２】 半導体チップの表面にボンディングパッ
ドが設けられ、パッケージベースの表面には前記ボンデ
ィングパッドに対応する接続用電極が設けられ、前記半
導体チップは表面をパッケージベースの表面に向けて搭
載され、前記ボンディングパッドが前記接続用電極に直
接接続されている請求項１の半導体装置。2. A bonding pad is provided on a surface of the semiconductor chip, a connection electrode corresponding to the bonding pad is provided on a surface of the package base, and the semiconductor chip is mounted with the surface facing the surface of the package base. 2. The semiconductor device according to claim 1, wherein said bonding pad is directly connected to said connection electrode. 【請求項３】 半導体チップとパッケージベースとが樹
脂で封止されてなる請求項２の半導体装置。3. The semiconductor device according to claim 2, wherein the semiconductor chip and the package base are sealed with a resin. 【請求項４】 複数の半導体チップに相当する素子が形
成されている半導体基板を、前記半導体チップを個々に
搭載可能な電極及び外部接続用電極が形成されているパ
ッケージ基板に搭載し、前記半導体基板とパッケージ基
板とを相互に電気接続する工程と、前記半導体基板とパ
ッケージ基板とを一体的に切断して複数個の半導体チッ
プとパッケージベースとに分離する工程とを含むことを
特徴とする半導体装置の製造方法。4. A semiconductor substrate on which elements corresponding to a plurality of semiconductor chips are formed on a package substrate on which electrodes on which the semiconductor chips can be individually mounted and electrodes for external connection are formed. A semiconductor, comprising: a step of electrically connecting a substrate and a package substrate to each other; and a step of integrally cutting the semiconductor substrate and the package substrate to separate a plurality of semiconductor chips and a package base. Device manufacturing method. 【請求項５】 切断分離された半導体チップとパッケー
ジベースとをそれぞれ樹脂で封止する工程を含む請求項
４の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of sealing each of the cut and separated semiconductor chip and the package base with a resin. 【請求項６】 半導体基板の一部に目合わせマークを形
成し、パッケージ基板の対応する箇所には目合わせ窓を
形成し、半導体基板をパッケージ基板に搭載する際にこ
れら目合わせマークと目合わせ窓を利用して両者の位置
決めを行う請求項４または５の半導体装置の製造方法。6. A registration mark is formed in a part of the semiconductor substrate, a registration window is formed in a corresponding portion of the package substrate, and the registration mark is aligned with the registration mark when the semiconductor substrate is mounted on the package substrate. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the positioning of both is performed using a window.
JP8289409A 1996-10-31 1996-10-31 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2800806B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8289409A JP2800806B2 (en) 1996-10-31 1996-10-31 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8289409A JP2800806B2 (en) 1996-10-31 1996-10-31 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH10135245A JPH10135245A (en) 1998-05-22
JP2800806B2 true JP2800806B2 (en) 1998-09-21

Family

ID=17742874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8289409A Expired - Fee Related JP2800806B2 (en) 1996-10-31 1996-10-31 Semiconductor device and manufacturing method thereof

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Country Link
JP (1) JP2800806B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462284B1 (en) 1998-07-01 2002-10-08 Seiko Epson Corporation Semiconductor device and method of manufacture thereof
JP2001127088A (en) * 1999-10-27 2001-05-11 Mitsubishi Electric Corp Semiconductor device

Also Published As

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