JPH02130950A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02130950A JPH02130950A JP28597788A JP28597788A JPH02130950A JP H02130950 A JPH02130950 A JP H02130950A JP 28597788 A JP28597788 A JP 28597788A JP 28597788 A JP28597788 A JP 28597788A JP H02130950 A JPH02130950 A JP H02130950A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- stepped portion
- semiconductor device
- fixing agent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000011368 organic material Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 abstract description 3
- 239000003795 chemical substances by application Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置、特に半導体素子とリードフレー
ムとを接合する構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure for joining a semiconductor element and a lead frame.
第４図は従来の半導体装置のダイスパッド及びその周辺
部を示す図で、（ａ）が平面図、（ｂ）がＩＶ−■線が
断面図である０図において、１は半導体素子、４はリー
ドフレーム、５は前記半導体素子１を載置するダイスパ
ッド、６は前記半導体素子１とリードフレーム４を電気
的に導通させるための結線（金線）、７は前記半導体素
子１とダイスバット５を接合する接合材である。FIG. 4 is a diagram showing a die pad and its surrounding area of a conventional semiconductor device. In FIG. 5 is a lead frame, 5 is a die pad on which the semiconductor element 1 is placed, 6 is a connection (gold wire) for electrically connecting the semiconductor element 1 and the lead frame 4, and 7 is the semiconductor element 1 and the die pad. This is a bonding material for bonding 5.
従来の半導体装置は半導体素子１の側面１ａをフラット
にして切断した後、前記半導体素子１とダイスパッド５
を接合するために温度を上げて金属材料又は接着剤等の
接合剤７を用いて固着していた。さらに金線等による結
線６をやりやすくするため、ダイスパッド５部を曲げ加
工により少し折り曲げリードフレーム４より低くなるよ
うにしていた。In the conventional semiconductor device, after cutting the semiconductor element 1 with the side surface 1a flattened, the semiconductor element 1 and the die pad 5 are cut.
In order to bond them, the temperature is raised and a metal material or a bonding agent 7 such as an adhesive is used to fix them. Furthermore, in order to facilitate the connection 6 using gold wire or the like, the die pad 5 was bent a little to be lower than the lead frame 4.
従来の半導体装置は以上のように構成されているので、
半導体素子１をダイスパッド４に接合する際、その接合
のための温度変化により、半導体素子１とダイスパッド
４との熱膨張率（収縮率）に差があるため、半導体素子
１に反りが発生し、応力がかかる問題点があった。Conventional semiconductor devices are configured as described above, so
When the semiconductor element 1 is bonded to the die pad 4, there is a difference in the coefficient of thermal expansion (contraction rate) between the semiconductor element 1 and the die pad 4 due to temperature changes during the bonding, so that the semiconductor element 1 is warped. However, there was a problem that stress was applied.
この発明は上記のような問題点を解消するためになされ
たもので、半導体素子１にかかる応力や反りを緩和する
ことができる半導体装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can alleviate the stress and warpage applied to the semiconductor element 1.
この発明に係る半導体装置は、半導体素子の側面に段差
部を設け、絶縁性の有機材料からなる固定剤を用いて、
前記段差部の側面及び上面とリードフレーム先端の側面
及び下面との間を固定したものである。In the semiconductor device according to the present invention, a stepped portion is provided on the side surface of a semiconductor element, and a fixing agent made of an insulating organic material is used.
The side and top surfaces of the stepped portion and the side and bottom surfaces of the tip of the lead frame are fixed.
この発明における半導体装置は半導体素子を固定する固
定部が従来の接合部より小さくなり、しかもその固定剤
に有機材料を用いたので半導体素子を固定した後の半導
体素子の反りが無くなる。In the semiconductor device of the present invention, the fixing part for fixing the semiconductor element is smaller than the conventional joint part, and since an organic material is used as the fixing agent, there is no warping of the semiconductor element after the semiconductor element is fixed.
第１図（ａ）はこの発明の一実施例による半導体装置を
示す平面図、第１図（ｂ）は第１図（ａ）のＩ−１線断
面図である０図において、１は半導体素子、４はリード
フレーム、６は前記半導体素子１とリードフレーム４と
を電気的に導通させるための結線（金線）、８は半導体
素子１を固定するための絶縁性の固定剤であり、この固
定剤は絶縁性の有機材料からなるものが最適である。FIG. 1(a) is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line I-1 in FIG. 1(a). 4 is a lead frame; 6 is a connection (gold wire) for electrically connecting the semiconductor element 1 and the lead frame 4; 8 is an insulating fixing agent for fixing the semiconductor element 1; This fixing agent is optimally made of an insulating organic material.
まな第２図（ａ）、 （ｂ）はそれぞれ上記第１図の実
施例に用いられる半導体素子１の側面図、及び斜視図を
示す０図において、２は段差部側面、３は段差部上面で
ある。FIGS. 2(a) and 2(b) are a side view and a perspective view of the semiconductor element 1 used in the embodiment shown in FIG. It is.
上記実施例において、絶縁性の固定剤８は、半導体素子
１の段差部側面２及び上面３とリードフレーム２先端の
側面及び下面との間に設けられている。すなわち半導体
素子１は絶縁性の固定剤８を介してリードフレーム４に
固定される。In the above embodiment, the insulating fixing agent 8 is provided between the side surface 2 and top surface 3 of the stepped portion of the semiconductor element 1 and the side surface and bottom surface of the tip of the lead frame 2. That is, the semiconductor element 1 is fixed to the lead frame 4 via the insulating fixing agent 8.
次に動作について説明する。まず半導体素子１を各素子
に分離する工程時に、その半導体素子１に第２図に示す
ような段差部（段差部側面２及び段差部上面３）を作成
する。このとき、半導体素子１の表面から段差部上面３
までの距離をリードフレーム４の厚さとほぼ同等にする
ように加工するとリードフレーム４と半導体素子１との
結線作業が容易となる。そして半導体素子の段差部側面
２及び段差部上面３とリードフレームの側面及び下面と
を絶縁性の固定剤８により固定する。Next, the operation will be explained. First, in the step of separating the semiconductor element 1 into each element, a stepped portion (a stepped portion side surface 2 and a stepped portion upper surface 3) as shown in FIG. 2 is created in the semiconductor element 1. At this time, from the surface of the semiconductor element 1 to the top surface 3 of the stepped portion
By processing the distance to be approximately equal to the thickness of the lead frame 4, the connection work between the lead frame 4 and the semiconductor element 1 becomes easier. Then, the side surface 2 of the stepped portion and the upper surface 3 of the stepped portion of the semiconductor element are fixed to the side and lower surfaces of the lead frame using an insulating fixing agent 8.
以上のように上記実施例によると、半導体素子ｌの段差
部側面２及び段差部上面３とリードフレーム４の先端の
側面および下面とを絶縁性の固定剤８（特に有機材料の
固定剤）により接合したので、半導体素子１の反りを無
くし、応力が緩和される効果がある。As described above, according to the above embodiment, the side surface 2 of the stepped portion and the upper surface 3 of the stepped portion of the semiconductor element l, and the side surface and lower surface of the tip of the lead frame 4 are bonded by the insulating fixing agent 8 (particularly the fixing agent made of organic material). Since they are bonded, there is an effect that warping of the semiconductor element 1 is eliminated and stress is alleviated.
また、半導体素子１の表ｍ（電極が形成された面）から
段差部上面３までの距離をリードフレーム４の厚さと同
等以上に加工することにより、第３図のような従来のダ
イスパッドをリードフレームに対して低い位置に曲げ加
工しているのと同等の効果をもつことができる。Furthermore, by processing the distance from the surface m (the surface on which electrodes are formed) of the semiconductor element 1 to the top surface 3 of the stepped portion to be equal to or greater than the thickness of the lead frame 4, the conventional die pad as shown in FIG. It can have the same effect as bending the lead frame at a lower position.
さらに、従来のリードフレーム４の数が増えると、第５
図に示すようにこのリードフレームのバタツキを防ぐた
めリードフレーム固定シート９を使用していたが、上記
実施例の絶縁性の固定剤８はこれと同等の効果を有する
。Furthermore, when the number of conventional lead frames 4 increases, the fifth
As shown in the figure, a lead frame fixing sheet 9 was used to prevent the lead frame from fluttering, but the insulating fixing agent 8 of the above embodiment has the same effect.
なお上記実施例では、絶縁性の固定剤８が半導体素子ｌ
の側面全周に施されているものを示したが、第３図のよ
うにリードフレーム４先端の側面及び下面部のみに施さ
れていてもよい。In the above embodiment, the insulating fixing agent 8 is attached to the semiconductor element l.
Although the lead frame 4 is shown as having been applied to the entire circumference of the side surface thereof, it may be applied only to the side surface and lower surface of the tip of the lead frame 4 as shown in FIG.
以上のように、この発明によれば半導体素子の側面に段
差部を形成し、その段差部にリードフレームを絶縁性の
有機材料からなる固定剤により接合したので、半導体素
子の反りを無くし応力が緩和される効果がある。As described above, according to the present invention, a stepped portion is formed on the side surface of a semiconductor element, and a lead frame is bonded to the stepped portion using a fixing agent made of an insulating organic material, thereby eliminating warpage of the semiconductor element and reducing stress. It has a soothing effect.
第１図（ａ）はこの発明の一実施例による半導体装置を
示す平面図、第１図（ｂ）は第１図（ａ）のＩ−■線断
面図、第２図（ａＨｂ）は第１図の実施例に用いられる
半導体素子の側面図及び斜視図、第３図はこの発明の他
の実施例を示す半導体装置の平面図、第４図（ａ）は従
来の半導体装置を示す平面図、第４図（ｂ）は第４図（
ａ）のＩＶ−ＩＶ線断面図、第５図は従来の半導体装置
を示す平面図である。
図において、１は半導体素子、２は段差部側面、３は段
差部上面、４はリードフレーム、６は結線、８は固定剤
である。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1(a) is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a cross-sectional view taken along line I-■ in FIG. 1(a), and FIG. 1 is a side view and a perspective view of a semiconductor element used in the embodiment, FIG. 3 is a plan view of a semiconductor device showing another embodiment of the present invention, and FIG. 4(a) is a plan view showing a conventional semiconductor device. Figure 4(b) is shown in Figure 4(b).
FIG. 5 is a sectional view taken along line IV-IV in a) and a plan view showing a conventional semiconductor device. In the figure, 1 is a semiconductor element, 2 is a side surface of a stepped portion, 3 is an upper surface of a stepped portion, 4 is a lead frame, 6 is a wire connection, and 8 is a fixing agent. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ドフレームを絶縁性の有機材料からなる固定剤により接
合したことを特徴とする半導体装置。1. A semiconductor device, characterized in that a step portion is formed on a side surface of a semiconductor element, and a lead frame is bonded to the step portion using a fixing agent made of an insulating organic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28597788A JPH02130950A (en) | 1988-11-11 | 1988-11-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28597788A JPH02130950A (en) | 1988-11-11 | 1988-11-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02130950A true JPH02130950A (en) | 1990-05-18 |
Family
ID=17698423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28597788A Pending JPH02130950A (en) | 1988-11-11 | 1988-11-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02130950A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5475259A (en) * | 1991-10-17 | 1995-12-12 | Fujitsu Limited | Semiconductor device and carrier for carrying semiconductor device |
-
1988
- 1988-11-11 JP JP28597788A patent/JPH02130950A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5475259A (en) * | 1991-10-17 | 1995-12-12 | Fujitsu Limited | Semiconductor device and carrier for carrying semiconductor device |
| US5637923A (en) * | 1991-10-17 | 1997-06-10 | Fujitsu Limited | Semiconductor device, carrier for carrying semiconductor device |
| US5666064A (en) * | 1991-10-17 | 1997-09-09 | Fujitsu Limited | Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device |
| US5736428A (en) * | 1991-10-17 | 1998-04-07 | Fujitsu Limited | Process for manufacturing a semiconductor device having a stepped encapsulated package |
| US5750421A (en) * | 1991-10-17 | 1998-05-12 | Fujitsu Limited | Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device |
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