JPH06244335A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH06244335A JPH06244335A JP2458193A JP2458193A JPH06244335A JP H06244335 A JPH06244335 A JP H06244335A JP 2458193 A JP2458193 A JP 2458193A JP 2458193 A JP2458193 A JP 2458193A JP H06244335 A JPH06244335 A JP H06244335A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- resin
- lead frame
- semiconductor device
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リードフレームを用い
て組立てた樹脂封止型半導体装置、特にリードフレーム
の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device assembled using a lead frame, and more particularly to a lead frame structure.
【０００２】[0002]
【従来の技術】まず、本発明の実施対象となる樹脂封止
型半導体装置，およびその組立てに用いるリードフレー
ムの従来構造を図５，図６に示す。各図において、１は
半導体チップ、２はリードフレーム、３は樹脂パッケー
ジ、４は半導体チップ１と外部リード２ｂとの間を接続
したボンディングワイヤであり、金属製リボンで作られ
たリードフレーム２には半導体チップ１を搭載する平坦
面なダイパッド２ａ、外部リード２ｂ、タイバー２ｃが
パターン形成されている。2. Description of the Related Art First, FIGS. 5 and 6 show a conventional structure of a resin-sealed semiconductor device to which the present invention is applied and a lead frame used for assembling the same. In each drawing, 1 is a semiconductor chip, 2 is a lead frame, 3 is a resin package, 4 is a bonding wire connecting between the semiconductor chip 1 and the external lead 2b, and is a lead frame 2 made of a metal ribbon. Has a flat die pad 2a on which the semiconductor chip 1 is mounted, external leads 2b, and tie bars 2c.
【０００３】かかる半導体装置を組立てるには、まずリ
ードフレーム２に対し、ダイパッド２ａの定位置に半導
体チップ１をマウントし、続いて半導体チップ１と外部
リード２ｂの間にワイヤ４をボンディングした後に、ト
ランスファモールドにより樹脂パッケージ３を成形して
半導体チップ１を樹脂封止し、さらにタイバーカットを
施して図１の樹脂封止型半導体装置を完成する。In order to assemble such a semiconductor device, first, the semiconductor chip 1 is mounted on the lead frame 2 at a fixed position of the die pad 2a, and then the wire 4 is bonded between the semiconductor chip 1 and the external lead 2b. The resin package 3 is molded by transfer molding, the semiconductor chip 1 is resin-sealed, and tie bar cutting is performed to complete the resin-sealed semiconductor device of FIG.
【０００４】[0004]
【発明が解決しようとする課題】ところで、前記した従
来構造のままでは、組立時，およびプリント配線板への
製品の取付け時に次記のような不具合が多く発生する。
すなわち、リードフレーム２を採用した半導体装置で
は、樹脂パッケージ３のモールド工程，あるいは製品を
プリント配線板へねじ止めなどで取付ける際に、リード
フレームのダイパッドに大きな熱的，ないし機械的なス
トレスが加わる。このためにリードフレームの板厚が薄
いと熱的，機械的なストレスでダイパッドが変形（湾
曲）し、このためにダイパッドにマウントした半導体チ
ップに大きな応力が働いてチップ割れの生じることがあ
る。このチップ割れはリードフレームの板厚が薄くなる
ほど発生率が高く、このことが半導体装置の製品良品率
を低める大きな原因となっている。By the way, with the conventional structure as described above, the following problems often occur during assembly and mounting of the product on the printed wiring board.
That is, in the semiconductor device employing the lead frame 2, a large thermal or mechanical stress is applied to the die pad of the lead frame during the molding process of the resin package 3 or when the product is attached to the printed wiring board by screwing or the like. . For this reason, when the lead frame is thin, the die pad is deformed (curved) due to thermal and mechanical stress, which may cause a large stress on the semiconductor chip mounted on the die pad to cause chip cracking. The occurrence of chip cracks increases as the plate thickness of the lead frame becomes thinner, and this is a major cause of lowering the non-defective product rate of semiconductor devices.
【０００５】本発明は上記の点にかんがみなされたもの
であり、リードフレームのダイパッドに簡単な追加加工
を施すことにより、前記課題を解決してチップ割れの発
生を抑えた信頼性の高い樹脂封止型半導体装置を提供す
ることを目的とする。The present invention has been made in view of the above points, and by subjecting the die pad of the lead frame to a simple additional process, the above problems are solved and a highly reliable resin encapsulation that suppresses the occurrence of chip cracks. An object is to provide a static semiconductor device.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置においては、リードフレームの
ダイパッドに対し、チップ搭載部の周辺に曲げ剛性を高
める補強部を形成するものとする。また、前記構成にお
ける補強部は、チップ搭載部を取り囲んでダイパッドの
板面に凹ないし凸状の溝付け加工を施すか、あるいはチ
ップ搭載部を取り囲んでダイパッドの板面に台形状の段
付け加工を施すかして形成するものとする。In order to achieve the above object, in a semiconductor device of the present invention, a reinforcing portion for enhancing bending rigidity is formed around a chip mounting portion with respect to a die pad of a lead frame. . In addition, the reinforcing portion in the above-mentioned configuration encloses the chip mounting portion and performs grooved or convex groove processing on the plate surface of the die pad, or surrounds the chip mounting portion and forms a trapezoidal step on the plate surface of the die pad. Shall be formed.
【０００７】[0007]
【作用】上記のようにリードフレームのダイパッドに補
強部を形成したことにより、ダイパッドの曲げ剛性が増
し、熱的，機械的な曲げストレスに対して十分な抗力が
働く。これにより、樹脂パッケージのモールド形成，あ
るいはプリント配線板への製品取付け時に加わる熱的，
機械的な曲げストレスが原因で、ダイパッドに搭載した
半導体チップに割れが生じるのを回避できる。By forming the reinforcing portion on the die pad of the lead frame as described above, the bending rigidity of the die pad is increased and a sufficient resistance acts against the thermal and mechanical bending stress. As a result, the heat generated when molding the resin package or mounting the product on the printed wiring board,
It is possible to prevent the semiconductor chip mounted on the die pad from cracking due to mechanical bending stress.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。なお、実施例の図中で図６に対応する同一部材に
は同じ符号が付してある。図１（ａ）〜（ｃ）におい
て、半導体チップ１をマウントしたリードフレーム２の
ダイパッド２ａに対して、その板面にはチップ搭載部を
取り囲んで凸状を呈するように補強部２ｄが溝付け加工
（プレス加工）によって膨出形成されている。この補強
部２ｄは、リードフレーム２をプレスにより打ち抜く際
に同時に形成することができる。なお、その他の構造は
図６と同様である。Embodiments of the present invention will be described below with reference to the drawings. In the drawings of the embodiments, the same members corresponding to FIG. 6 are designated by the same reference numerals. In FIGS. 1A to 1C, with respect to the die pad 2a of the lead frame 2 on which the semiconductor chip 1 is mounted, a reinforcing portion 2d is grooved on the plate surface so as to surround the chip mounting portion and have a convex shape. The bulge is formed by processing (pressing). The reinforcing portion 2d can be formed at the same time when the lead frame 2 is punched by a press. The other structure is the same as that of FIG.
【０００９】かかる構成により、凸状の補強部２ｄがダ
イパッド２ａの曲げに対する剛性を高めるように補強リ
ブとして機能する。したがって、熱的，機械的ストレス
によるダイパッド自身の変形，並びにダイパッド２ａの
変形に起因する半導体チップ１のチップ割れが回避でき
る。図２，図３は先記した図１の応用実施例を示すもの
であり、図２の構成では、補強部２ｄとしてダイパッド
２ａの板面にはチップ搭載部を取り囲んで凹状の溝付け
加工が施されている。さらに、図３ではチップ搭載部を
取り囲むように台形状の段付き加工が施されており、い
ずれの構成でも図１の構造と同等な効果を奏する。With this structure, the convex reinforcing portion 2d functions as a reinforcing rib so as to increase the rigidity of the die pad 2a against bending. Therefore, it is possible to avoid deformation of the die pad itself due to thermal and mechanical stress, and chip cracking of the semiconductor chip 1 due to deformation of the die pad 2a. 2 and 3 show the application example of FIG. 1 described above, and in the configuration of FIG. 2, a concave groove is formed around the chip mounting portion on the plate surface of the die pad 2a as the reinforcing portion 2d. It has been subjected. Further, in FIG. 3, a trapezoidal stepped process is performed so as to surround the chip mounting portion, and any configuration has the same effect as the structure of FIG.
【００１０】図４はリードフレームの板厚と半導体チッ
プの割れ発生率との関係を表したものである。すなわ
ち、発明者等はリードフレーム（ダイパッド）の板厚を
様々に変えて製作した従来構造，および本発明の構造に
よる樹脂封止型半導体装置を試料として半田耐熱試験を
行った後、樹脂パッケージを分解してダイパッドに搭載
した半導体チップの破損発生状況を調査した。その結果
によれば、図６に示した従来構造ではリードフレームの
板厚が１mm以下であるとチップ割れ発生率が高くなるの
に対し、本発明の構造を採用したものでは、チップ割れ
発生率が大幅に改善されることが確認された。FIG. 4 shows the relationship between the thickness of the lead frame and the crack occurrence rate of the semiconductor chip. That is, the inventors of the present invention conducted a solder heat resistance test using a resin-sealed semiconductor device having a conventional structure manufactured by changing the plate thickness of a lead frame (die pad) variously, and a resin-sealed semiconductor device having the structure of the present invention, and then tested the resin package. The disassembly state of the semiconductor chip mounted on the die pad was investigated. According to the result, in the conventional structure shown in FIG. 6, the chip crack occurrence rate is high when the lead frame plate thickness is 1 mm or less, whereas in the conventional structure shown in FIG. Was confirmed to be significantly improved.
【００１１】[0011]
【発明の効果】以上述べたように、本発明の構成によれ
ば、リードフレームのダイパッドに簡易な補強部を形成
したことにより、半導体装置の樹脂封止工程，あるいは
製品をプリント配線板にねじ止めなどで取付ける際に加
わる熱的，機械的ストレスに対するダイパッドの曲げ抗
力を高めてダイパッドに搭載した半導体チップのチップ
割れを確実に防ぐことができ、これにより樹脂封止型半
導体装置の信頼性が大幅に向上する。As described above, according to the structure of the present invention, by forming the simple reinforcing portion on the die pad of the lead frame, the resin sealing process of the semiconductor device or the product is screwed onto the printed wiring board. By increasing the bending resistance of the die pad against the thermal and mechanical stress applied when mounting it with a stopper, etc., it is possible to reliably prevent chip cracking of the semiconductor chip mounted on the die pad, which improves the reliability of the resin-sealed semiconductor device. Greatly improved.
【図１】本発明実施例の構成図であり、（ａ）は半導体
チップをマウントしたリードフレームの平面図、（ｂ),
（ｃ）はそれぞれ（ａ）図における矢視Ａ−Ａ，Ｂ−Ｂ
断面図FIG. 1 is a configuration diagram of an embodiment of the present invention, (a) is a plan view of a lead frame on which a semiconductor chip is mounted, (b),
(C) is the arrow AA, BB in the figure (a), respectively.
Cross section
【図２】図１の応用実施例を示すリードフレームの断面
図FIG. 2 is a sectional view of a lead frame showing an application example of FIG.
【図３】図２と異なる応用実施例を示すリードフレーム
の断面図FIG. 3 is a sectional view of a lead frame showing an application example different from that of FIG.
【図４】半田耐熱試験結果より求めたリードフレームの
板厚と半導体チップのチップ割れ発生率との関係を表す
図FIG. 4 is a diagram showing the relationship between the lead frame thickness obtained from the solder heat resistance test results and the chip crack occurrence rate of the semiconductor chip.
【図５】本発明の実施対象となる樹脂封止型半導体装置
の外観図FIG. 5 is an external view of a resin-encapsulated semiconductor device to which the present invention is applied.
【図６】樹脂封止型半導体装置の従来構成図であり、
（ａ）は半導体チップをマウントしたリードフレームの
平面図、（ｂ）は同側面図FIG. 6 is a conventional configuration diagram of a resin-sealed semiconductor device,
(A) is a plan view of a lead frame on which a semiconductor chip is mounted, and (b) is a side view of the same.
１ 半導体チップ ２ リードフレーム ２ａ ダイパッド ２ｂ 外部リード ２ｃ タイバー ２ｄ 補強部 ３ 樹脂パッケージ 1 semiconductor chip 2 lead frame 2a die pad 2b external lead 2c tie bar 2d reinforcing portion 3 resin package
Claims (3)
プをマウントし、その周域を樹脂封止してなる樹脂封止
型半導体装置において、リードフレームのダイパッドに
対し、チップ搭載部の周辺に曲げ剛性を高める補強部を
形成したことを特徴とする樹脂封止型半導体装置。1. A resin-sealed semiconductor device in which a semiconductor chip is mounted on a die pad of a lead frame, and the peripheral area of the semiconductor chip is resin-sealed. Flexural rigidity is provided around the chip mounting portion with respect to the die pad of the lead frame. A resin-encapsulated semiconductor device, characterized in that a reinforcing portion is formed.
部として、チップ搭載部を取り囲んでダイパッドの板面
に凹ないし凸状の溝付け加工を施したことを特徴とする
樹脂封止型半導体装置。2. The resin-encapsulated semiconductor according to claim 1, wherein, as a reinforcing portion, a concave or convex groove is formed on the plate surface of the die pad surrounding the chip mounting portion. apparatus.
部として、チップ搭載部を取り囲んでダイパッドの板面
に台形状の段付け加工を施したことを特徴とする樹脂封
止型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein as a reinforcing portion, a trapezoidal step is formed on the plate surface of the die pad surrounding the chip mounting portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2458193A JPH06244335A (en) | 1993-02-15 | 1993-02-15 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2458193A JPH06244335A (en) | 1993-02-15 | 1993-02-15 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06244335A true JPH06244335A (en) | 1994-09-02 |
Family
ID=12142134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2458193A Pending JPH06244335A (en) | 1993-02-15 | 1993-02-15 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06244335A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100335480B1 (en) * | 1999-08-24 | 2002-05-04 | 김덕중 | Leadframe using chip pad as heat spreading path and semiconductor package thereof |
| KR100771233B1 (en) * | 2000-08-21 | 2007-10-29 | 페어차일드코리아반도체 주식회사 | Semiconductor package for high power dissipation |
-
1993
- 1993-02-15 JP JP2458193A patent/JPH06244335A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100335480B1 (en) * | 1999-08-24 | 2002-05-04 | 김덕중 | Leadframe using chip pad as heat spreading path and semiconductor package thereof |
| KR100771233B1 (en) * | 2000-08-21 | 2007-10-29 | 페어차일드코리아반도체 주식회사 | Semiconductor package for high power dissipation |
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