JPS6197842A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6197842A
JPS6197842A JP59219002A JP21900284A JPS6197842A JP S6197842 A JPS6197842 A JP S6197842A JP 59219002 A JP59219002 A JP 59219002A JP 21900284 A JP21900284 A JP 21900284A JP S6197842 A JPS6197842 A JP S6197842A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor element
substrate
chip
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59219002A
Other languages
Japanese (ja)
Inventor
Mitsuoki Fujita
藤田　光興
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59219002A priority Critical patent/JPS6197842A/en
Publication of JPS6197842A publication Critical patent/JPS6197842A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enable the prevention of cracks of the semiconductor element by a method wherein a semiconductor chip of the same material and different crystal orientation is interposed between a semiconductor element and a substrate. CONSTITUTION:An Si semiconductor chip 6 is arranged on a substrate 2 of Fe-Ni alloy, and a semiconductor element 1 thereon, which are then integrally welded with a mount material 3. An Si semiconductor chip 6 is arranged on a ceramic substrate 7, and a semiconductor element 1 thereon, which are then welded with a mount material 3. If the semiconductor element 1 is silicon, the semiconductor chip 6 is made of silicon and is made different in crystal orientation. Besides, if the chip 6 is allowed to have a cross section of almost the same shape as that of the semiconductor element 1, the generation of cracks due to thermal shock in the part of contact between the element 1 and the chip 6 can be perfectly prevented in the point of shape.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置にに、構造上の分類から、プラスチック封止
＆トセラミック型とがある。谷型の構造を第２図に例示
しである。Semiconductor devices are classified into plastic-sealed and ceramic types based on their structural classification. An example of the valley-shaped structure is shown in FIG.

グラスチック封止型は第２図（幻に示すように半導体素
子１を鉄・ニッケル合金の基板２上にマウント材３で溶
接する。リード４と半導体素子１とをボンディングワイ
ヤで接続してからプラスチック樹脂５で封止する。セラ
ミック型は第２図（ｂ）に示すようにセラミックの基板
７に同様に半導体素子１を溶接後、ボンディングワイヤ
でリード１０と接続する。この型では、セラミックの基
板７は容器の一部をなし金属キャップ８と圧着して封じ
てｂる。９は圧着部である。For the glass-sealed type, as shown in Figure 2, a semiconductor element 1 is welded onto an iron-nickel alloy substrate 2 using a mounting material 3. After connecting the leads 4 and the semiconductor element 1 with bonding wires, The ceramic mold is sealed with a plastic resin 5. As shown in FIG. The substrate 7 forms a part of the container and is sealed by being crimped to a metal cap 8. 9 is a crimping part.

上記構造で、半導体素子１は鉄・ニッケルの基板２ある
いはセラミックの基板７と溶接している。半導体素子１
の材質はシリコンであり、上記基板２．７と熱膨張係数
の差異があるため、熱ストレスが加わった場合、基板２
，７の接触面から半導体素子１０表面へ向ってクラック
が発生し故障となることが多かった。In the above structure, the semiconductor element 1 is welded to the iron/nickel substrate 2 or the ceramic substrate 7. Semiconductor element 1
The material of the substrate 2 is silicon, which has a different coefficient of thermal expansion from the substrate 2.7 above, so when thermal stress is applied, the substrate 2
, 7 toward the surface of the semiconductor element 10, often resulting in failure.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、上記の欠点を除去し、熱ストレスに起
因する半導体素子のクラック事故を防ぐ淘造全有する半
導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates the above-mentioned drawbacks and has a complete structure that prevents cracking of semiconductor elements caused by thermal stress.

Ｃ問題点を解決するための手段〕 本発明においては、半導体素子を搭載する基板と前記半
導体素子との間に、前記半導体素子と同一材質で結晶方
位を異にする半導体片を配設し、互いに接着して一体構
造にすることによって上記問題を解決している。Means for Solving Problem C] In the present invention, a semiconductor piece made of the same material as the semiconductor element and having a different crystal orientation is disposed between a substrate on which a semiconductor element is mounted and the semiconductor element, The above problem is solved by bonding them together to form an integral structure.

〔作　用〕[For production]

本発明においては、半導体素子と半導体片とは同一材質
であるから熱膨張係数が同一であるノテ、熱ショックに
よシ半導体素子にクラックが生ずることがない。半導体
片と基板とは熱膨張係数が異なるので、熱ショックによ
り半導体片にクラックが生ずることがある。しかし、半
導体片と半導体素子とは結晶方位を異にするから、仮に
半導体片にクラックが生じても半導体素子にまでクラッ
クが進行することがない。In the present invention, since the semiconductor element and the semiconductor piece are made of the same material and have the same coefficient of thermal expansion, the semiconductor element will not crack due to thermal shock. Since the semiconductor piece and the substrate have different coefficients of thermal expansion, cracks may occur in the semiconductor piece due to thermal shock. However, since the semiconductor piece and the semiconductor element have different crystal orientations, even if a crack occurs in the semiconductor piece, the crack will not propagate to the semiconductor element.

〔実　施　例〕〔Example〕

第１図を参照して本発明の実施例につき説明する。第１
図（−）はプラスチック封止型、同図（ｂ）はセラミッ
ク型に本発明を適用した実施例の断面図である、第１図
（、）においては、鉄・ニッケル合金゛の基板２の上に
シリコン半導体片６、その上に半導体素子１を配置し、
相互の間をマウント材３で溶着して一体としている。第
１図（ｂ）では、セラミック基板Ｚ上にシリコン半導体
片６、その上に半導体素子１を配置し、マウント材３で
溶着している。An embodiment of the present invention will be described with reference to FIG. 1st
Figure (-) is a sectional view of an embodiment in which the present invention is applied to a plastic sealed type, and Figure (b) is a sectional view of an embodiment in which the present invention is applied to a ceramic type. A silicon semiconductor piece 6 is placed on top, a semiconductor element 1 is placed on top of the silicon semiconductor piece 6,
They are welded together with a mounting material 3 to make them integral. In FIG. 1(b), a silicon semiconductor piece 6 is placed on a ceramic substrate Z, and a semiconductor element 1 is placed thereon, and welded with a mounting material 3.

半導体片６は、半導体素子１がシリコンならば、同じく
シリコンとし、結晶方位を異にしている。また半導体片
６は半導体素子１と略々、同じ形状の断面をもつように
すれば、半導体素子１と半導体片６との接触部に熱ショ
ックによるクラックが生ずることは形状の面からいって
も、さらに完全に防ぐことができる。If the semiconductor element 1 is made of silicon, the semiconductor piece 6 is also made of silicon, but has a different crystal orientation. Furthermore, if the semiconductor chip 6 is made to have a cross section that has approximately the same shape as the semiconductor chip 1, cracks due to thermal shock will not occur at the contact area between the semiconductor chip 1 and the semiconductor chip 6, even from the viewpoint of the shape. , can even be completely prevented.

〔発明の効果〕〔Effect of the invention〕

以上、詳しく説明したように、半導体素子と　　　゛）
基板との間に同一材質で結晶方位の異なる半導体片全介
在させることにより、半導体素子のクラックを防止する
ことができる。As explained in detail above, semiconductor elements and ゛)
By interposing all semiconductor pieces made of the same material and having different crystal orientations between the semiconductor element and the substrate, cracks in the semiconductor element can be prevented.

本発明は半導体素子としてシリコンに限らず、金属間化
合物半導体のデバイスなどにも適用できることはいうま
でもない。It goes without saying that the present invention is applicable not only to silicon as a semiconductor element but also to intermetallic compound semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例の断面図、第２図は従来例の断
面図である。 １・・・半導体素子、 ２・・・（鉄・ニッケル合金）基板、 ３・・・マウント材、４．１０・・・＋７−と５・・・
プラスチック樹脂、　　６・・・半導体片７・・・（セ
ラミック）基板、　　８・・・金属キャップ、９・・・
圧着部。 特許出願人　　日本電気株式会社 第　１　ｎ 、ｂノ １：　季４仏未予 ２．７：　　基板 ３：　　マウント、トイ ６二　半導に＊片FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1...Semiconductor element, 2...(Iron-nickel alloy) substrate, 3...Mount material, 4.10...+7- and 5...
Plastic resin, 6... Semiconductor piece 7... (ceramic) substrate, 8... Metal cap, 9...
Crimping part. Patent Applicant NEC Corporation No. 1 n, b no. 1: Season 4 Unprepared 2.7: Substrate 3: Mount, Toy 62 * Piece on semiconductor

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子を搭載する基板と前記半導体素子との
間に、前記半導体素子と同一材質で結晶方位を異にする
半導体片を配設し、互いに接着してなる一体の構造を有
することを特徴とする半導体装置。(1) Semiconductor pieces made of the same material as the semiconductor element but having different crystal orientations are disposed between the substrate on which the semiconductor element is mounted and the semiconductor element, and are bonded together to form an integrated structure. Characteristic semiconductor devices. （２）前記半導体片の半導体素子と接する面の形状が前
記半導体素子の底面と略々同一である特許請求の範囲の
第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the shape of the surface of the semiconductor piece in contact with the semiconductor element is substantially the same as the bottom surface of the semiconductor element.
JP59219002A 1984-10-18 1984-10-18 Semiconductor device Pending JPS6197842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59219002A JPS6197842A (en) 1984-10-18 1984-10-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59219002A JPS6197842A (en) 1984-10-18 1984-10-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6197842A true JPS6197842A (en) 1986-05-16

Family

ID=16728723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59219002A Pending JPS6197842A (en) 1984-10-18 1984-10-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6197842A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06302573A (en) * 1993-04-16 1994-10-28 Dainippon Screen Mfg Co Ltd Board processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06302573A (en) * 1993-04-16 1994-10-28 Dainippon Screen Mfg Co Ltd Board processor

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