JPS5834932A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5834932A
JPS5834932A JP56133480A JP13348081A JPS5834932A JP S5834932 A JPS5834932 A JP S5834932A JP 56133480 A JP56133480 A JP 56133480A JP 13348081 A JP13348081 A JP 13348081A JP S5834932 A JPS5834932 A JP S5834932A
Authority
JP
Japan
Prior art keywords
element substrate
substrate
resin film
support substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56133480A
Other languages
Japanese (ja)
Inventor
Hisaharu Sakurai
桜井　寿春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56133480A priority Critical patent/JPS5834932A/en
Publication of JPS5834932A publication Critical patent/JPS5834932A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

PURPOSE:To reduce distortion produced in an element substrate by a method wherein a heat-resisting resin film is fixed by an adhesive agent between the element substrate and a support substrate therefor. CONSTITUTION:Thermosetting adhesive coatings 12 and 14, of an epoxy resin for example, are applied to the both surfaces of a heat-resisting film 13. The film 13 is then placed on a support substrate 11 and is overlaid with an element substrate 15, and the lamination is heated under pressure. The lamination solidifies, with the resin film 13 sandwiched between the element substrate 15 and the support substrate 11. Most of the stress generated between the two substrates 15 and 11 is absorbed by the resin film 13 and therefore little stress is expected to remain within the element substrate 15.

Description

【発明の詳細な説明】 この発明は支持基板に素子基板が取り付けられている半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which an element substrate is attached to a support substrate.

第１図（Ａ）　、　（Ｂ）に従来の支持基板に対する素
子基板の取り付は方法を示す。なお、第１図（Ａ）はそ
の平面図であり、同図（Ｂｌは同図（Ａｌのｘ−ｘ’に
おける断面図である。図中、１は支持基板を示している
。この支持基板１には接合部材２を介して素子基板３が
接合されている。このとき、素子基板３．接合部材２．
支持基ｇ１１それぞれの素材の線膨張係数、ヤング率等
がそれぞれ異なるために素子基＠３には、接合温度と実
使用温度との差により歪が生じる。この素子基板３に生
じる歪は、素子基′８３．接合部材２．支持基板１の素
材の線膨張係数の差が小さい程小さい事は明らかである
。FIGS. 1A and 1B show a conventional method for attaching an element substrate to a support substrate. In addition, FIG. 1(A) is a plan view thereof, and FIG. An element substrate 3 is bonded to the bonding member 2 through the bonding member 2. At this time, the element substrate 3. bonding member 2.
Since the materials of the support base g11 have different linear expansion coefficients, Young's moduli, etc., distortion occurs in the element base @3 due to the difference between the bonding temperature and the actual operating temperature. This strain occurring on the element substrate 3 is caused by the strain on the element substrate '83. Joining member 2. It is clear that the smaller the difference in the linear expansion coefficients of the materials of the support substrate 1, the smaller the difference.

したがつ゛て、従来より上記の事を考慮して、支持基＠
１の素材として線膨張係数が素子基板３に近い４２アロ
イ、コバール等が用いられてきた。しかしながら、これ
らの材料は熱伝導率が小さく、素子基板３が取り付けら
れた支持基板１を樹脂封止した場合には、熱抵抗が大き
くなってしまう。そこで、熱抵抗を小さくするために、
熱伝導率の大きい銅系の素材を用いることが考えられる
が、銅系の素材は線膨張係数が大きいため、素子基板内
に生じる歪が大きくなり、最悪の場合には素子基板に割
れが生じてしまう。Therefore, considering the above, the support base @
42 alloy, Kovar, etc., which have a coefficient of linear expansion close to that of the element substrate 3, have been used as the material for the element substrate 1. However, these materials have low thermal conductivity, and when the support substrate 1 to which the element substrate 3 is attached is sealed with resin, the thermal resistance becomes large. Therefore, in order to reduce thermal resistance,
It is possible to use a copper-based material with high thermal conductivity, but since copper-based materials have a large coefficient of linear expansion, the strain that occurs within the element substrate will be large, and in the worst case, the element substrate will crack. It ends up.

第１表に各種素材の諸性質および樹脂封止した場合の熱
抵抗の一例を示す。Table 1 shows an example of the properties of various materials and the thermal resistance when resin-sealed.

第　　１　　表 たとえば、４２アロイを素材とした支持基板１ａを用い
た場合、素子基板３との間に生じる変形が、第２図（Ａ
）に示す程度であるとすると、銅系素材の支持基板１ｂ
を用いた場合の素子基板３との間に生じる変形は、第２
図（Ｂ）に示すようになる。すなわち、銅系素、材の支
持基板１を用いた場合の方がより大きな変形を生じる。Table 1 For example, when using a support substrate 1a made of 42 alloy, the deformation that occurs between it and the element substrate 3 is as shown in Figure 2 (A
), the support substrate 1b made of copper-based material
The deformation that occurs between the element substrate 3 and the second
The result is as shown in Figure (B). That is, larger deformation occurs when the support substrate 1 is made of a copper-based material.

なお、素子基板３には線膨張差による収縮とバイメタル
効果による反りが生じる。Note that the element substrate 3 undergoes shrinkage due to the difference in linear expansion and warpage due to the bimetal effect.

第２表は、３ｓＢ″′の素子基板を４２アロイあるいは
燐脱酸鋼を素材とした支持基板に、各？＋；接着材料を
用いて接着した時に、素子基政表面に生じる応力の大き
さを示している。なお、この表において、＋は引張応力
を示し、−は圧縮応力を示している。Table 2 shows the magnitude of stress generated on the element substrate surface when a 3sB'' element substrate is bonded to a supporting substrate made of 42 alloy or phosphorus-deoxidized steel using various adhesive materials. In this table, + indicates tensile stress and - indicates compressive stress.

この発明は上記のような事情に鑑みてなされたもので、
素子基板を支持基板に取り付けたききの素子基板に生じ
る歪を緩和することができる半導体装置を提供すること
を目的とする。This invention was made in view of the above circumstances,
It is an object of the present invention to provide a semiconductor device that can alleviate strain occurring in an element substrate when the element substrate is attached to a support substrate.

以下、図面を参照してこの発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第３図はこの発明の一実施例の半導体装置を示す断面図
である。図中、１１は支持基板で、この支持基板１１に
は、接着剤１２を介して例えばポリイミド樹脂からなる
高耐熱性の樹脂フィルム１３が接合されている。そして
、この樹脂フィルム１３の上面側には、接着剤１４を介
して樹脂フィルム１３の主面よりその主面の面積が小さ
い素子基板１５が接合されている。FIG. 3 is a sectional view showing a semiconductor device according to an embodiment of the present invention. In the figure, reference numeral 11 denotes a support substrate, and a highly heat-resistant resin film 13 made of, for example, polyimide resin is bonded to the support substrate 11 via an adhesive 12. Further, an element substrate 15 whose main surface area is smaller than the main surface of the resin film 13 is bonded to the upper surface side of the resin film 13 via an adhesive 14 .

次に、上記実施例の製造工程を説明する。高耐熱性の樹
脂フィルム１３の両面に例えばエポキシ樹脂からなる熱
硬化性の接着剤１２．１４を塗布し、これを支持基板１
１にのせた後、その上に素子基板１５をのせ、加圧加熱
することにより、素子基板１５および支持基板１１間に
、樹脂フィルム１３が介在されたかたちで接着される。Next, the manufacturing process of the above embodiment will be explained. A thermosetting adhesive 12.14 made of, for example, epoxy resin is applied to both sides of the highly heat-resistant resin film 13, and this is applied to the supporting substrate 1.
1, the element substrate 15 is placed thereon and heated under pressure to bond the element substrate 15 and the support substrate 11 with the resin film 13 interposed therebetween.

なお、支持基板１１にエポキシペーストからなる接着剤
により樹脂フィルム１３を接着した後、樹脂フィルム１
３と素子基ｉ＆１５をエポキシペーストにより接着して
もよい。Note that after bonding the resin film 13 to the support substrate 11 with an adhesive made of epoxy paste, the resin film 1
3 and the element base i&15 may be bonded together using epoxy paste.

このような半導体装置では、素子基板１５と支持基板１
１間に生じる応力を樹脂フィルム１３がほとんど吸収し
てしまうため、素子基板１５内にほとんど歪が残ること
はない。また、上記樹脂フィルム１３の厚さが増せば増
すほど、素子基板１５内に残る歪は少なくなる。In such a semiconductor device, the element substrate 15 and the support substrate 1
Since the resin film 13 absorbs most of the stress generated between the elements 1 and 1, almost no strain remains in the element substrate 15. Further, as the thickness of the resin film 13 increases, the strain remaining in the element substrate 15 decreases.

さらに、従来では、第２図（Ａ）　、　（Ｂｌに示す様
な状態で樹脂封止した場合、素子基板内では極めて複雑
な応力分布を示すことになるが、上記実施例の場合、樹
脂封止したとしても樹脂フィルム１３が変形して素子基
板１５内に複雑な応力を残すことがない。Furthermore, conventionally, when resin sealing is performed in the state shown in FIGS. Even if the device is stopped, the resin film 13 will not be deformed and no complicated stress will remain in the element substrate 15.

以上述べたようにこの発明によれば、素子基板を支持基
板に取り付けたときの素子基板に生じる歪を緩和させる
ことができる半導体装置を提供することができる。As described above, according to the present invention, it is possible to provide a semiconductor device that can alleviate the strain that occurs in the element substrate when the element substrate is attached to the support substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａ）は従来の半導体装置の平面図、第１図（Ｂ
ｌは第１図（Ａ）におけるｘ　−ｘ’における断面図、
第２図（Ａｌ　、　（Ｂｌはそれぞれ支持基板に異なっ
た材料を用いた場合の変形を示す図、第３図はこの発明
の一実施例の断面図である。 １１・・・支持基板、１２．１４・・・接着部、１３・
・・樹脂フィルム、１５・・・素子基板。 出願人代理人　弁理士　鈴　江　武　章節１図 （Ｂ） 第２図 （Ａ）　　　　　　　（Ｂ） 第”３図 ５FIG. 1(A) is a plan view of a conventional semiconductor device, and FIG. 1(B) is a plan view of a conventional semiconductor device.
l is a cross-sectional view at x-x' in FIG. 1(A),
FIG. 2 (Al, (Bl) is a diagram showing deformation when different materials are used for the support substrate, respectively, and FIG. 3 is a cross-sectional view of one embodiment of the present invention. 11...Support substrate, 12 .14...adhesive part, 13.
... Resin film, 15... Element substrate. Applicant's agent Patent attorney Takeshi Suzue Chapter 1 Figure 1 (B) Figure 2 (A) (B) Figure 3 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 素子基板と支持基板間に耐熱性樹脂フィルムを接着した
状態で介在させたことを特徴とする半導体装置。A semiconductor device characterized in that a heat-resistant resin film is interposed between an element substrate and a support substrate in a bonded state.
JP56133480A 1981-08-26 1981-08-26 Semiconductor device Pending JPS5834932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56133480A JPS5834932A (en) 1981-08-26 1981-08-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56133480A JPS5834932A (en) 1981-08-26 1981-08-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5834932A true JPS5834932A (en) 1983-03-01

Family

ID=15105753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56133480A Pending JPS5834932A (en) 1981-08-26 1981-08-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5834932A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184841A (en) * 1984-10-02 1986-04-30 Toshiba Corp Enclosure of semiconductor device
JPH01162237U (en) * 1988-04-26 1989-11-10
JPH03185741A (en) * 1989-12-14 1991-08-13 Toshiba Corp Semiconductor device and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184841A (en) * 1984-10-02 1986-04-30 Toshiba Corp Enclosure of semiconductor device
JPH01162237U (en) * 1988-04-26 1989-11-10
JPH03185741A (en) * 1989-12-14 1991-08-13 Toshiba Corp Semiconductor device and manufacture thereof

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