KR20020032013A - stack-type semiconductor package - Google Patents
stack-type semiconductor package Download PDFInfo
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- KR20020032013A KR20020032013A KR1020000062866A KR20000062866A KR20020032013A KR 20020032013 A KR20020032013 A KR 20020032013A KR 1020000062866 A KR1020000062866 A KR 1020000062866A KR 20000062866 A KR20000062866 A KR 20000062866A KR 20020032013 A KR20020032013 A KR 20020032013A
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- semiconductor chip
- circuit board
- chip
- semiconductor
- wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
본 발명은 적층형 반도체 패키지에 관한 것으로서, 더욱 상세하게는 상하방향으로 적층되는 반도체칩중 가운데 위치하는 반도체칩의 하면에도 금속패턴을 형성하여 상·하면 모두를 전기적 연결에 이용하므로써 패키지가 경박단소화되도록 하는 한편, 열방출 성능을 향상시키고 적층부에서의 응력이 해소되도록 하여 신뢰성 또한 향상된 새로운 구조의 적층형 반도체 패키지를 구현한 것이다.The present invention relates to a stacked semiconductor package, and more particularly, a metal pattern is formed on a lower surface of a semiconductor chip which is stacked in the vertical direction, so that both the upper and lower surfaces are used for electrical connection. On the other hand, the stack-type semiconductor package of the new structure has been implemented to improve the heat dissipation performance and to solve the stress in the stack, thereby improving the reliability.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키면서도 메모리 용량을 증가시키기 위해 지금까지 계속 발전해오고 있다.In general, packaging technology for integrated circuits in the semiconductor industry continues to evolve to increase memory capacity while satisfying the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있고, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있으며, 메모리 용량을 증가시키기 위한 적층형 패키지 제조 기술에 대한 기술 개발 및 중요성 또한 부각되고 있는 실정이다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. In addition, the development and importance of stacked package manufacturing technology for increasing memory capacity is also emerging.
이에 따라, 여러 가지 형태의 적층형 반도체 패키지가 고안되고 있으나, 각 패키지마다 갖는 단점 또는 구조적 한계로 인해, 꾸준히 새로운 적층형 반도체 패키지에 개발이 진행되고 있다.Accordingly, various types of stacked semiconductor packages have been devised, but due to the disadvantages or structural limitations of each package, development is continuously progressing to new stacked semiconductor packages.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 상하방향으로 적층되는 반도체칩중 가운데 위치하는 반도체칩의 상·하면 모두를 전기적 연결에 이용하므로써 패키지를 경박단소화 하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce the thickness of a package by using both upper and lower surfaces of a semiconductor chip located in the middle of the semiconductor chips stacked in the vertical direction for electrical connection.
한편, 본 발명은 상기한 목적과 더불어, 열방출 성능이 향상되도록 함과 더불어 적층부에서 발생하는 응력이 해소되도록 패키지의 구조를 개선하여 신뢰성 또한 높은 새로운 구조의 적층형 반도체 패키지를 제공하는데 그 목적이 있다.On the other hand, the present invention, in addition to the above object, to improve the heat dissipation performance and to improve the structure of the package to solve the stress generated in the laminated portion to provide a highly reliable layered semiconductor package of the structure have.
도 1은 본 발명에 따른 적층형 반도체 패키지 구조를 나타낸 종단면도1 is a longitudinal sectional view showing a stacked semiconductor package structure according to the present invention;
도 2는 도 1의 제1반도체칩을 나타낸 종단면도FIG. 2 is a longitudinal cross-sectional view illustrating the first semiconductor chip of FIG. 1. FIG.
도 3은 본 발명에 따른 적층형 반도체 패키지의 다른 실시예를 나타낸 종단면도3 is a longitudinal sectional view showing another embodiment of the stacked semiconductor package according to the present invention;
도 4는 도 3의 제1반도체칩을 나타낸 종단면도4 is a longitudinal cross-sectional view illustrating the first semiconductor chip of FIG. 3.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:회로기판 2:제1반도체칩1: Circuit board 2: First semiconductor chip
3:제2반도체칩 4:제3반도체칩3: second semiconductor chip 4: third semiconductor chip
5:와이어 6a,6b,6c:플립칩 범프5: Wire 6a, 6b, 6c: Flip chip bump
7:와이어 본딩용 패드 8:플립칩 본딩용 패드7: Pad for wire bonding 8: Pad for flip chip bonding
9:몰드바디 10:솔더볼9: mold body 10: solder ball
11:회로필름 12:어드헤시브층11: Circuit film 12: Advance layer
13:보호막13: Shield
상기한 목적을 달성하기 위해, 본 발명은 중앙부에 오프닝 영역을 구비한 회로기판과, 상면에 와이어 본딩용 패드 및 플립칩 본딩용 패드가 형성되고 하면에 일정한 패턴의 금속배선이 형성되며 상기 하면이 회로기판상면에 부착되는 제1반도체칩과, 상기 제1반도체칩의 하면에 형성된 금속배선과 회로기판의 본딩부를 전기적으로 연결하는 플립칩 범프와, 상기 제1반도체칩 상면의 와이어 본딩용 패드와 회로기판의 본딩부를 전기적으로 연결하는 와이어와, 상기 제1반도체칩 상면의 와이어 본딩용 패드 내측 영역에 부착되는 제2반도체칩과, 상기 제2반도체칩과 제1반도체칩을 전기적으로 연결시키는 플립칩 범프와, 상기 회로기판 중앙부의 오프닝 영역을 통해 삽입되어 제1반도체칩의 하면에 부착되는 제3반도체칩과, 상기 제3반도체칩과 제2반도체칩을 전기적으로 연결시키는 플립칩 범프와, 상기 제1반도체칩과 제2반도체칩 및 와이어를 봉지하도록 회로기판 상면에 형성되는 몰드바디를 포함하여서 됨을 특징으로 하는 적층형 반도체 패키지가 제공된다.In order to achieve the above object, the present invention is a circuit board having an opening area in the center, a wire bonding pad and a flip chip bonding pad are formed on the upper surface and a metal pattern of a predetermined pattern is formed on the lower surface. A first semiconductor chip attached to an upper surface of the circuit board, a flip chip bump electrically connecting the metal wiring formed on the lower surface of the first semiconductor chip to a bonding portion of the circuit board, a pad for wire bonding on the upper surface of the first semiconductor chip; A wire for electrically connecting the bonding portion of the circuit board, a second semiconductor chip attached to an inner region of the wire bonding pad on the upper surface of the first semiconductor chip, and a flip for electrically connecting the second semiconductor chip and the first semiconductor chip. A chip bump, a third semiconductor chip inserted through an opening area of the center portion of the circuit board and attached to a lower surface of the first semiconductor chip, the third semiconductor chip and the second semiconductor The flip chip bumps and the stacked-layer type semiconductor package as characterized in that the hayeoseo containing the first semiconductor chip and the second semiconductor chip and the mold body, which forms the wire on the upper surface of the circuit board so that a bag is provided to electrically connect the.
이하, 본 발명의 실시예들을 첨부도면 도 1 내지 도 4를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4.
도 1은 본 발명에 따른 적층형 반도체 패키지 구조를 나타낸 종단면도이고, 도 2는 도 1의 제1반도체칩 구조를 나타낸 종단면도로서, 본 발명의 적층형 반도체패키지는, 중앙부에 사각형상의 오프닝 영역이 구비된 회로기판(1)과, 상면에 와이어 본딩용 패드(7) 및 플립칩 본딩용 패드(8)가 형성되고 하면에 일정한 패턴의 금속배선이 형성되며 상기 하면이 회로기판(1) 상면에 부착되는 제1반도체칩(2)과, 상기 제1반도체칩(2)의 하면에 형성된 금속배선과 회로기판(1)의 본딩부를 전기적으로 연결하는 플립칩 범프(6a)와, 상기 제1반도체칩(2) 상면의 와이어 본딩용 패드(7)와 회로기판(1)의 본딩부를 전기적으로 연결하는 와이어(5)와, 상기 제1반도체칩(2) 상면의 와이어 본딩용 패드(7) 내측 영역에 부착되는 제2반도체칩(3)과, 상기 제2반도체칩(3)과 제1반도체칩(2)을 전기적으로 연결시키는 플립칩 범프(6b)와, 상기 회로기판(1) 중앙부의 오프닝 영역을 통해 삽입되어 제1반도체칩(2)의 하면에 부착되는 제3반도체칩(4)과, 상기 제3반도체칩(4)과 제2반도체칩(3)을 전기적으로 연결시키는 플립칩 범프(6c)와, 상기 제1반도체칩(2)과 제2반도체칩(3) 및 와이어(5)를 봉지하도록 회로기판(1) 상면에 형성되는 몰드바디(9)를 포함하여서 됨을 특징으로 하는 적층형 반도체 패키지가 제공된다.1 is a longitudinal cross-sectional view showing a stacked semiconductor package structure according to the present invention, Figure 2 is a longitudinal cross-sectional view showing a first semiconductor chip structure of Figure 1, the stacked semiconductor package of the present invention is provided with a rectangular opening area in the center The circuit board 1, the wire bonding pad 7 and the flip chip bonding pad 8 are formed on the upper surface thereof, and metal wirings having a predetermined pattern are formed on the lower surface thereof, and the lower surface is attached to the upper surface of the circuit board 1. A first semiconductor chip 2, a flip chip bump 6a electrically connecting the metal wiring formed on the bottom surface of the first semiconductor chip 2, and a bonding portion of the circuit board 1, and the first semiconductor chip. (2) a wire 5 electrically connecting the bonding pad 7 of the upper surface to the bonding portion of the circuit board 1, and an inner region of the bonding pad 7 of the upper surface of the first semiconductor chip 2; A second semiconductor chip 3 attached to the second semiconductor chip 3 and the first semiconductor chip 2 A flip chip bump 6b for electrically connecting the second chip, a third semiconductor chip 4 inserted through an opening area of the center portion of the circuit board 1 and attached to the bottom surface of the first semiconductor chip 2, Encapsulates a flip chip bump 6c electrically connecting the third semiconductor chip 4 and the second semiconductor chip 3 with the first semiconductor chip 2, the second semiconductor chip 3, and the wire 5. There is provided a stacked semiconductor package, characterized in that it comprises a mold body (9) formed on the upper surface of the circuit board (1).
이 때, 상기 제1반도체칩(2) 하면에 형성되는 금속배선은 FAB(Fabrication) 공정 진행시 웨이퍼 상태로 형성됨이 바람직하다.At this time, the metal wiring formed on the lower surface of the first semiconductor chip 2 is preferably formed in the wafer state during the FAB (Fabrication) process.
그리고, 상기 회로기판(1) 하면에는 적층형 반도체 패키지를 마더보드(mother board)에 실장하기 위한 솔더볼(10)이 부착된다.In addition, a solder ball 10 is attached to the bottom surface of the circuit board 1 to mount the stacked semiconductor package on a motherboard.
한편, 미설명 부호 13은 보호막이다.In addition, reference numeral 13 is a protective film.
이와 같이 구성된 본 발명의 적층형 반도체 패키지 제조과정 및 작용은 다음과 같다.The manufacturing process and operation of the stacked semiconductor package of the present invention configured as described above are as follows.
먼저, 중앙부에 오프닝 영역(opening area)이 형성된 회로기판(1) 상면에 제1반도체칩(2)을 정렬시켜 부착한다.First, the first semiconductor chip 2 is aligned and attached to an upper surface of the circuit board 1 having an opening area in the center thereof.
이 때, 상기 제1반도체칩(2)은 가장자리가 회로기판(1)의 오프닝 영역 주위에 위치하도록 부착되며, 하면에 형성된 플립칩 범프(6a)가 회로기판(1)의 본딩부에 접합되어 부착된다.At this time, the first semiconductor chip 2 is attached so that an edge thereof is positioned around the opening area of the circuit board 1, and the flip chip bumps 6a formed on the bottom surface thereof are bonded to the bonding portion of the circuit board 1. Attached.
이어, 상기 제1반도체칩(2) 상면의 와이어 본딩용 패드(7) 내측 영역에는 제2반도체칩(3)을 부착하고, 상기 회로기판(1) 중앙부의 오프닝 영역을 통해서는 제3반도체칩(4)을 삽입하여 상기 제3반도체칩(4)을 제1반도체칩(2)의 하면에 부착한다.Subsequently, a second semiconductor chip 3 is attached to an inner region of the wire bonding pad 7 on the upper surface of the first semiconductor chip 2, and a third semiconductor chip is formed through an opening area of the center portion of the circuit board 1. (4) is inserted to attach the third semiconductor chip 4 to the bottom surface of the first semiconductor chip 2.
이 때, 상기 제1반도체칩(2)과 제2반도체칩(3)은 상기 제1반도체칩(2)에 형성된 플립칩 본딩용 패드(8)와 플립칩 범프(6b)와의 결합에 의해 전기적으로 연결되고, 제3반도체칩(4)은 플립칩 범프(6)에 의해 제1반도체칩(3)에 형성된 금속배선과 전기적으로 연결된다.At this time, the first semiconductor chip 2 and the second semiconductor chip 3 are electrically connected by the flip chip bonding pad 8 and the flip chip bump 6b formed on the first semiconductor chip 2. The third semiconductor chip 4 is electrically connected to the metal wires formed on the first semiconductor chip 3 by the flip chip bumps 6.
한편, 상기한 과정을 거친 후에는 제1반도체칩(2) 상면의 와이어 본딩용 패드(7)와 회로기판(1)상의 본딩부를 와이어(5)를 이용하여 전기적으로 연결한다.Meanwhile, after the above process, the wire bonding pad 7 on the upper surface of the first semiconductor chip 2 and the bonding portion on the circuit board 1 are electrically connected using the wires 5.
이에 따라, 제1반도체칩(2)과 제2반도체칩(3)은 플립칩 범프(6b)에 의해 서로 전기적으로 연결되며, 이와 더불어 제1반도체칩(2)과 제3반도체칩(4) 또한 제1반도체칩 하면에 형성된 금속배선과 플립칩 범프(6c)에 의해 서로 전기적으로 연결된다.Accordingly, the first semiconductor chip 2 and the second semiconductor chip 3 are electrically connected to each other by flip chip bumps 6b, and together with the first semiconductor chip 2 and the third semiconductor chip 4, respectively. In addition, the metal wiring and flip chip bumps 6c formed on the lower surface of the first semiconductor chip are electrically connected to each other.
즉, 상기 제1반도체칩(2)과 제2반도체칩(3) 및 제3반도체칩(4)은, 플립칩 범프(6)와 와이어(5) 및 회로기판(1) 그리고 제1반도체칩(2) 뒷면의 금속배선을 통해 서로 전기적으로 연결된 상태를 유지하게 되며, 이에 따라 패키지의 메모리 용량을 증가시킬 수 있게 된다.That is, the first semiconductor chip 2, the second semiconductor chip 3, and the third semiconductor chip 4 may include a flip chip bump 6, a wire 5, a circuit board 1, and a first semiconductor chip. (2) The metal wiring on the back side maintains the electrical connection to each other, thereby increasing the memory capacity of the package.
한편, 상기와 같이 반도체칩의 적층이 끝난 다음에는 제1반도체칩(2) 및 제2반도체칩(3)과 와이어(5) 등을 외부의 영향으로부터 보호할 수 있도록 에폭시 몰딩콤파운드를 이용하여 봉지하는 엔캡슐레이션 공정을 수행하여 몰드바디(9)를 형성하게 된다.On the other hand, after the stacking of semiconductor chips as described above, the first semiconductor chip 2, the second semiconductor chip 3 and the wire 5, etc. are sealed using an epoxy molding compound so as to protect them from external influences. The encapsulation process is performed to form the mold body 9.
그 후, 상기 회로기판(1) 하면에 마더보드에의 실장을 위한 솔더볼(10)을 부착하여 패키지를 완성한다.After that, the solder ball 10 for mounting on the motherboard is attached to the bottom surface of the circuit board 1 to complete the package.
이와 같이 구성된 본 발명의 적층형 반도체 패키는 제1반도체칩(2)의 상하 양면을 전기적 접속에 이용함에 따라 다음과 같은 장점이 있다.The stacked semiconductor package of the present invention configured as described above has the following advantages as the upper and lower surfaces of the first semiconductor chip 2 are used for electrical connection.
먼저, 제1반도체칩(2)과 제2반도체칩(3)간의 전기적 연결을 와이어(5) 본딩에 의해 행하는 대신, 상기 제1반도체칩(2)과 제2반도체칩(3)간의 전기적 연결을 플립칩 본딩에 의해 행함에 따라, 반도체 패키지의 높이를 낮출 수 있게 된다.First, instead of performing electrical connection between the first semiconductor chip 2 and the second semiconductor chip 3 by wire 5 bonding, electrical connection between the first semiconductor chip 2 and the second semiconductor chip 3 is performed. By flip chip bonding, the height of the semiconductor package can be reduced.
또한, 회로기판(1)의 오프닝 영역을 통해 삽입되는 제3반도체칩(4)은 패키지의 전체 높이에 아무런 영향을 미치지 않는 위치에 부착되므로, 반도체 패키지의 높이를 증대시키지 않으면서 메모리 용량을 확장시킬 수 있게 된다.In addition, since the third semiconductor chip 4 inserted through the opening area of the circuit board 1 is attached to a position having no influence on the overall height of the package, the memory capacity can be expanded without increasing the height of the semiconductor package. You can do it.
즉, 상기 회로기판(1)의 오프닝 영역 내측에 위치하는 제3반도체칩(4)은 회로기판(1)의 두께를 벗어나지 않으면서 제1반도체칩(2) 하면에 부착되므로 메모리 용량을 확장시키면서도 패키지의 전체 높이에는 아무런 영향을 미치지 않는다.That is, the third semiconductor chip 4 located inside the opening region of the circuit board 1 is attached to the bottom surface of the first semiconductor chip 2 without deviating from the thickness of the circuit board 1, thereby expanding the memory capacity. It has no effect on the overall height of the package.
이와 더불어, 본 발명에서는 제1반도체칩(2)의 와이어 본딩용 패드(7)와 회로기판(1)의 본딩부를 와이어(5) 본딩시, 와이어(5) 루프의 가장 높은 지점이 제1반도체칩(2)에 부착된 제2반도체칩(3)의 상면을 벗어나지 않으므로 인해, 와이어(5) 루프에도 불구하고 패키지의 높이가 증가되지 않는 장점이 있다.In addition, in the present invention, when the wire bonding pad 7 of the first semiconductor chip 2 and the bonding portion of the circuit board 1 are bonded to the wire 5, the highest point of the loop of the wire 5 is the first semiconductor. Since it does not deviate from the upper surface of the second semiconductor chip 3 attached to the chip 2, there is an advantage that the height of the package does not increase despite the loop of the wire (5).
즉, 본 발명에서는 제2반도체칩(3)과 회로기판(1) 사이를 와이어(5) 본딩에 의해 전기적으로 연결하는 대신, 제2반도체칩(3)을 제1반도체칩(2) 상면에 플립칩 본딩한 상태에서상기 제1반도체칩(2)과 회로기판(1)이 와이어(5) 본딩에 의해 전기적으로 연결되도록 하므로써, 칩 상면으로 돌출되는 와이어 루프로 인해 패키지의 두께가 증가하게 되는 단점을 해소할 수 있게 된다.That is, in the present invention, instead of electrically connecting the second semiconductor chip 3 and the circuit board 1 by wire 5 bonding, the second semiconductor chip 3 is placed on the upper surface of the first semiconductor chip 2. In the flip-chip bonded state, the first semiconductor chip 2 and the circuit board 1 are electrically connected by the wire 5 bonding, so that the thickness of the package increases due to the wire loop protruding to the upper surface of the chip. The disadvantages can be solved.
또한, 제1반도체칩(2)에 대한 제2반도체칩(3) 및 제3반도체칩(4)의 접속이 플립칩 범프(6)에 의해 이루어지므로 다이어태치 어드헤시브가 필요치 않게 되므로 비용을 절감할 수 있게 되며, 다이어태치 어드헤시브의 두께 만큼 패키지 높이를 줄일 수 있게 된다.In addition, since the connection of the second semiconductor chip 3 and the third semiconductor chip 4 to the first semiconductor chip 2 is made by the flip chip bump 6, since the die attach passive is not necessary, Savings can be achieved, and package height can be reduced by the thickness of the die attach aggressive.
한편, 본 발명의 패키지는 회로기판(1)의 면적을 벗어나지 않는 범위에서 반도체칩이 적층되므로 사이즈 면에서도 소형화된 구조이다.On the other hand, the package of the present invention has a structure which is miniaturized in terms of size since the semiconductor chips are stacked within a range not exceeding the area of the circuit board 1.
그리고, 본 발명은 제3반도체칩(4)의 뒷면이 외부로 노출되므로 인해 열방출 능력이 향상되는 장점이 있다.In addition, the present invention has the advantage that the heat dissipation ability is improved because the back surface of the third semiconductor chip 4 is exposed to the outside.
또한, 제1반도체칩(2)과 이에 대해 상하부로 적층되는 제2반도체칩(3) 및 제3반도체칩(4)이 동일 재질이어서, 적층부에 열팽창 계수차에 기인한 응력이 발생하는 현상이 해소된다.In addition, the first semiconductor chip 2 and the second semiconductor chip 3 and the third semiconductor chip 4 stacked up and down are made of the same material so that the stress caused by the thermal expansion coefficient difference occurs in the laminated part. This is solved.
한편, 도 3은 본 발명에 따른 적층형 반도체 패키지의 다른 실시예를 나타낸 종단면도이고, 도 4는 도 3의 회로필름이 하면에 부착된 반도체칩을 나타낸 종단면도로서, 이 경우에는 전술한 실시예의 적층형 패키지와 다른 부분은 구조적으로 동일하며, 다만 제1반도체칩(2)의 하부면에 금속배선이 형성되는 대신, 회로패턴이 형성되며 어드헤시브층(12)이 구비된 회로필름(11)이 부착되는 점이 다르다.3 is a longitudinal sectional view showing another embodiment of the stacked semiconductor package according to the present invention, and FIG. 4 is a longitudinal sectional view showing a semiconductor chip attached to the lower surface of the circuit film of FIG. The other parts of the stacked package are structurally the same, except that a metal wiring is formed on the lower surface of the first semiconductor chip 2, and a circuit pattern is formed and the circuit film 11 is provided with the active layer 12. This is different from the point of attachment.
그리고, 상기 제1반도체칩(2)의 하면에 부착되는 회로필름(11)도 웨이퍼 상태에서 미리 부착됨이 바람직하다.In addition, the circuit film 11 attached to the lower surface of the first semiconductor chip 2 is also preferably attached in advance in the wafer state.
한편, 상기한 실시예들에서 반도체칩의 적층이 끝난 다음에 행해지는 엔캡슐레이션 작업시, 제2반도체칩(3)의 상면이 노출되도록 몰드바디(9)를 형성하면, 제2반도체칩(3) 및 제3반도체칩(4)이 각각 외부로 노출되도록 하므로써 패키지의 열방출 성능을 보다 향상시킬 수 있게 된다.Meanwhile, in the encapsulation operation performed after the stacking of the semiconductor chips in the above embodiments, when the mold body 9 is formed to expose the top surface of the second semiconductor chip 3, the second semiconductor chip ( 3) and the third semiconductor chip 4 are exposed to the outside, respectively, it is possible to further improve the heat dissipation performance of the package.
그리고, 상기한 실시예들에서는 제3반도체칩(4)의 사이즈가 오프닝 영역과 동일한 것으로 되어 있으나, 제3반도체칩(4)의 사이즈가 오프닝 영역 보다 작아도 무방함은 물론이다.In the above-described embodiments, the size of the third semiconductor chip 4 is the same as that of the opening area, but the size of the third semiconductor chip 4 may be smaller than that of the opening area.
이상에서와 같이, 본 발명은 상하방향으로 적층되는 반도체칩중 가운데 위치하는 반도체칩의 상·하면 모두를 전기적 연결에 이용하므로써 패키지의 경박단소화를 도모할 수 있게 된다.As described above, the present invention makes it possible to reduce the thickness of the package by using both the upper and lower surfaces of the semiconductor chips, which are located in the vertical direction of the semiconductor chips, for electrical connection.
즉, 본 발명의 반도체 패키지는 반도체칩이 3층으로 적층되는 구조이면서도 2층 높이로 적층되어 메모리 용량의 증가에 비해 패키지가 경박한 구조를 이루게된다.That is, the semiconductor package of the present invention has a structure in which the semiconductor chips are stacked in three layers but stacked in two layers so that the package is lighter than the increase in memory capacity.
한편, 본 발명은 상부 및 하부에 위치하는 반도체칩이 외부로 노출되어 열방출 성능이 향상되고, 적층부에서의 응력이 해소되므로 인해 패키지의 신뢰성이 향상되는 효과가 있다.On the other hand, the present invention has the effect that the semiconductor chip located in the upper and lower parts is exposed to the outside to improve the heat dissipation performance, the stress in the stack is solved, thereby improving the reliability of the package.
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