JPS5763850A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5763850A
JPS5763850A JP13958880A JP13958880A JPS5763850A JP S5763850 A JPS5763850 A JP S5763850A JP 13958880 A JP13958880 A JP 13958880A JP 13958880 A JP13958880 A JP 13958880A JP S5763850 A JPS5763850 A JP S5763850A
Authority
JP
Japan
Prior art keywords
lead
leads
semiconductor chip
package
enlargement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13958880A
Other languages
Japanese (ja)
Inventor
Eigo Fuse
Fumio Harasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13958880A priority Critical patent/JPS5763850A/en
Publication of JPS5763850A publication Critical patent/JPS5763850A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To dispense with enlargement of the size of a package even when the number of leads is increased, by dividing a plurality of leads into the upper and lower ones and putting an insulating matter between them. CONSTITUTION:A lead frame is divided into two stages of the upper lead 5 and the lower lead 5, and glass 4 is put between them and bonded by heat treatment, while the lower lead 5' is made longer than the upper lead 5. A semiconductor chip 3 is fitted to an island part of the lead frame and a pad on the semiconductor chip 3 is connected selectively to the upper and lower leads 5 and 5' with fine metal wires and sealed with mold resin 1, whereby the package is formed. Bending of the leads is conducted later by a mold. By this method, enlargement of the package can be avoided even when the integration of the semiconductor chip is increased.
JP13958880A 1980-10-06 1980-10-06 Semiconductor device Pending JPS5763850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13958880A JPS5763850A (en) 1980-10-06 1980-10-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13958880A JPS5763850A (en) 1980-10-06 1980-10-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5763850A true JPS5763850A (en) 1982-04-17

Family

ID=15248756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13958880A Pending JPS5763850A (en) 1980-10-06 1980-10-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5763850A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198744A (en) * 1983-04-25 1984-11-10 Fujitsu Ltd Resin sealed type semiconductor device
JPS61121744U (en) * 1984-08-27 1986-07-31
EP0228869A2 (en) * 1986-01-06 1987-07-15 AT&T Corp. Method of manufacturing an electronic component package
JPH01140648A (en) * 1987-11-26 1989-06-01 Nec Corp Resin seal type semiconductor device
US4839716A (en) * 1987-06-01 1989-06-13 Olin Corporation Semiconductor packaging
WO2007053606A2 (en) * 2005-11-01 2007-05-10 Sandisk Corporation Multiple die integrated circuit package
US7352058B2 (en) 2005-11-01 2008-04-01 Sandisk Corporation Methods for a multiple die integrated circuit package
US7511371B2 (en) 2005-11-01 2009-03-31 Sandisk Corporation Multiple die integrated circuit package

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198744A (en) * 1983-04-25 1984-11-10 Fujitsu Ltd Resin sealed type semiconductor device
JPS61121744U (en) * 1984-08-27 1986-07-31
EP0228869A2 (en) * 1986-01-06 1987-07-15 AT&T Corp. Method of manufacturing an electronic component package
US4839716A (en) * 1987-06-01 1989-06-13 Olin Corporation Semiconductor packaging
JPH01140648A (en) * 1987-11-26 1989-06-01 Nec Corp Resin seal type semiconductor device
WO2007053606A2 (en) * 2005-11-01 2007-05-10 Sandisk Corporation Multiple die integrated circuit package
WO2007053606A3 (en) * 2005-11-01 2007-09-07 Sandisk Corp Multiple die integrated circuit package
US7352058B2 (en) 2005-11-01 2008-04-01 Sandisk Corporation Methods for a multiple die integrated circuit package
US7511371B2 (en) 2005-11-01 2009-03-31 Sandisk Corporation Multiple die integrated circuit package
US7514297B2 (en) 2005-11-01 2009-04-07 Sandisk Corporation Methods for a multiple die integrated circuit package
US7939920B2 (en) 2005-11-01 2011-05-10 Sandisk Corporation Multiple die integrated circuit package
US8030135B2 (en) 2005-11-01 2011-10-04 Sandisk Technologies Inc. Methods for a multiple die integrated circuit package

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