JPS5776867A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5776867A
JPS5776867A JP15259380A JP15259380A JPS5776867A JP S5776867 A JPS5776867 A JP S5776867A JP 15259380 A JP15259380 A JP 15259380A JP 15259380 A JP15259380 A JP 15259380A JP S5776867 A JPS5776867 A JP S5776867A
Authority
JP
Japan
Prior art keywords
drawn
chip
outside
semiconductor device
metallic thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15259380A
Other languages
Japanese (ja)
Inventor
Eigo Fuse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15259380A priority Critical patent/JPS5776867A/en
Publication of JPS5776867A publication Critical patent/JPS5776867A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To manufacture the semiconductor device at low cost, and to improve the wetproof property of the device by sealing a semiconductor chip, a metallic thin wire, an island section and one part of a lead drawn to the outside in an airtight manner by an insulator substrate and sealing them with resin. CONSTITUTION:The semiconductor chip 3 is loaded on the island section 2 of the lead frames, and the lead frames 4 drawn to the outside and the chip 3 are connected by the metallic thin wires 5. The chip, the metallic thin wires, the island section and one parts of the lead frames drawn to the outside are sealed in the airtight manner by the insulator substrate 6, and sealed 1 with resin. Accordingly, the semiconductor device, which is cheaper than a ceramic vessel and has excellent wetproof property, is obtained.
JP15259380A 1980-10-30 1980-10-30 Semiconductor device Pending JPS5776867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15259380A JPS5776867A (en) 1980-10-30 1980-10-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15259380A JPS5776867A (en) 1980-10-30 1980-10-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5776867A true JPS5776867A (en) 1982-05-14

Family

ID=15543824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15259380A Pending JPS5776867A (en) 1980-10-30 1980-10-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5776867A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4766095A (en) * 1985-01-04 1988-08-23 Oki Electric Industry Co., Ltd. Method of manufacturing eprom device
EP0348361A2 (en) * 1988-06-22 1989-12-27 STMicroelectronics S.r.l. Hollow plastic package for semiconductor devices
US4971930A (en) * 1985-12-20 1990-11-20 Sgs Microelectronics S.P.A. EPROM semiconductor device erasable with ultraviolet rays and manufacturing process thereof
EP1420458A2 (en) 2002-11-15 2004-05-19 STMicroelectronics Pte Ltd. Semiconductor device package and method of manufacture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4766095A (en) * 1985-01-04 1988-08-23 Oki Electric Industry Co., Ltd. Method of manufacturing eprom device
US4971930A (en) * 1985-12-20 1990-11-20 Sgs Microelectronics S.P.A. EPROM semiconductor device erasable with ultraviolet rays and manufacturing process thereof
EP0348361A2 (en) * 1988-06-22 1989-12-27 STMicroelectronics S.r.l. Hollow plastic package for semiconductor devices
EP1420458A2 (en) 2002-11-15 2004-05-19 STMicroelectronics Pte Ltd. Semiconductor device package and method of manufacture
EP1420458A3 (en) * 2002-11-15 2005-05-04 STMicroelectronics Pte Ltd. Semiconductor device package and method of manufacture

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