JP2002204077A - Wiring substrate, wiring substrate main body, and chip capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide wiring substrate having an electronic component such as an IC chip mounted on a major surface of a main body of the substrate having a core insulating layer, which facilitates connection between terminals such as power and grounding terminals and through-hole conductors formed in the core insulating layer. SOLUTION: A wiring substrate 100 having an electronic component 20 mounted on a major surface 100b has a core insulating layer 110, and the major surface has first and second connection bumps 187 and 188 alternately arranged on the major surface in a lattice form to be formed as power and grounding terminals. Soled first and second conversion conductor layers 161 and 162 are provided between through-hole conductors 114 formed in the core insulating layer 110, and via conductors 182 and 183 on the major surface are extended from first and second bumps 187 and 188 to be connected to the first and second conductor layers. A core-side via conductor 184 is extended to be connected directly from first and second through-hole conductors 117 and 118 thereto.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board having a core insulating layer for mounting electronic components, a wiring board mounting chip capacitors, a wiring board body for mounting chip capacitors, and a chip. Related to capacitors.

[0002]

2. Description of the Related Art With the high integration of IC chips, a power supply potential and a ground potential are supplied to each part of the IC chip with low resistance and low inductance. Some terminals are provided with a ground terminal. On the other hand, in order to prevent noise from being superimposed on power supply wiring and the like and malfunctioning of the IC chip, the main surface 2b or the back surface 2c of the wiring board 2 on which the IC chip 1 is mounted as shown in FIG. Separately, connect chip capacitor 3 to pad 1
9, the capacitor connection wiring 4 connected to the two electrodes of the capacitor 3 via the pad 19 and the connection wiring 7 to the pad 6 are provided inside the wiring board 2. Thus, the chip capacitor 3 is connected to the power supply terminal and the ground terminal of the IC chip 1 via the capacitor connection wiring 4 and the flip chip pad 5, and the signal terminal and the like are connected to the pad 6.

[0003]

By the way, the wiring board 2
In some cases, one obtained by laminating one or more insulating layers 9 to 11 and 12 to 14 on one or both surfaces of the core insulating layer 8 may be used. However, among the capacitor connection wirings 4 and the connection wirings 7, the interval between the through-hole conductors 15 that penetrate the core insulating layer 8 to connect the upper and lower sides of the core insulating layer 8 is different from the flip chip pads 5 due to processing. In some cases, the distance between via conductors 16 for connecting the via conductor 15 to the through hole conductor 15 must be larger than the distance between via conductors 16. Therefore, a design in which the capacitor connection wiring 4 and the connection wiring 7 are appropriately routed using the interlayer wiring 17 and the like including the through-hole conductor 15 and the via conductor 16 so that the distance between the through-hole conductors 15 is appropriate is provided. There is a need to do.

However, as described above, the IC chip 1
When there are a large number of power terminals and ground terminals on the rear surface, a capacitor connection wiring 4 for connecting these to the capacitor 3 mounted on the back surface 2c side and a connection wiring 7 for connecting to the pads 6 on the back surface side are provided. And the wiring tends to be complicated, and the resistance and inductance of the capacitor connection wiring 4 and the connection wiring 7 tend to increase.
Further, when a large number of chip capacitors are to be mounted on the back surface 2c or the like, or when it is desired to connect to a chip capacitor having a large number of terminals, wiring routing is likely to be complicated.

On the other hand, when mounting the chip capacitor 3 on the back surface side, there is a chip capacitor in which a large number of bump-shaped terminals are formed in a vertical and horizontal lattice on the connection surface, and the bump-shaped terminals are connected to the wiring board. . Even in a wiring board on which such a chip capacitor is mounted, in order to facilitate the connection between the wiring board body and the chip capacitor,
Via conductors 18 and pads 19 formed in insulating layers 12 to 14
Needs to be considered.

A first object of the present invention is to provide a wiring board for mounting an electronic component such as an IC chip on a main surface side of a wiring board body having a core insulating layer. In the above, it is an object of the present invention to provide a wiring board that facilitates connection between terminals such as a power supply terminal and a ground terminal among connection terminals connected to terminals of an electronic component and through-hole conductors formed in a core insulating layer. Another object of the present invention is to provide a wiring board having a chip capacitor mounted on a mounting surface of the wiring board body, the wiring board and the wiring board body taking into consideration the arrangement of the terminals of the chip capacitor and via conductors and pads formed in the wiring board body. , And a chip capacitor.

[0007]

A means for solving the problem is a wiring board having a main surface and a back surface, which is formed on the main surface side and has terminals for electronic components mounted on the main surface. A plurality of connection terminals that can be connected to the first connection terminal and a plurality of second connection terminals that are set to a common first potential and a plurality of second connection terminals that are set to a common second potential. At least one of the two connection terminals is formed of a first grid connection terminal and a second grid connection terminal, which are alternately arranged in a grid pattern at a first predetermined interval to form a grid region, and one or more insulating layers. A core insulating layer having a core main surface and a core back surface, and a plurality of through-hole conductors penetrating between the core main surface and the core back surface of the core insulating layer. Of the first through-hole conductor and a common second potential It includes a second through-hole conductors having,
At least one of the first through-hole conductor and the second through-hole conductor located at least in the projection lattice area where the lattice area is projected toward the back side in the thickness direction is alternately arranged in a lattice pattern at a second predetermined interval. And a plurality of first through-holes interposed between the first lattice through-hole conductor and the second lattice through-hole conductor, which are disposed in the core insulating layer, and the core main surface of the core insulating layer and the connection terminal. First
A conversion conductor layer, a second conversion conductor layer located between the first conversion conductor layer and the core main surface of the core insulating layer, the second conversion conductor layer having a plurality of second through holes, and a first lattice in the lattice region. A first main surface side via conductor extending from the connection terminal toward the back side in the thickness direction of the wiring substrate and electrically connecting to the first conversion conductor layer, and a second lattice connection terminal in the lattice region Respectively, extending toward the back side in the thickness direction of the wiring board, and electrically connected to the second conversion conductor layer through the first through hole while being insulated from the first conversion conductor layer. A second main surface side via conductor extending from the first lattice through hole conductor in the projection lattice region toward the main surface side in the thickness direction of the wiring board, and being insulated from the second conversion conductor layer, respectively. While passing through the second through hole, A first core-side via conductor connected to the conversion conductor layer; and a second conversion conductor layer extending from the second grid through-hole conductor in the projection grid area toward the main surface in the thickness direction of the wiring board. A second core-side via conductor connected to the first grid-side via conductor, wherein the second grid spacing is larger than the first grid spacing, and the number of the first core-side via conductors in the projection grid area is within the grid area. A wiring board having a number smaller than the number of the first main surface side via conductors and a smaller number of the second core side via conductors in the projection grid region than the number of the second main surface side via conductors in the grid region; It is.

As described above, when the through-hole conductors are formed in the core insulating layer, the distance between the through-hole conductors formed in the core insulating layer is generally different from that of electronic parts such as IC chips due to differences in processing techniques. Connection terminals such as flip-chip bumps for connection, and the main surface side via conductors connected thereto may be inevitably larger. For this reason, in a wiring board in which a plurality of connection terminals connectable to terminals of an electronic component are formed on a main surface side, a connection wiring extending from this connection terminal to a back surface side beyond a core insulating layer is designed to have a core. Since the distance between through-hole conductors that can be formed in the insulating layer is limited, the design of the connection wiring is troublesome.

On the other hand, since the wiring board of the present invention has the first and second conversion conductor layers, the first grid connection terminals and the second grid connection are alternately arranged in a grid in the grid area. The terminal and the connection position and the number of connections are converted by the first and second conversion conductor layers and connected to the first and second lattice through-hole conductors formed in the projection lattice region of the core insulating layer. Moreover, the second lattice spacing is larger than the first lattice spacing, and the number of the first and second core-side via conductors in the projection lattice area is greater than the number of the first and second principal-surface side via conductors in the lattice area. Are also small. Therefore, the first and second in this lattice area
The connection position and the number of connections of the lattice connection terminals are changed by the first and second conversion conductor layers, and the lattice connection terminals can be easily connected to the first and second lattice through-hole conductors. Therefore, the design of the connection wiring on the wiring board becomes easy.

Here, one of the common first potential and the second common potential is a power supply potential (for example, a + potential: for example, +1.
8V, + 5V, etc.) and the other is ground potential (0V) or-
A potential is given. The core insulating layer may be made of a known material. For example, epoxy resin, polyimide resin, BT resin, PP
A resin-resin composite material containing a resin such as an E resin as a main component, a three-dimensional network structure fluorine resin such as PTFE having continuous pores impregnated with an epoxy resin, or the like can be used. Furthermore, composite materials such as glass-epoxy resin composite materials, which are composited with epoxy resin using glass fiber such as glass woven fabric or glass nonwoven fabric or organic fiber such as polyamide fiber, alumina, aluminum nitride, mullite, glass ceramic And a composite of a resin such as ceramic, epoxy resin and ceramic powder. Furthermore, as the core insulating layer,
Not limited to a single insulating layer, for example, glass-
Also included are those composed of a plurality of insulating layers, such as a core substrate made of an epoxy resin composite material and resin insulating layers formed on both surfaces.

The grid region formed by the first grid connection terminal and the second grid connection terminal is a part of the portion where the first connection terminal and the second connection terminal are arranged, and the shape of the grid region is not limited. . Therefore, the shape becomes a shape corresponding to the arrangement of the terminals of the mounted electronic component, such as a substantially rectangular shape or a ring shape. In addition, a solder resist layer may be formed around the first and second connection terminals to ensure insulation between the first and second connection terminals and to prevent the spread of solder or the like.

Furthermore, in the above wiring board, the second
The lattice spacing is an odd multiple of the first lattice spacing, and the first
Each of the core-side via conductors is substantially coaxial with the first principal-surface-side via conductor, and the second core-side via conductor is substantially a coaxial with the second main-surface-side via conductor. good.

If the first and second core-side via conductors converted by the first and second conversion conductor layers are not substantially coaxial with the first and second main-surface via conductors before conversion, the connection terminal And the path connecting the through-hole conductor to the first and second main surface side via conductors, the first and second conversion conductor layers in a plane direction,
After that, they are connected to the first and second lattice through-hole conductors through the first and second core-side via conductors, respectively. Therefore, since each path once passes through the conversion conductor layer in the plane direction, the combined resistance and the inductance of each path increase by the amount that passes through the conversion conductor layer in the plane direction.

On the other hand, in the wiring board of the present invention, the second grid interval is an odd multiple of the first grid interval, specifically, 3, 5,.
It is twice. When the odd multiples are used in this manner, a relationship is obtained in which the grids at the first grid interval and the grids at the second predetermined interval can be exactly overlapped. In addition, the first core-side via conductor is substantially coaxial with the first main surface-side via conductor, and
Each of the core side via conductors is substantially coaxial with the second main surface side via conductor. As described above, the number of the first core-side via conductors in the projection lattice region is smaller than the number of the first main surface-side via conductors in the lattice region. Therefore, when viewed from the first main surface side via conductor, there is a first main surface side via conductor that is not coaxial with the first core side via conductor. Since the main surface side via conductor is connected to the first core side via conductor through the first conversion conductor layer in the plane direction, the path connecting the first lattice connection terminal and the first lattice through hole conductor is The combined resistance and combined inductance of each path increase by the amount of the conversion conductor layer. However, between the coaxial main-surface via conductor and the core-side via conductor, the conductor only passes through the conversion conductor layer in the thickness direction, and the resistance and inductance are smaller than those of other conductor conductors. Therefore, since the other main surface side via conductors located in the periphery are not coaxial with the core side via conductors, they pass through the conversion conductor layer in the plane direction, and even if resistance or inductance is generated in this portion, they are connected in parallel with these. Of the first main surface side via conductor and the first
Since the resistance and inductance between the core-side via conductor can be reduced, the combined resistance and combined inductance of the entire path connecting the first lattice connection terminal and the first lattice through-hole conductor can be reduced.

The relationship between the second core-side via conductor and the second main-surface via conductor is the same, and the path between the second main-surface via conductor and the second core-side via conductor is partially changed. Since the resistance and the inductance can be reduced, the combined resistance and combined inductance of the entire path connecting the second lattice connection terminal and the second lattice through-hole conductor can be reduced. Therefore, the combined resistance and the combined inductance of the entire path connecting the first and second lattice connection terminals and the first and second lattice through-hole conductors can be reduced for the entire wiring board.

Still another solution is a wiring board having a main surface and a back surface, wherein a plurality of connection terminals formed on the main surface and connectable to terminals of electronic components mounted on the main surface. And includes a number of first connection terminals having a common first potential and a number of second connection terminals having a common second potential, wherein at least one of the first connection terminal and the second connection terminal is A first lattice connection terminal and a second lattice connection terminal, which are alternately arranged in a lattice pattern at a first predetermined interval to form a lattice region, and a connection terminal serving as a second lattice connection terminal, and one or a plurality of insulating layers; And a through-hole conductor penetrating between the core main surface and the core back surface of the core insulating layer, the plurality of first insulating layers having a common first potential.
A first through-hole conductor including a through-hole conductor and a plurality of second through-hole conductors having a common second potential, wherein the first through-hole conductor is located at least in a projection grid area where the grid area is projected toward the back side in the thickness direction; And at least one of the second through-hole conductor is a first lattice through-hole conductor and a second lattice through-hole conductor, which are alternately arranged in a lattice pattern at a second predetermined interval, and the core insulating layer A first conversion conductor layer having a plurality of first through-holes interposed between the core main surface and the connection terminal, and a plurality of second through-holes located on the core main surface of the core insulating layer. A first conversion conductor layer extending from the first grid connection terminal in the grid region toward the back side in the thickness direction of the wiring board, and a first main conductor electrically connected to the first conversion conductor layer. Surface side via And extending from the second grid connection terminals in the grid area toward the back side in the thickness direction of the wiring board, and pass through the first through hole while being insulated from the first conversion conductor layer, respectively. A second main surface side via conductor electrically connected to the second conversion conductor layer, and a first main surface through hole conductor in the projection lattice region, respectively, toward a main surface side in the thickness direction of the wiring substrate. And a first core-side via conductor connected to the first conversion conductor layer. The first lattice through-hole conductor is located in the second through hole and is separated from the second conversion conductor layer. Insulate,
The second grid through-hole conductor in the projection grid area is directly connected to the second conversion conductor layer, the second grid pitch is larger than the first grid pitch, and the first core in the projection grid area is The number of the side via conductors is smaller than the number of the first main surface side via conductors in the lattice area, and the number of the second lattice through-hole conductors in the projection lattice area is the number of the second main conductors in the lattice area. The wiring board is smaller in number than the surface side via conductors.

Since the wiring board of the present invention has the first and second conversion conductor layers, the first grid connection terminals and the second grid connection terminals alternately arranged in a grid pattern in the grid area are: The connection position and the number of connections are converted by the first and second conversion conductor layers and connected to the first and second lattice through-hole conductors formed in the projection lattice region of the core insulating layer. Moreover, the second lattice spacing is larger than the first lattice spacing, and the number of the first core-side via conductors in the projection lattice area is smaller than the number of the first main surface-side via conductors in the lattice area. The number of through-hole conductors is smaller than the number of second main surface side via conductors in the lattice area. Therefore, the connection positions and the number of connections of the first and second lattice connection terminals in this lattice region are converted by the first and second conversion conductor layers, and the first and second lattice connection terminals can be easily connected to the first and second lattice through-hole conductors. . Therefore, the design of the connection wiring on the wiring board becomes easy.

In general, as for the resistance and the inductance, as the number of parallel paths increases, the combined resistance and the combined inductance can be reduced. In the wiring board of the present invention, the second conversion conductor layer is formed on the core main surface of the core insulating layer, and the second conversion conductor layer is directly connected to the second lattice through-hole conductor. That is, in the wiring board of the present invention, since the second conversion conductor layer is located closest to the core insulating layer, the path from each second lattice connection terminal to the second conversion conductor layer is long, and The path to the second grid through-hole conductor is the shortest (direct connection). Here, the number of paths from each second lattice connection terminal including the second principal surface side via conductor to the second conversion conductor layer is larger than that of the second lattice through-hole conductor. The combined resistance and combined inductance generated in the path from each second lattice connection terminal to the second conversion conductor layer can be minimized.

Further, in the above-mentioned wiring board, further comprising a plurality of main surface side insulating layers between the core main surface of the core insulating layer and the connection terminals, wherein the first conversion conductor layer is provided on the main surface. It is preferable that the wiring board is arranged on the main surface side of the main surface side insulating layer located closest to the core insulating layer among the side insulating layers.

In the wiring board of the present invention, the first conversion conductor layer is disposed on the main surface side of the main surface side insulating layer closest to the core insulating layer among the main surface side insulating layers. That is,
Of the main surface side insulating layers, the main surface side insulating layer is disposed between the main surface side insulating layer closest to the core insulating layer and the main surface side insulating layer adjacent thereto. Therefore, not only is the second conversion conductor layer located closest to the second lattice through-hole conductor,
The first conversion conductor layer is also positioned closest to the first lattice through-hole conductor, and the first conversion conductor layer is connected to the first lattice connection terminal by the first lattice connection terminal.
The path from the first conversion conductor layer to the first
The path to the grid through-hole conductor is the shortest. Therefore, the combined resistance and combined inductance generated in the path from each first lattice connection terminal to the first conversion conductor layer can be minimized. Therefore, combined with the fact that the combined resistance and the combined inductance generated in the path from each second lattice connection terminal to the second conversion conductor layer can be minimized, the first and second lattice connection terminals are connected to the first and second lattice connection terminals. The combined resistance and combined inductance generated in the path to the conversion conductor layer can be minimized.

Further, in the wiring board according to any one of the above, the second grid interval is an odd multiple of the first grid interval, and the first core-side via conductors are all of the first grid via conductor.
The second lattice through-hole conductor is preferably substantially coaxial with the main surface side via conductor, and the second lattice through-hole conductor is preferably a wiring substrate substantially coaxial with the second main surface side via conductor.

When the first core-side via conductor converted by the first conversion conductor layer is not substantially coaxial with the first main-surface-side via conductor before conversion, the first grid connection terminal and the first grid through hole are provided. All the paths connecting the conductors pass through the first main surface side via conductor, first pass through the first conversion conductor layer in the plane direction, and then pass through the first core side via conductor to be connected to the first lattice through-hole conductor. Will do. When the second lattice through-hole converted by the second conversion conductor layer is not substantially coaxial with the second main surface side via conductor before conversion, the second lattice connection terminal and the second lattice through-hole conductor Is the second route
After passing through the main surface side via conductor, the second conversion conductor layer is once passed in the plane direction, and then connected to the second lattice through-hole conductor. Therefore, since all the paths pass through the conversion conductor layer in the plane direction, the combined resistance and the inductance of each path are increased by the amount that passes through the conversion conductor layer in the plane direction.

On the other hand, in the wiring board of the present invention, the second grid interval is an odd multiple of the first grid interval, specifically, 3, 5,.
It is twice. When the odd multiples are used in this manner, a relationship is obtained in which the grids at the first grid interval and the grids at the second predetermined interval can be exactly overlapped. In addition, the first core-side via conductor is substantially coaxial with the first main surface-side via conductor. Each of the second lattice through-hole conductors is substantially coaxial with the second main surface side via conductor. As described above, the number of the first core-side via conductors in the projection lattice region is smaller than the number of the first main surface-side via conductors in the lattice region. Therefore, when viewed from the first main surface side via conductor, the first core side via conductor which is not coaxial with the first core side via conductor.
There is a main surface side via conductor. Since the main surface side via conductor is connected to the first core side via conductor through the first conversion conductor layer in the plane direction, a path connecting the grid connection terminal and the first grid through-hole conductor is formed by the conversion conductor. The combined resistance and the combined inductance of each path are increased by the number of layers. However, between the coaxial main-surface via conductor and the core-side via conductor, the conductor only passes through the conversion conductor layer in the thickness direction, and the resistance and inductance are smaller than those of other conductor conductors. Therefore, since other main surface side via conductors located around are not coaxial with the core side via conductor, they pass through the conversion conductor layer in the plane direction,
Even if resistance and inductance are generated in this portion, the resistance and inductance between the first main surface side via conductor and the first core side via conductor can be reduced in some paths connected in parallel with these portions. In addition, the combined resistance and combined inductance of the entire path connecting the first lattice connection terminal and the first lattice through-hole conductor can be reduced.

The relationship between the second lattice through-hole conductor and the second main surface side via conductor is the same, and the second lattice through-hole conductor and the second main surface side via conductor have the same structure.
The resistance and inductance between the main-surface-side via conductor and the second lattice through-hole conductor can be reduced, so that the combined resistance and the combined inductance of the entire path connecting the second lattice connection terminal and the second lattice through-hole conductor are reduced. can do. Therefore, the combined resistance and the combined inductance of the entire path connecting the first and second lattice connection terminals and the first and second lattice through-hole conductors can be reduced in the entire wiring board.

Further, a solution according to the other object is as follows.
A wiring board comprising one or a plurality of chip capacitor capacitors mounted on a wiring board body, wherein the chip capacitor is formed on one electrode and the other electrode constituting a capacitor, a connection surface, and the connection surface. A plurality of first terminals connected to the first electrode and a plurality of second terminals formed on the connection surface and connected to the other electrode, wherein the first terminal and the second terminal are arranged in a lattice pattern at a predetermined interval. The wiring board body is a capacitor mounting surface on which the chip capacitor is mounted, one or more insulating layers, and a via conductor penetrating the insulating layer. A first via conductor having one potential,
And at least one of the first via conductor and the second via conductor, the first via conductor and the second via conductor being alternately arranged in a grid pattern at substantially the same interval as the predetermined interval. A via conductor that is a lattice via conductor and a second lattice via conductor, and the chip capacitor having the connection surface facing the capacitor mounting surface on the terminal forming surface closest to the capacitor mounting surface among the surfaces formed by the insulating layers. A first capacitor connection terminal formed at a position facing the first terminal and connected to the first lattice via conductor; and a first capacitor connection terminal formed at the terminal formation surface and facing the second terminal of the chip capacitor. And a second capacitor connection terminal formed and connected to the second lattice via conductor.

In the wiring board of the present invention, the chip capacitor has first and second terminals alternately arranged in a grid on the connection surface. On the other hand, the wiring board body has first and second lattice via conductors alternately arranged in a lattice pattern, and the distance between the lattices is substantially the same as the distance between the lattices of the first and second terminals. In addition, the first and second lattice via conductors are respectively connected to the first and second lattice via conductors.
It has first and second capacitor connection terminals facing the second terminal, respectively. For this reason, each of the first and
The connection between the second terminal and each of the first and second lattice via conductors does not require the use of a wiring layer extending in the planar direction in the insulating layer, and the connection can be made only through the first and second capacitor connection terminals. In addition, both the chip capacitor and the first and second lattice via conductors can be easily connected. Moreover, they can be connected with low resistance and low inductance.

The chip capacitor may be any one as long as it can be mounted on a wiring board.
For example, a multilayer ceramic type, an electrolytic capacitor type, a film capacitor type and the like can be mentioned. In particular, a multilayer ceramic type chip capacitor is preferable because it has good frequency characteristics and its characteristics are relatively stable even when heat is applied. Further, a solder resist layer may be formed around the first and second capacitor connection terminals to ensure insulation between the first and second capacitor connection terminals and to prevent wet spread of solder or the like.

Further, in the above wiring board, the chip capacitor is plural, and the first terminal or the second terminal of one chip capacitor and the second terminal or the first terminal of another chip capacitor adjacent thereto are provided. Is an integer multiple of 2 or more of the predetermined interval, and among the first lattice via conductors, the first lattice via conductor not connected to the first capacitor connection terminal is formed on the terminal formation surface; The first capacitor connecting terminal is connected to a first extending portion extending from any one of the first capacitor connecting terminals, and the second grid via conductor is connected to the second extending portion.
The second grid via conductor not connected to the capacitor connection terminal is
The wiring board may be formed on the terminal formation surface and connected to a second extending portion extending from any of the second capacitor connection terminals.

When a plurality of chip capacitors are mounted on the wiring board body, a gap is formed between the chip capacitors, so that connection between each chip capacitor and the via conductor tends to be troublesome. In contrast, in the wiring board of the present invention,
Focusing on the relationship between the terminals of the chip capacitors, the interval between the terminals belonging to two adjacent chip capacitors was set to an integer multiple of 2 or more of the lattice interval. As a result, regarding the connection between the first and second lattice via conductors having substantially the same lattice spacing and the first and second terminals of each chip capacitor,
Each of the first and second terminals of each of the chip capacitors and each of the first and second lattice via conductors are connected to the first and second lattice via conductors without the interposition of a wiring layer extending in the planar direction in the insulating layer. There is no difference in that the connection can be made only through the capacitor connection terminal. Therefore, the first and second terminals and the first and second lattice via conductors can be easily connected with low resistance and low inductance.

Moreover, the first and second lattice via conductors located at positions corresponding to the gaps and surroundings between the chip capacitors are connected to the first and second extension portions, respectively, and the first and second lattice via conductors are connected via the first and second extension portions. Since the first and second capacitor connection terminals are connected, they can be connected to the first and second capacitor connection terminals respectively. Therefore, in the first and second capacitor connection terminals having the first and second extension portions, the number of the connected first and second lattice via conductors increases, and the first and second grid via conductors when charging and discharging the chip capacitor are connected. Resistance and inductance due to the second lattice via conductor can be reduced. In addition, the first and second lattice via conductors located at these portions also maintain a state of being alternately arranged in a lattice pattern at a predetermined interval. Even if there is a change, by changing the pattern of the first and second capacitor connection terminals including the first and second extending portions without changing the position and the like of the first and second lattice via conductors, It can be easily handled.

Further, in the above wiring board, the distance between the first terminal or the second terminal of the one chip capacitor and the second terminal or the first terminal of another chip capacitor adjacent to the first terminal may be the same as that of the first chip capacitor. It is preferable that the wiring board be twice as long as the predetermined interval.

When mounting a plurality of chip capacitors, as many chip capacitors as possible are mounted on a limited area of the mounting surface to increase the capacitance of the entire chip capacitor. It may be desirable to reduce the gap between them. In such a case, the wiring board is provided with a plurality of the chip capacitors, and the first terminal or the second terminal of one chip capacitor and the first terminal or the other terminal of another chip capacitor adjacent thereto. It is preferable that the wiring board has a distance from the second terminal that is substantially equal to the predetermined distance. However, in this case, the first and second terminals provided on the chip capacitor are located very close to the peripheral edge of the connection surface, which makes it difficult to form the chip capacitor itself, and insulates the adjacent chip capacitors. It tends to be difficult to maintain.

In the wiring board of the present invention, the interval between the terminals of adjacent chip capacitors is twice the predetermined interval, that is, twice the lattice interval between the first and second lattice via conductors.
For this reason, regarding the connection between the first and second lattice via conductors having substantially the same lattice spacing and the first and second terminals of each chip capacitor, each of the first and second terminals of each chip capacitor includes: Each of the first and second lattice via conductors can be connected only through the first and second capacitor connection terminals. Therefore, the first and second terminals and the first and second lattice via conductors can be easily connected with low resistance and low inductance. In addition, since the interval between the terminals of adjacent chip capacitors is set to a small interval twice as large as the predetermined interval, the chip capacitors can be densely mounted.

Still another solution is a wiring board body for mounting one or a plurality of chip capacitor capacitors to form a wiring board, wherein the chip capacitor has one electrode and another electrode constituting the capacitor. electrode,
A first terminal formed on the connection surface and connected to the one electrode, and a plurality of second terminals formed on the connection surface and connected to the other electrode;
A terminal and a second terminal are chip capacitors alternately arranged in a grid pattern at a first predetermined interval, and the wiring board body includes:
A capacitor mounting surface for mounting the above chip capacitor,
The first via conductor including one or more insulating layers and a via conductor penetrating the insulating layer, the first via conductor having a common first potential, and the second via conductor having a common second potential; At least one of the via conductors and the second via conductors is a first conductor that is alternately arranged in a grid pattern at substantially the same interval as the predetermined interval.
Via conductors that are lattice via conductors and second lattice via conductors;
Of the surfaces formed by the insulating layers, the surface closest to the capacitor mounting surface is formed at a position facing the first terminal when mounting the chip capacitor with the connection surface facing the capacitor mounting surface side, A first capacitor connection terminal connected to the first lattice via conductor, and a first capacitor connection terminal formed on the same surface as the first capacitor connection terminal and formed at a position facing the second terminal when the chip capacitor is mounted; And a second capacitor connection terminal connected to the second lattice via conductor.

In the wiring board body of the present invention, the chip capacitor mounted on the wiring board body has first and second terminals alternately arranged in a grid on the connection surface. On the other hand, the wiring board body
It has first and second lattice via conductors alternately arranged in a lattice, and the lattice spacing is substantially the same as the lattice spacing of the first and second terminals. In addition, the semiconductor device has first and second capacitor connection terminals connected to the first and second lattice via conductors and facing the first and second terminals, respectively. Therefore, it is not necessary to form a wiring layer extending in the planar direction in the insulating layer for connecting the first and second terminals of the chip capacitor to the first and second lattice via conductors. Since the connection can be made only through the first and second capacitor connection terminals, both the chip capacitor and the first and second lattice via conductors can be easily connected. Moreover, they can be connected with low resistance and low inductance.

Further, in the wiring board main body, the chip capacitor is plural, and the first terminal or the second terminal of one chip capacitor is connected to the second terminal or the second terminal of another chip capacitor adjacent thereto. An interval between the first lattice via conductor and the first lattice via conductor that is not integral with the first capacitor connection terminal is formed on the terminal formation surface. A second lattice via conductor connected to a first extension extending from any one of the first capacitor connection terminals and not connected to the second capacitor connection terminal among the second lattice via conductors, A wiring board main body formed on a formation surface and connected to a second extending portion extending from any one of the second capacitor connection terminals.

When a plurality of chip capacitors are mounted on the wiring board body, a gap is formed between the chip capacitors, so that connection between each chip capacitor and the via conductor tends to be troublesome. On the other hand, in the wiring board body of the present invention, the interval between terminals belonging to two adjacent chip capacitors is set to an integral multiple of 2 or more of the lattice interval. For this reason,
Regarding the connection between the first and second lattice via conductors having substantially the same lattice spacing and the first and second terminals of each chip capacitor, the first and second terminals of each chip capacitor and the first and second terminals , The second lattice via conductor means that the wiring layer formed in the insulating layer and extending in the planar direction does not intervene.
There is no change in that the connection can be made only through the first and second capacitor connection terminals. Therefore, the first and second terminals and the first and second lattice via conductors can be easily connected with low resistance and low inductance.

Moreover, when the chip capacitors are mounted, the first and second lattice via conductors located at positions corresponding to the gaps and surroundings between the chip capacitors are the first and second grid via conductors, respectively.
Since it is connected to the second extending portion and connected to the first and second capacitor connection terminals via this, it is connected to the first and second capacitor connection terminals respectively through this. For this reason,
In the first and second capacitor connection terminals having the first and second extending portions, the number of first and second grid via conductors connected increases, and the first and second grids for charging and discharging the chip capacitor are increased. Resistance and inductance due to via conductors can be reduced. In addition, the first and second lattice via conductors located at these portions also maintain a state of being alternately arranged in a lattice at a predetermined interval, so that the chip capacitor mounted on the wiring board body of the present invention can be used. Even when the shape of the chip capacitor such as the number of terminals is changed, the first and second capacitor connections including the first and second extending portions are not changed without changing the positions and the like of the first and second grid via conductors. By changing the pattern of the terminals, it is possible to easily cope with the problem.

Still another solution is a chip capacitor having one electrode and the other electrode constituting a capacitor. The chip capacitor has a substantially rectangular parallelepiped shape, a substantially rectangular connection surface, and four side surfaces orthogonal to the connection surface. And a plurality of first terminals formed on the connection surface and connected to the one electrode; and a plurality of second terminals formed on the connection surface and connected to the other electrode. The terminals and the second terminals are alternately arranged at a predetermined interval in a lattice shape parallel and orthogonal to any one of the peripheral edges of the connection surface, and the terminal and the second terminal of the connection surface of the first terminal and the second terminal are arranged at the end of the connection surface. The distance between the outermost first terminal and the outermost second terminal located on the outer circumference and the four side surfaces is a chip capacitor smaller than the predetermined distance.

In the chip capacitor of the present invention, the first terminals and the second terminals are alternately arranged at a predetermined interval and in a lattice shape parallel and orthogonal to any one of the peripheral edges of the connection surface. In addition, the distance between the outermost first terminal and the outermost second terminal located at the outermost periphery of the connection surface of the first terminal and the second terminal and the four side surfaces is smaller than the above-described predetermined distance. Therefore, when this chip capacitor is used, a plurality of chip capacitors can be arranged with the interval between terminals between adjacent chip capacitors being twice the predetermined interval. Furthermore, the interval between terminals between adjacent chip capacitors can be reduced to within twice.
That is, a plurality of chip capacitors can be arranged at narrow intervals. Therefore, for example, a large number of chip capacitors can be mounted on the wiring board body.

[0041]

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS. The wiring board 100 shown in FIG. 1 includes a core insulating layer 110 serving as a center,
The main surface side insulating layers 122 to 125 and the back side insulating layers 132 to 13 made of epoxy resin are respectively stacked on the upper and lower sides.
And 5. In the center of the main surface 100b of the wiring substrate 100, a large number of connection pads 185 and a large number of connection bumps 189 formed thereon are arranged.
And a plurality of terminals 22 formed on the lower surface 21 of each of them can be flip-chip connected. Also, the back surface 100 in FIG.
c, the first and second capacitor connection pads 19
5, 196 are alternately arranged in a grid pattern and connected to the first and second capacitor terminals 212 of the chip capacitor 210 via solder 199.
Is mounted on the back surface 100c. Also, the back 100c
A large number of connection pads 194 are formed on the periphery of, and can be connected to another substrate (not shown) such as a motherboard.

The core insulating layer 110 is made of a glass
It is composed of three insulating layers formed of insulating layers 112 and 113 made of epoxy resin on and under an insulating layer 111 made of an epoxy resin composite material, and penetrates between the core main surface 110b and the core back surface 110c in the thickness direction. Core through hole 1
Many through-hole conductors 114 are formed in 10h. The through-hole conductor 114 includes a through-hole conductor 115 serving as a part of a signal wiring and a first through-hole conductor 11 having a positive power supply potential (common first potential).
7. There is a second through-hole conductor 118 which is set to the ground potential (common second potential). In particular, as described later, the first and second through-hole conductor layers 117 and 118 located in the projection grating area PLA (the central portion in FIG. 1) have a predetermined grating interval TP (TP = 450 μm in the present embodiment). ) Are the first lattice through-hole conductor layers 117 and the second lattice through-hole conductor layers 118 alternately arranged.

Next, the structure on the main surface side (upper side in the figure) of the core insulating layer 110 will be described. Core insulating layer 11
0 on the core main surface 110b.
25 and a solder resist layer 126 are laminated.
Of these layers 141 to 145, the substantially solid second conversion conductor layer 16 is provided between layers 141 (on the core main surface 110 b).
1 are formed (see FIG. 5). Also, the core main surface 11
A substantially solid first conversion conductor layer 162 is formed on the main surface side of the main surface side insulating layer 122 in contact with Ob (ie, between the main surface side insulating layers 122 and 123) (see FIG. 4). . Further, wiring layers 163 and 164 are formed between the layers 143 and 144, respectively. The connection bumps 189 formed on the main surface 100b side are connected to the connection pads 18 respectively.
5, through the main surface side insulating layer 125, etc.
It extends to the c side.

Here, the arrangement of the connection bumps 189 of the wiring board 100 is as shown in FIG. That is, a large number of connection bumps 18 are provided at the central portion of main surface 100b.
9 is a predetermined interval BP (BP = 150 μm in this embodiment)
Are arranged in a vertical and horizontal lattice. Of these, connection bumps 189 mainly for inputting / outputting signals and the like are arranged outside the lattice area LA surrounded by a dashed line. on the other hand,
As shown in FIG. 3, the first grid connection bumps 187L which are set to the + power supply potential (common first potential) in the grid area LA.
And the second grid connection bumps 188L which are set to the ground potential (common second potential) are alternately arranged in a grid pattern at a predetermined interval BP. In addition, the first connection bump 187 which is a power supply potential of + and the second connection bump 188 which is a ground potential are:
It may be formed outside the lattice area LA.

Of the connection bumps 189 thus arranged, the connection bumps 186 formed outside the lattice area LA and used for signal wiring and the like are, as shown in FIG. The layers 125 and 124 penetrate and are connected to the wiring layers 163 and 164, and are once further fanned out (in the left-right direction in the drawing), and
Via conductor 1 penetrating through 4-122 or 123, 122
72 connects to the through-hole conductor 115 formed in the core insulating layer 110. Then, the back side insulating layer 132
135 are connected to connection pads 194 formed on the back surface side of the back surface side insulating layer 135 by via conductors 191. This enables connection to another substrate as described above.

On the other hand, the first region located in the lattice area LA
The grid connection bumps 187L are formed on the main surface side insulating layers 125 and 12.
First main surface side via conductor 182 extending through 4,123
By this, the connection is made to the first conversion conductor layer 162. FIG. 4 shows the lattice region L in the MM ′ section in FIG.
3A shows a portion in the projection grid area PLA where A is projected on the back surface 100c side, and corresponds to the arrangement of the first and second grid connection bumps 187L and 188L shown in FIG. FIG.
In the figure, the connection position of the first main surface side via conductor 182 connected to the first conversion conductor layer 162 from the main surface side is indicated by a mark x. Further, a first core-side via conductor 184 indicated by a dashed circle is connected to the back surface side (core insulating layer 110 side) of the first conversion conductor layer 162. That is, the first core-side via conductor 184 extends from the first conversion conductor layer 162 toward the rear surface. Here, the number and positions of the first core-side via conductors 184 are as shown in FIG. That is, when the number of the first main surface side via conductors 182 and the number of the first core side via conductors 184 are compared, the number of the first core side via conductors 184 is reduced so as to be easily understood. The first core-side via conductor 184 is the first main-surface-side via conductor 1.
4 is formed at a position overlapping with FIG. That is, the first core side via conductor 184 is the first main surface side via conductor 1
82 is formed coaxially. Accordingly, the coaxial first core side via conductor 184 is separated from the first main surface side via conductor 182 only by the thickness of the first conversion conductor layer 162, and thus occurs at this portion. Since the resistance and inductance are extremely small, the combined resistance and combined inductance can be reduced as a whole.

Further, the positions of the first core-side via conductors 184 are regular, and the positions of the first main-side via conductors 182 are different from the lattices (lattices which appear obliquely in FIG. 4) formed by the first main surface side via conductors 182.
The spacing has been chosen to form a triple grid. In this manner, the connection position and the number of connections of the first main surface side via conductor 182 can be changed by the first conversion conductor layer, and the first main surface side via conductor 182 can be easily connected to the first core side via conductor 184.

Similarly, the second grid connection bump 188L located in the grid area LA is connected to the main surface side insulating layer 12
5, 124, 123, and 122 are connected to the second conversion conductor layer 161 by the second main surface side via conductor 183 extending through the conductor (see FIG. 5). However, in relation to the first conversion conductor layer 162, as shown in FIG. 4, the second main surface side via conductor 183 passes through the first through hole 162h formed in the first conversion conductor layer 162, and The insulation from the conversion conductor layer 162 is maintained. FIG. 5 shows a portion in the projection grating area PLA in the NN ′ cross section in FIG.
This corresponds to the arrangement of the first and second lattice connection bumps 187L and 188L in FIG. In FIG. 5, the connection position of the second main surface side via conductor 183 connected to the second conversion conductor layer 161 from the main surface side is indicated by an x mark. Further, on the back surface side (core insulating layer side) of the second conversion conductor layer 161, the second lattice through-hole conductor 118L is connected at a position indicated by a broken circle. Here, the number and positions of the second lattice through-hole conductors 118L are as shown in FIG. That is, when the number of the second main surface side via conductors 183 and the number of the second lattice through-hole conductors 118L are compared, the number of the second lattice through-hole conductors 118L is reduced so as to be easily understood. The second lattice through-hole conductor 118L is formed at a position overlapping the second main surface side via conductor 183 in FIG. That is, the second lattice through-hole conductor 118L is formed coaxially with the second main surface side via conductor 183. Therefore, the coaxial second lattice through-hole conductor 118L is separated from the second main surface side via conductor 183 by only the thickness of the second conversion conductor layer 161 and is generated at this portion. Since the resistance and inductance are extremely small, the combined resistance and combined inductance can be reduced as a whole.

In the present embodiment, the core insulating layer 11
The second conversion conductor layer 161 is formed on the core main surface 110b of the first main surface 110b, and the main surface side of the main surface side insulating layer 122 (the interlayer 1)
42), since the first conversion conductor layer 162 is formed, both the first and second conversion conductor layers are located closest to the through-hole conductor, and the first and second conversion conductor layers 161, 16
The distance from the second to the first and second lattice connection bumps 187L and 188L is the longest, and the distance from the first and second lattice through-hole conductors 117L and 118L is the shortest. Therefore, since the parallel paths are formed long, the first and second paths have low resistance and low inductance as a whole.
The grid connection bumps 187L and 188L can be connected to the first and second grid through-hole conductors 117L and 118L.

Further, the second lattice through-hole conductor 118
The position of L is regular, and the second main surface side via conductor 1
The grid constituted by 83 (the grid which appears obliquely in FIG. 5)
Is selected so as to form a grid having a triple interval. In this manner, the connection position and the number of connections of the second main surface side via conductor 183 can be changed by the second conversion conductor layer, and can be easily connected to the second lattice through-hole conductor 118L. Further, in the second conversion conductor layer 161, second through holes 161h are formed at various places, in which the first lattice through-hole conductor 117L is located. Try to keep the insulation. Here, as can be easily understood from FIG. 1 and the relationship between FIG. 4 and FIG. 5, the first core-side via conductor 184 extending from the first conversion conductor layer 162 to the back side is the first lattice through-hole conductor 117L. Connected to

Thus, the first and second conversion conductor layers 1
61, 162, the first and second lattice connection bumps 187L,
188L, the first and second main surface side via conductors 182,
By converting the connection position and the number of connections in the core insulating layer 110, as shown in FIG.
The lattice through-hole conductors 117L and 118L are alternately arranged in a vertical and horizontal lattice again, and have a lattice spacing TP.
Is three times the lattice spacing BP of the first and second lattice connection bumps 187L and 188L.

According to such a method, the core insulating layer 11
0, first and second lattice through-hole conductors 117
The first and second lattice through-hole conductors 117L and 118L and the first and second lattice connection bumps 187L and 18 having a small lattice spacing BP are formed while increasing the lattice spacing TP of the L and 118L.
The connection with 8L can be easily made, and the wiring layout design of the wiring board becomes extremely easy.

Thus, the first and second lattice through-hole conductors 117L and 118L whose lattice spacing is tripled are provided.
Are from the core back surface 110c to the back side insulating layers 132 to 135
Are connected to the first and second back side via conductors 192 and 193, respectively. First and second backside via conductors 192,
193 also has its lattice spacing VP (VP = TP = 450 μm)
, And are alternately arranged in a grid pattern, and are connected to the first and second capacitor connection pads 195 and 196 formed on the back surface of the back surface insulating layer 135, respectively. The first and second capacitor connection pads 195 and 196 include:
As described above, the chip capacitor 210 is connected.

The chip capacitor 210 has a substantially rectangular parallelepiped shape as shown in FIG.
A large number of capacitor terminals 212 are arranged in a grid pattern on 10b, which is a multilayer ceramic capacitor having a structure as shown in FIG. 7B. That is, the chip capacitor 210 has a laminated structure in which the high dielectric constant ceramics 215 made of BaTiO3 or the like and the electrode layers 221 and 222 are alternately laminated.
The via 224 is connected to the electrode 221 of every other layer,
The electrode 222 is connected to every other layer. These vias 223 and 224 are respectively connected to first and second capacitor terminals 213 and 214 formed on the connection surface 210b side. First and second capacitor terminals 213 and 214
Are alternately arranged in a grid with a predetermined grid interval CP (in the present embodiment, CP = VP = 450 μm) substantially equal to the grid interval VP of the first and second back side via conductors 192 and 193. Solder 199 is attached to the first and second capacitor terminals 213 and 214 as necessary. In addition, in order to prevent the problem due to the spread of solder wet,
A solder resist layer 216 may be formed around the second capacitor terminals 213 and 214. Since the chip capacitor 210 has the above-described structure, a capacitor as shown in FIG. 7C is formed between the first capacitor terminal 213 and the second capacitor terminal 214. .

As described above, the above-described chip capacitor 2
10, the first and second capacitor terminals 213 and 214
Is a predetermined interval CP substantially equal to the lattice interval VP of the first and second back side via conductors 192 and 193 (in the present embodiment, the predetermined interval CP is
= VP = 450 μm). Therefore, the first and second capacitor terminals 213 and 214 of the chip capacitor can be easily connected to the first and second capacitor connection pads 195 and 196 of the wiring board main body 101, respectively. Moreover, the first and second back side via conductors 192 and 193 and the first and second capacitor terminals 2
Since only the first and second capacitor connection pads 195 and 196 are interposed between the first and second capacitors 13 and 214, the resistance and inductance generated between them can be suppressed.

Further, in the present embodiment, as shown on the left side of FIG.
Via the first and second through-hole conductors 117 and 118 and the core-side via conductor 172, the first and second conversion conductor layers 16
By supplying a + power supply potential or a ground potential (represented by a + or G symbol) to the first
0 and the electronic component 20. By mounting such a chip capacitor 210 on the back surface 100c of the wiring board 100, the chip capacitor 210 is arranged immediately below the electronic component 20 such as an IC chip, and both of them are connected in parallel by using a large number of via conductors. Because the connection between
A stable power supply potential and ground potential can be supplied through a low resistance and low inductance path.

Next, a method of manufacturing the wiring board 100 will be described. The wiring board 100 may be formed by a known method of forming a build-up wiring board and a multilayer ceramic capacitor. For example, a resin layer 111 made of a glass-epoxy resin composite material is prepared, and resin layers 112 and 113 and a copper foil are respectively laminated and cured on the upper and lower surfaces. Then, a laser is inserted through the through hole 110h at a necessary portion,
Drill holes and perform panel plating, and fill the through holes with resin. After curing, the upper and lower surfaces are polished, electroless plating and electrolytic plating are performed to form a plating layer also on the upper portion (lower portion) of the filling resin, and then patterning is performed to complete the core insulating layer 110 in which a through-hole conductor is formed. I do. Thereafter, an insulating layer, a wiring layer, a conversion conductor layer, a via conductor, and the like are sequentially formed by a build-up technique, plating, and an etching technique to complete the wiring board main body 101. After that, the separately formed chip capacitor 210 is mounted by soldering to complete the wiring board 100.

(Modification 1) Next, Modification 1 of this embodiment will be described with reference to FIG. In the wiring board 100 according to the first embodiment, the core insulating layer 110 composed of three insulating layers is the center, and the main-surface-side insulating layers 122 to 125 are used.
And a back insulating layer 132 to 135, and a core insulating layer 1
10 is provided with a second conversion conductor layer 161 on the core main surface 110b and a first conversion conductor layer 162 between adjacent layers 142. The second conversion conductor layer 161 is directly connected to the second lattice through-hole conductor 118L. It was shown. On the other hand, as shown in FIG. 8, the wiring board 300 according to the second modification uses a single core insulating layer 311 as a core insulating layer,
The second conversion conductor layer 161 may be formed between the main surface side insulating layers. Specifically, in the present modification, the main surface side insulating layer 3
The second conversion conductor layer 161 is formed between the layers 341 between the layers 21 and 122. Further, the first conversion conductor layer 162 is formed between the main surface side insulating layer 122 and the interlayer 142 between the main surface side insulating layer 123 adjacent thereto. However, in the wiring board 300, as shown in FIGS. 4 and 5, a first core-side via conductor 384 extends from the first conversion conductor layer 162 instead of the first core-side via conductor 184. Also, the second conversion conductor layer 161
Through the second through hole 161h, and is connected to the first lattice through-hole conductor 317L. Further, a second core-side via conductor 385 extends from the second conversion conductor layer 161,
It is connected to the second lattice through-hole conductor 318L.

Even in this case, similar to the first embodiment,
The through-hole conductors 317 and 318 are formed while increasing the lattice spacing of the through-hole conductors formed in the core insulating layer 110.
And the first and second connection bumps 187 and 18 having a narrow lattice spacing.
8 can be easily made, and the wiring layout design of the wiring board becomes extremely easy.

(Modification 2) Still another modification will be described with reference to FIGS. Embodiment 1
In the above, an example in which a single chip capacitor 210 is used as the chip capacitor mounted on the wiring board 100 has been described. However, a plurality of chip capacitors may be mounted. In this modification, the chip capacitor 410
The following describes a wiring board on which a plurality of components are mounted. The wiring board body 501 is substantially the same as the wiring board body 101 used in the first embodiment. However, a plurality of chip capacitors 410
The chip capacitors 4 adjacent to each other
In the vicinity of the gap (boundary) of No. 10, the first and second capacitor connection pads 195 and 196 and the solder
Capacitor terminal 413 or second capacitor terminal 41
4, the first and second back side via conductors 192, 19
3 may occur. To cope with this, the wiring substrate body 501 includes first and second extending portions 595E extending from the first and second capacitor connection pads 195 and 196 in the vicinity.
L, 596EL, and the first and second extending portions 595
First and second backside via conductors 1 left over EL and 596EL
92 and 193 are connected.

That is, as shown in FIG. 9, when a plurality of chip capacitors 410 are mounted on the wiring substrate body 501, the side surfaces 417S1
And the gap between the chip capacitor 410 and the side surface 417S3 of another chip capacitor cannot be made extremely small. , 193
May be located (for example, the center first backside via conductor 192 in FIG. 9). In such a case, it is conceivable to insulate only the first and second back-side via conductors 192 and 193 so as not to connect them to others. However, as in the present modification shown in FIG. 10, nearby first and second capacitor connection pads 195, 1
First and second extending portions 595EL, 596E extending from 96
L are formed, and the first and second extending portions 595E are formed.
L and 596EL are connected to the first and second rear surface side via conductors 192 and 193 located at portions corresponding to the gaps. By doing so, as shown in FIG. 11, the first and second back side via conductors 192 and 193 are also provided via the first and second extending portions 595EL and 596EL.
It can be connected to the first and second capacitor terminals 413 and 414. Moreover, the first and second extending portions 595EL, 5
95EL via the first and second back side via conductors 192,
Since the number of routes connecting to 193 has increased,
Resistance and inductance generated between the second back side via conductors 192 and 193 and the first and second capacitor terminals 413 and 414 can be further suppressed.

In this modification, as shown in FIG. 12, each of the capacitor terminals 412 (first and second capacitor terminals 413 and 414) is used as the chip capacitor 410.
Are the peripheral edges 410P1, 410P2 of the connection surface 410b.
The first and second capacitor terminals 413 and 414 located on the outermost periphery and the four side surfaces 417S1 and 417 are arranged in a lattice shape parallel or orthogonal to 410P3 and 410P4.
Intervals SS1 and SS with S2, 417S3 and 417S4
2, SS3 and SS4 are smaller than the lattice spacing CP of the capacitor terminal 412. Therefore, as shown in FIG. 11, the distance between the terminals of adjacent chip capacitors is twice (2 times) the lattice spacing CP of the capacitor terminals.
Also in the second modification in which CP = 900 μm), a gap ΔS is provided between adjacent chip capacitors 410,
It can be easily arranged. However, in the present embodiment, since the intervals SS1 and the like are all the same, they are represented by the intervals SS.

(Modification 3) Still another modification will be described with reference to FIGS. In the second modification, the interval between the terminals of the adjacent chip capacitors 410 is twice (2C) the lattice intervals CP of the capacitor terminals.
P), but the interval between the terminals can be further increased. That is, the third modification shown in FIGS.
In the wiring board body 601, the spacing between the terminals of the chip capacitor 410 to be mounted is set to be three times (3CP) the lattice spacing CP of the capacitor terminals.

Also in this case, FIGS.
, The first and second extending portions 695E extending from the nearby first and second capacitor connection pads 195 and 196.
L, 696EL are formed, and the first and second extending portions 695 are formed.
The first and second backside via conductors 192 and 193 near the position corresponding to the gap are connected to EL and 696EL. In this way, as shown in FIGS. 13 and 14, the first and second back-side via conductors 192 and 193 which could not be connected to the capacitor terminals 413 and 414 are also provided with the first and second extending portions. It can be connected to the first and second capacitor terminals 413 and 414 via 695EL and 696EL. Moreover, the first and second extension portions 695E
L, 695EL via first and second backside via conductors 1
Since the number of routes connecting to 92 and 193 has increased,
The first and second back side via conductors 192 and 193 and the first and second
Resistance and inductance generated between the capacitor terminals 413 and 414 can be further suppressed.

Although the present invention has been described with reference to the embodiment and the first to third modifications, the present invention is not limited to the above-described embodiment and the like, and may be appropriately modified without departing from the gist thereof. Needless to say, it can be applied.

[Brief description of the drawings]

FIG. 1 is a sectional view of a wiring board according to a first embodiment.

FIG. 2 is a plan view of the wiring board according to the first embodiment.

FIG. 3 is an explanatory diagram showing an arrangement of first and second grid connection terminals located in a grid area in the wiring board according to the first embodiment;

FIG. 4 is an explanatory diagram illustrating a relationship between a first conversion conductor layer, a first main surface side via conductor, and a second main surface side via conductor in a projection grid region in the wiring board according to the first exemplary embodiment.

FIG. 5 is an explanatory diagram illustrating a relationship between a second conversion conductor layer, a first core-side via conductor, and a second main surface-side via conductor in a projection grid region in the wiring board according to the first exemplary embodiment.

FIG. 6 is a diagram illustrating a relationship between a first lattice through-hole conductor and a second lattice through-hole conductor and a relationship between first and second lattice terminals in a projection lattice region in the wiring board according to the first embodiment; FIG.

7A is a perspective view of a chip capacitor mounted on the back side of the wiring board according to the first embodiment, FIG. 7B is a cross-sectional explanatory view for explaining the internal structure of the capacitor, and FIG. FIG. 3 is a circuit diagram illustrating a relationship with first and second terminals.

FIG. 8 is a sectional view of a wiring board according to a first modification;

FIG. 9 is a cross-sectional view showing a relationship between each terminal of a chip capacitor and a structure of a wiring board body near the terminal when a plurality of chip capacitors are mounted on the back surface side of the wiring board according to Modification 2; is there.

FIG. 10 is a cross-sectional view showing a relationship between the first and second lattice via conductors, the first and second capacitor connection pads, and the first and second extending portions, in the wiring board according to Modification 2; is there.

FIG. 11 is a cross-sectional view showing a relationship between first and second capacitor connection pads and first and second extending portions, and first and second terminals of a chip capacitor in the wiring board according to Modification 2; It is.

FIG. 12 is a perspective view of a chip capacitor mounted on a rear surface side of a wiring board according to a second modification.

FIG. 13 is a diagram illustrating a wiring board according to Modification 3, in which a plurality of chip capacitors are mounted on the back surface side.
It is sectional drawing which shows the relationship between each terminal of a chip capacitor, and the structure of the wiring-board main body of the vicinity.

FIG. 14 is a cross-sectional view illustrating a relationship between first and second lattice via conductors, first and second capacitor connection pads, and first and second extending portions, in the wiring board according to Modification 3. is there.

FIG. 15 is a wiring board according to Modification 3, and is a cross-sectional view showing a relationship between first and second capacitor connection pads and first and second extending portions, and first and second terminals of a chip capacitor. It is.

FIG. 16 is an explanatory diagram showing a conventional wiring board having a chip capacitor mounted on a main surface or a back surface of the substrate.

[Explanation of symbols]

Reference Signs List 20 IC chip (electronic component) 100, 300 Wiring board 100b, 300b Main surface 100c, 300c Back surface 101, 301 Wiring substrate body 110, 311 Core insulating layer 110b, 311b Core main surface 110c, 311c Core back surface 111, 112, 113 Insulation Layers 114, 115, 117, 118, 314, 315, 3
17,318 Through-hole conductor 117L, 317L First lattice through-hole conductor 118L, 318L Second lattice through-hole conductor 122,123,124,125,321 Main surface side resin insulation layer 132,133,134,135,331 Back side Resin insulation layer 126, 136 Solder resist layer 161 Second conversion conductor layer 161h Second through hole 162 First conversion conductor layer 162h First through hole 182 First main surface side via conductor 183 Second main surface side via conductor 184, 384 First core side via conductor 185 Connection pad 187 First connection bump (first connection terminal) 188 Second connection bump (second connection terminal) 187L First lattice connection bump (first lattice connection terminal) 188L Second lattice connection bump (Second lattice connection terminal) 189 Connection bump (Connection terminal) 385 Second core side via conductor 192 First backside via conductor 193 Second backside via conductor 195 First capacitor connection pad (first capacitor connection terminal) 196 Second capacitor connection pad (second capacitor connection terminal) 210, 410 Chip capacitor 210b, 410b Connection surface 212 capacitor terminal 213, 413 first capacitor terminal (first terminal) 214, 414 second capacitor terminal (second terminal) LA lattice area PLA projection lattice area CP lattice spacing of capacitor terminals VP first connection bump and second connection bump Grid spacing

Continued on the front page (72) Inventor Yukihiro Kimura 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi F-term in Japan Special Ceramics Co., Ltd. 5E001 AB03 5E082 AA01 AB03 DD11 DD13 EE35 FF05 5E346 AA04 AA06 AA12 AA15 AA32 AA43 BB02 BB03 BB04 BB06 BB07 BB11 BB16 BB20 FF01 FF45 GG15 GG17 GG28 HH01 HH22

Claims (11)

[Claims] 1. A wiring board having a main surface and a back surface, comprising: a plurality of connection terminals formed on the main surface side and connectable to terminals of electronic components mounted on the main surface; A plurality of first connection terminals having a first potential and a plurality of second connection terminals having a common second potential, wherein at least one of the first connection terminal and the second connection terminal has a first predetermined interval A first grid connection terminal and a second grid connection terminal, which are alternately arranged in a grid pattern to form a grid area, and a core insulation having one or a plurality of insulating layers and having a core main surface and a core back surface A plurality of first through-hole conductors having a common first potential, a plurality of first through-hole conductors having a common first potential, and a plurality of first through-hole conductors penetrating between the core main surface and the core back surface of the core insulating layer. Including a large number of second through-hole conductors Also, at least one of the first through-hole conductors and the second through-hole conductors located in the projection lattice area where the lattice area is projected toward the back side in the thickness direction is alternately arranged in a lattice pattern at a second predetermined interval. A first lattice through-hole conductor and a second lattice through-hole conductor, which are arranged in the first lattice through-hole conductor; and a plurality of first through-holes interposed between the core main surface of the core insulating layer and the connection terminal. A first conversion conductor layer having a plurality of second through-holes located between the first conversion conductor layer and the core main surface of the core insulating layer; A first main surface side via conductor extending from the first lattice connection terminal toward the back surface side in the thickness direction of the wiring substrate, and electrically connected to the first conversion conductor layer; The above wiring from the grid connection terminals A second main conductor extending toward the back side in the thickness direction of the substrate and electrically connected to the second conversion conductor layer through the first through hole while being insulated from the first conversion conductor layer, respectively. A surface-side via conductor and each of the first lattice through-hole conductors in the projection lattice region extend toward the principal surface side in the thickness direction of the wiring board, and are respectively insulated from the second conversion conductor layer. (2) a first core-side via conductor connected to the first conversion conductor layer through the through-hole, and a main surface side in the thickness direction of the wiring board from the second lattice through-hole conductor in the projection lattice region, And a second core-side via conductor connected to the second conversion conductor layer, wherein the second lattice interval is larger than the first lattice interval, and the first core in the projection lattice region is provided. The number of side via conductors is above the grid area A wiring board having a number smaller than the number of the first main surface side via conductors and a number of the second core side via conductors in the projection grid region smaller than the number of the second main surface side via conductors in the grid region; . 2. The wiring board according to claim 1, wherein the second lattice spacing is an odd multiple of the first lattice spacing, and each of the first core-side via conductors is the first main surface. A wiring board which is substantially coaxial with a side via conductor, and wherein the second core side via conductor is substantially coaxial with the second main surface side via conductor. 3. A wiring board having a main surface and a back surface, comprising: a plurality of connection terminals formed on the main surface and connectable to terminals of electronic components mounted on the main surface; A plurality of first connection terminals having a first potential and a plurality of second connection terminals having a common second potential, wherein at least one of the first connection terminal and the second connection terminal has a first predetermined interval A first grid connection terminal and a second grid connection terminal, which are alternately arranged in a grid pattern to form a grid area, and a core insulation having one or a plurality of insulating layers and having a core main surface and a core back surface A plurality of first through-hole conductors having a common first potential, a plurality of first through-hole conductors having a common first potential, and a plurality of first through-hole conductors penetrating between the core main surface and the core back surface of the core insulating layer. Including a large number of second through-hole conductors Also, at least one of the first through-hole conductors and the second through-hole conductors located in the projection lattice area where the lattice area is projected toward the back side in the thickness direction is alternately arranged in a lattice pattern at a second predetermined interval. A first lattice through-hole conductor and a second lattice through-hole conductor, which are arranged in the first lattice through-hole conductor; and a plurality of first through-holes interposed between the core main surface of the core insulating layer and the connection terminal. A first conversion conductor layer, a second conversion conductor layer located on a core main surface of the core insulating layer, the second conversion conductor layer having a plurality of second through holes, and a first grid connection terminal in the grid region. A first main surface side via conductor extending toward the back side in the thickness direction of the substrate and electrically connected to the first conversion conductor layer, respectively; Towards the back side in the thickness direction A second main-surface-side via conductor that extends through the first conversion conductor layer and electrically connects to the second conversion conductor layer through the first through hole while being insulated from the first conversion conductor layer; A first core-side via conductor extending from the first lattice through-hole conductor in the region toward the main surface in the thickness direction of the wiring board, and connected to the first conversion conductor layer; The grid through-hole conductor is located in the second through-hole and insulated from the second conversion conductor layer, and the second grid through-hole conductor in the projection grid region is directly in contact with the second conversion conductor layer. The second lattice spacing is greater than the first lattice spacing, and the number of the first core-side via conductors in the projection lattice area is greater than the number of the first main surface-side via conductors in the lattice area. And the number of the Less wiring board than the number of the number of grid through-hole conductors is the second main surface side via conductors within the grating region. 4. The wiring board according to claim 3, further comprising a plurality of main surface side insulating layers between a core main surface of the core insulating layer and the connection terminal, wherein the first conversion conductor layer is provided. Is a wiring board arranged on the main surface side of the main surface side insulating layer closest to the core insulating layer among the main surface side insulating layers. 5. The wiring board according to claim 3, wherein the second grid interval is an odd multiple of the first grid interval, and the first core-side via conductors are all the same. A wiring board which is substantially coaxial with the first main surface side via conductor, and wherein each of the second lattice through-hole conductors is substantially coaxial with the second main surface side via conductor. 6. A wiring board comprising one or a plurality of chip capacitor capacitors mounted on a wiring board body, wherein the chip capacitor comprises one electrode and the other electrode constituting a capacitor, a connection surface, and the connection surface. A plurality of first terminals formed on the connection surface and connected to the one electrode, and a plurality of second terminals formed on the connection surface and connected to the other electrode, wherein the first terminal and the second terminal are Chip capacitors that are alternately arranged in a grid pattern at a predetermined interval. The wiring board body includes a capacitor mounting surface on which the chip capacitors are mounted, one or more insulating layers, and a via conductor penetrating the insulating layers. And a first via conductor having a common first potential and a second via conductor having a common second potential, wherein at least one of the first via conductor and the second via conductor includes: Via conductors, which are first lattice via conductors and second lattice via conductors, which are alternately arranged in a lattice at substantially the same interval as the predetermined interval, and a terminal on the capacitor mounting surface side of the surface formed by the insulating layer A first capacitor connection terminal formed on the formation surface at a position facing the first terminal of the chip capacitor with the connection surface facing the capacitor mounting surface side, and connected to the first lattice via conductor; And a second capacitor connection terminal formed on a formation surface, facing the second terminal of the chip capacitor, and connected to the second lattice via conductor. 7. The wiring board according to claim 6, wherein the chip capacitor includes a plurality of chip capacitors, and the first terminal or the second terminal of one chip capacitor and the chip terminal of another chip capacitor adjacent to the first terminal or the second terminal. The interval between the two terminals or the first terminal is an integer multiple of 2 or more of the predetermined interval, and among the first lattice via conductors, the first lattice via conductor not connected to the first capacitor connection terminal is the terminal A second grid via conductor connected to a first extending portion formed on a formation surface and extending from any one of the first capacitor connection terminals, and not connected to the second capacitor connection terminal among the second grid via conductors Is a wiring board formed on the terminal formation surface and connected to a second extending portion extending from any one of the second capacitor connection terminals. 8. The wiring board according to claim 7, wherein the first terminal or the second terminal of the one chip capacitor and a second terminal or a first terminal of another chip capacitor adjacent thereto. The wiring board whose interval is twice the predetermined interval. 9. A wiring board main body for mounting one or a plurality of chip capacitor capacitors to form a wiring board, wherein the chip capacitor comprises one electrode and the other electrode constituting a capacitor, a connection surface, A plurality of first terminals formed on the connection surface and connected to the one electrode; and a plurality of second terminals formed on the connection surface and connected to the other electrode, wherein the first terminal and the second terminal Are chip capacitors alternately arranged in a grid pattern at a first predetermined interval, wherein the wiring board body has a capacitor mounting surface on which the chip capacitors are mounted, one or a plurality of insulating layers, and penetrates the insulating layers. A first via conductor having a common first potential and a second via conductor having a common second potential, wherein at least one of the first via conductor and the second via conductor is provided. The first and second lattice via conductors are alternately arranged in a lattice pattern at substantially the same interval as the predetermined interval, and the capacitor mounting is the most of the surfaces formed by the insulating layers. A first capacitor formed at a position facing the first terminal when mounting the chip capacitor with the connection surface facing the capacitor mounting surface on the surface side, and connected to the first lattice via conductor; A connection terminal, a second capacitor connection formed on the same surface as the first capacitor connection terminal, formed at a position facing the second terminal when the chip capacitor is mounted, and connected to the second lattice via conductor; A wiring board body comprising: a terminal; 10. The wiring board body according to claim 9, wherein said chip capacitor is plural, and said first terminal or second terminal of one chip capacitor is connected to another chip capacitor adjacent thereto. An interval between the second terminal and the first terminal is an integer multiple of 2 or more of the predetermined interval, and among the first lattice via conductors, the first lattice via conductor not connected to the first capacitor connection terminal is A second lattice via formed on the terminal formation surface and connected to a first extension extending from any one of the first capacitor connection terminals, and not connected to the second capacitor connection terminal among the second lattice via conductors A wiring board body, wherein a conductor is formed on the terminal formation surface and is connected to a second extending portion extending from any one of the second capacitor connection terminals. 11. A chip capacitor comprising one electrode and the other electrode constituting a capacitor, the chip capacitor having a substantially rectangular parallelepiped shape, a substantially rectangular connection surface, four side surfaces orthogonal to the connection surface, and the connection surface. And a plurality of first terminals connected to the one electrode, and a plurality of second terminals formed on the connection surface and connected to the other electrode. The first terminal and the second terminal Are alternately arranged at a predetermined interval in a lattice shape parallel and orthogonal to any one of the peripheral edges of the connection surface, and the first terminal and the second terminal, which are located at the outermost periphery of the connection surface, A chip capacitor in which the distance between the outer first terminal and the outermost second terminal and the four side surfaces is smaller than the predetermined distance.