JP2009170941A - Capacitor mounting wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to improvement in operation reliability of a mounted semiconductor element etc., by reducing ESL of a mounted capacitor and performing effective decoupling. <P>SOLUTION: On the capacitor mounting wiring board 10b, a plurality of wiring layers 14a and 14b, 16a and 16b, and 18a and 18b patterned in necessary shapes respectively are laminated with insulating layers 15a and 15b, and 17a and 17b interposed, and connected to each other through conductors formed penetrating the insulating layers along the thicknesses. A capacitor 1 for decoupling is electrically connected to the wiring layers in vicinity to the wiring layer 18a as the outermost layer provided as a power line or ground line, and surface-mounted such that when a current flows to the capacitor 1, the direction of the current is opposite to the direction of a current flowing to the wiring layer 18a and a path of the current flowing to the capacitor is substantially parallel to a path of the current flowing to the wiring layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board on which a capacitor is mounted, and more specifically, a wiring on which a decoupling capacitor is surface-mounted for mounting a semiconductor element (chip) or an electronic component that requires high-speed switching operation. The present invention relates to a substrate (capacitor-mounted wiring substrate).

  In this specification, the wiring board is also referred to as a “semiconductor package” for the sake of convenience in the sense that it serves as a package for mounting a semiconductor element or the like. A wiring board (semiconductor package) on which a semiconductor element or the like is mounted is called a “semiconductor device”.

  In recent years, printed circuit boards have been required to be lighter, and equipped with BGA (Ball Grid Array), PGA (Pin Grid Array), CSP (Chip Size Package), etc., which are small and multi-pinned. Therefore, miniaturization and high density of wiring are required. However, since a conventional printed wiring board requires a large area for forming a via hole, the degree of freedom in design is limited and it is difficult to miniaturize the wiring. Therefore, a printed wiring board (build-up multilayer wiring board) using a build-up method has been put into practical use in recent years. This build-up multilayer wiring board can be manufactured in various types by combining the material of the interlayer insulating layer and the process of forming the via hole. The basic process is for the formation of the insulating layer and the interlayer connection in the insulating layer. The conductor layers are stacked while successively repeating the formation of the via holes and the formation of the conductor layers (patterned wiring, pads, etc.) including the inside of the via holes. In a multilayer wiring board obtained by such a build-up method, it is possible to mount even a semiconductor element (chip) whose degree of integration has progressed.

  However, on the other hand, since each wiring pattern is close to each other in such a multilayer wiring board (semiconductor package), crosstalk noise occurs between the wirings, and the potential of the power supply line, ground line, etc. fluctuates. Problems can arise. In particular, in semiconductor packages equipped with semiconductor elements and electronic components that require high-speed switching operation, crosstalk noise is likely to occur as the frequency increases, and switching occurs because the switching elements are turned on and off at high speed. Noise is generated, and the potential of the power supply line or the like is likely to fluctuate. This leads to a decrease in the operational reliability of the mounted semiconductor elements and the like, which is not preferable.

  Therefore, for the purpose of stabilizing the power supply voltage and reducing switching noise or the like, conventionally, a capacitor element such as a chip capacitor has been attached to a semiconductor package on which a semiconductor element is mounted to “decouple” the power supply line or the like. Has been done. As a typical method, there is a method in which a chip capacitor is surface-mounted by soldering or the like on the same surface as the side on which a semiconductor element or the like of a semiconductor package is mounted or on the opposite side.

  However, in this case, the thickness of the entire package is increased by the amount of the capacitor provided on the surface of the semiconductor package, and the routing distance of the wiring connecting the capacitor and the semiconductor element is increased, resulting in an increase in inductance. Sometimes. If the inductance is large, effective “decoupling” cannot be performed. Therefore, it is desirable that the inductance is as small as possible. For this purpose, it is desirable to place the capacitor as close to the semiconductor element as possible. In addition, it has been common knowledge in the art to dispose a capacitor close to a semiconductor element in this way.

  As a technique related to the above conventional technique, for example, as described in Patent Document 1, a decoupling capacitor is built in a resin multilayer circuit board obtained by a build-up method, and the capacitor is configured. There is one in which a dielectric layer sandwiched between two conductor patterns is formed of a material (resin) having a relative dielectric constant of a predetermined value or more.

JP-A-11-68319

  As described above, in the conventional technology, in order to reduce the inductance of the decoupling capacitor as much as possible, the wiring distance between the two is made as short as possible by arranging the capacitor close to the semiconductor element. . At this time, no consideration has been given to the magnetic coupling between the current flowing through the capacitor and the plane wiring pattern in the vicinity thereof, particularly the power plane or the ground plane.

  For this reason, when the capacitor and the semiconductor element are connected, the equivalent series inductance (ESL) of the capacitor cannot always be reduced simply by the short wiring distance between the two. For example, there is a plane wiring pattern connected to the capacitor in the vicinity of the long plate-shaped chip capacitor, and the current flowing in the capacitor in a state where the wiring pattern is parallel to the longitudinal direction of the capacitor. And the direction of the current flowing through the wiring pattern are the same, the direction of the magnetic field generated by the current flowing through the capacitor and the direction of the magnetic field generated by the current flowing through the wiring pattern are the same direction. The inductance is apparently increased under the influence of the magnetic field.

  That is, there is a problem that the ESL of the capacitor cannot always be reduced satisfactorily depending on the relationship between the arrangement of the capacitor and the arrangement of the wiring pattern in the vicinity thereof and the direction of the flowing current.

  The present invention has been created in view of the problems in the prior art, and enables effective decoupling by reducing the equivalent series inductance (ESL) of a capacitor to be mounted. An object of the present invention is to provide a capacitor-mounted wiring board that can contribute to improvement in performance.

  In order to solve the above-described problems of the prior art, according to the present invention, a plurality of wiring layers each patterned in a required shape are stacked via an insulating layer, and the insulating layer is arranged in the thickness direction. The capacitors are connected to each other through conductors formed therethrough, and the capacitor is provided on at least one of the same surface as the side on which the semiconductor element or the electronic component is mounted and the opposite surface, The wiring layer is electrically connected to the wiring layer in the vicinity of the outermost wiring layer provided as a power supply line or a ground line, and the current direction and the wiring when a current is passed through the capacitor Capacitor mounting characterized in that the direction of the current flowing through the layer is reverse and that the path of the current flowing through the capacitor is substantially parallel to the path of the current flowing through the wiring layer Line substrate is provided.

  According to the configuration of the capacitor-mounted wiring board according to the present invention, the capacitor is disposed close to the outermost wiring layer provided as a power supply (or ground), and flows through the capacitor and the wiring layer. Since surface mounting is performed so that the current paths are substantially parallel, the magnetic coupling between the current flowing in the capacitor and the current flowing in the wiring layer is enhanced. Further, since the directions of both currents are opposite to each other, the magnetic fields generated by the respective currents cancel each other. As a result, the equivalent series inductance (ESL) of the capacitor is apparently reduced due to the influence of the magnetic field from the wiring layer (the magnetic field acting in the direction to cancel the magnetic field generated by itself). That is, ESL of the capacitor can be reduced. As a result, effective decoupling can be performed, and it is possible to contribute to improvement of operation reliability of a semiconductor element to be mounted.

It is sectional drawing which shows the structure of the capacitor mounting wiring board which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board based on the 6th Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board which concerns on the 7th Embodiment of this invention. It is sectional drawing which shows the structure of the capacitor mounting wiring board based on the 8th Embodiment of this invention. FIG. 8 is a cross-sectional view showing a manufacturing process (No. 1) of a main part (part related to a chip capacitor connection form) of the capacitor-mounted wiring board according to the embodiment of FIG. 7; FIG. 10 is a cross-sectional view showing a manufacturing process (No. 2) subsequent to the manufacturing process of FIG. 9; It is sectional drawing which shows the manufacturing process (the 1) of the principal part (part which concerns on the connection form of a chip capacitor) of the capacitor mounting wiring board which concerns on embodiment of FIG. It is sectional drawing which shows the manufacturing process (the 2) following the manufacturing process of FIG. It is the figure which contrasted and showed the equivalent series inductance (ESL) obtained when the chip capacitor is mounted on the surface and when embedded. It is sectional drawing which shows the structure of the capacitor part in the capacitor mounting wiring board which concerns on the modification of embodiment of FIG.

  FIG. 1 schematically shows the configuration of a capacitor-mounted wiring board (semiconductor package) according to a first embodiment of the present invention in the form of a cross-sectional view. In the illustrated example, a configuration in which the chip capacitor 1 is mounted on the back surface of the semiconductor package 10 (the surface opposite to the side on which the semiconductor element 2 is mounted) is shown.

  In the semiconductor package 10 according to the present embodiment, 11 is an insulating base material (for example, glass cloth impregnated with a thermosetting resin such as epoxy resin or polyimide resin) as a core substrate of the package, and 12 is a core. A conductor (for example, a metal such as copper (Cu)) formed on the inner wall of a through hole formed through a required portion of the substrate 11 in the thickness direction, and 13 is an insulator filled inside the conductor 12 ( For example, epoxy resin or the like), 14a and 14b are each a wiring layer (for example, Cu) patterned in a required shape on both surfaces of the core substrate 11, and 15a and 15b are respectively on the core substrate 11 and the wiring layers 14a and 14b. The formed resin layer (for example, epoxy resin layer), 16a, 16b as an interlayer insulating layer is electrically connected to a part of the wiring layers 14a, 14b, respectively. Wiring layers patterned in a required shape on 5a and 15b, 17a and 17b are resin layers 15a and 15b and resin layers formed on the wiring layers 16a and 16b, and 18a and 18b are wiring layers 16a and 16b, respectively. The wiring layers 19a and 19b, which are electrically connected to a part of the resin layer and patterned in the required shape on the resin layers 17a and 17b, are formed on the resin layers 17a and 17b and the wiring layers 18a and 18b, respectively. Reference numerals 20a and 20b denote wiring layers that are electrically connected to parts of the wiring layers 18a and 18b, respectively, and are patterned in a required shape on the resin layers 19a and 19b.

  Reference numerals 21a and 21b each have an opening at a predetermined portion, and a solder resist layer as a protective film formed on the wiring layers 20a and 20b and the resin layers 19a and 19b. Reference numeral 22 denotes a lower solder resist layer 21b. Solder bumps as external connection terminals joined to the respective pad portions (a part of the wiring layer 20b) exposed from the openings of the solder, and 23 are two pads exposed from the openings of the solder resist layer 21b. A solder for connecting the chip capacitor 1 to a portion (a part of the wiring layer 20b) is shown. At this time, in order to improve the adhesiveness of the solder, the conductor layer formed by plating nickel (Ni) / gold (Au) on the pad portion (a part of the wiring layer 20b) exposed from the opening of the solder resist layer 21b. It is desirable to keep it attached. The same applies to the pad portion (a part of the wiring layer 20a) exposed from the opening of the upper solder resist layer 21a.

  In the illustrated example, solder bumps (external connection terminals) 22 are provided, but it is not always necessary to provide them. In short, it is sufficient that the pad portion (a part of the wiring layer 20b) is exposed from the opening of the lower solder resist layer 21b so that the external connection terminals can be joined when necessary. In addition, since the chip capacitor 1 is surface-mounted on the package 10, it is desirable to use a capacitor whose thickness is as thin as possible in order to suppress the thickness of the entire package. Also in the embodiment in which the chip capacitor 1 is embedded and mounted as will be described later, it is desirable that the thickness be as thin as possible because it is embedded in the package. Therefore, in each embodiment described below including this embodiment, a thin chip capacitor 1 having a thickness of about 100 μm is used.

  Each of the wiring layers 14a, 14b, 16a, 16b, 18a, 18b, 20a and 20b is patterned in a required shape. At this time, a signal line, a power supply line (P) or a ground line having a required pattern is formed. (G) and a pad portion for interlayer connection are formed. For the wiring layers other than the outermost wiring layers 20a and 20b, each pad portion has a vertical connection via hole formed in the corresponding resin layer (this via hole is filled with a conductor (for example, Cu)). The pattern is formed corresponding to the position of On the other hand, the pad portions of the outermost wiring layers 20a and 20b correspond to the positions of the electrodes of the semiconductor element (chip) 2 to be mounted, the bonding positions of the external connection terminals 22, and the mounting positions of the chip capacitor 1, respectively. A pattern is formed. In the illustrated example, the upper wiring layer 18a and the lower wiring layer 14b are provided as power supply lines, and the upper wiring layer 14a and the lower wiring layer 18b are provided as ground lines. In each embodiment described below including this embodiment, for convenience, a wiring layer serving as a power supply line is also referred to as a “power plane” and a wiring layer serving as a ground line is also referred to as a “ground plane”.

  As will be described later, the capacitor mounting wiring board (semiconductor package) 10 according to the present embodiment includes a chip capacitor 1 to be mounted for decoupling, and a via hole (in the example shown in FIG. 1, via holes ( In the vicinity of the lowermost wiring layer 20b) connected via the conductor filled in the plane, the plane is electrically connected to the plane, and the direction of the current when the current flows through the chip capacitor 1 (FIG. 1). In this example, the mounting is performed such that the direction from the right to the left) and the direction of the current flowing in the plane (wiring layer 20b) (the direction from the left to the right in the example of FIG. 1) are opposite to each other. It is said. Such a characteristic configuration is common to other embodiments to be described later, although there is a difference in whether the plane arranged close to the chip capacitor 1 is a power plane or a ground plane. .

  The semiconductor package 10 according to the present embodiment can be manufactured using a known technique such as a build-up method. Therefore, although the illustration of the steps of the manufacturing method is omitted, it will be briefly described as follows. For example, when the build-up method is used, first, the wiring layer 14a, the required pattern shape is formed on both surfaces of the core substrate 11 (through holes are formed at required locations and the conductors 12 and the insulators 13 are filled therein). 14b is formed, and then the formation of the resin layer (interlayer insulating layer) → the formation of the via hole for the interlayer connection in the resin layer → the formation of the wiring layer including the inside of the via hole is sequentially repeated to form the upper and lower four layers. After the wiring layers are stacked, the solder resist layers 21a and 21b are formed so as to cover the entire surface so that the pad portions of the outermost wiring layers 20a and 20b are exposed, and then from the solder resist layer 21b on the board mounting side. Solder bumps (external connection terminals) 22 are joined to the exposed pad portions, and the chip capacitor 1 is surface-mounted by soldering (23). In Rukoto, it is possible to obtain a semiconductor package 10 (FIG. 1) of the present embodiment.

  Further, when a semiconductor device is obtained by mounting the semiconductor element (chip) 2 on the package 10, for example, a pad portion (a part of the wiring layer 20a) exposed from the opening of the upper solder resist layer 21a. Further, the chip 2 is flip-chip connected so that the electrodes 3 (for example, solder bumps) bonded onto the pads of the semiconductor chip 2 are electrically connected, and further, an underfill is formed between the solder resist layer 21a. Resin 4 is filled and thermally cured and bonded. Alternatively, instead of this underfill resin 4, a non-conductive paste (NCP) is applied in advance or a non-conductive film (NCF) is pasted, and it is equivalent to the underfill resin 4 simultaneously with flip-chip connection. You may make it shape | mold in this shape.

  According to the configuration of the semiconductor package 10 (FIG. 1) according to the present embodiment, the chip capacitor 1 and the power plane (wiring layer 20b) are arranged close to each other, and the current flowing in the capacitor 1 and the direction of the current flowing in the plane Are in opposite directions, the magnetic coupling of both currents is strengthened, and the magnetic fields generated by the respective currents cancel each other. As a result, the ESL of the chip capacitor 1 is apparently reduced due to the influence of the magnetic field exerted from the power supply plane (wiring layer 20b) (that is, the magnetic field acting in the direction to cancel the magnetic field generated by the capacitor 1). In other words, the ESL of the chip capacitor 1 can be reduced, which makes it possible to perform effective decoupling and contribute to the improvement of the operational reliability of the semiconductor element (chip) 2 to be mounted. it can.

  FIG. 2 schematically shows a configuration of a capacitor-mounted wiring board (semiconductor package) according to the second embodiment of the present invention in the form of a cross-sectional view.

  In the semiconductor package 10a according to the present embodiment, the chip capacitor 1 is placed on the surface of the package 10a (on the side where the semiconductor element 2 is mounted) as compared with the semiconductor package 10 (FIG. 1) according to the first embodiment described above. This is different in that it is surface-mounted on the area around the semiconductor element mounting area (on the right side in the illustrated example). Other configurations and functions thereof are basically the same as those in the first embodiment, and thus description thereof is omitted.

  According to the second embodiment, as compared with the case of the first embodiment, the chip capacitor 1 is mounted closer to the semiconductor element 2 to be mounted, and the through-hole having a large inductance is not interposed. It is possible to further improve the electrical characteristics when viewed as a whole of the device (the semiconductor package 10a in which the semiconductor element 2 is mounted).

  FIG. 3 schematically shows the configuration of a capacitor-mounted wiring board (semiconductor package) according to a third embodiment of the present invention in the form of a sectional view.

  The semiconductor package 10b according to the present embodiment has a magnetic field generated by a ground plane (that is, a current flowing through the capacitor 1) immediately below the chip capacitor 1 as compared with the semiconductor package 10a (FIG. 2) according to the second embodiment described above. The difference is that a ground wiring layer 18a) through which a current for generating a magnetic field flows in the direction of cancellation is disposed. Due to the difference in arrangement, the number of via holes (length) existing on the path of the current flowing through the capacitor 1 is reduced as compared with the case of the second embodiment, and on the path of the current flowing through the capacitor. Since the generated inductance is reduced, the electrical characteristics of the semiconductor device (semiconductor package 10b in which the semiconductor element 2 is mounted) as a whole are improved. Other configurations and functions thereof are basically the same as those in the second embodiment, and thus description thereof is omitted.

  In the example of FIG. 3, the wiring layer 18a immediately below the chip capacitor 1 is used for grounding, but this is the same when it is used for power supply (power plane). In this case, the wiring layer 14a provided for power supply is changed to ground, and the wiring layer 14a is changed in pattern so as to be connected to the ground external connection terminal 22 (G). The pattern of the layer 18a is changed so as to be connected to the external connection terminal 22 (P) for power supply.

  According to the third embodiment, since the ground plane (or power supply plane) is arranged immediately below the chip capacitor 1, the magnetic field generated by the current flowing through the capacitor 1 is compared with the case of the second embodiment. And the magnetic field generated by the current flowing through the plane (wiring layer 18a) is further strengthened. As a result, the ESL of the chip capacitor 1 can be further effectively reduced.

  FIG. 4 schematically shows a configuration of a capacitor-mounted wiring board (semiconductor package) according to a fourth embodiment of the present invention in the form of a sectional view. In the illustrated example, a configuration in which the chip capacitor 1 is embedded and mounted in the semiconductor package 10c is shown.

  The semiconductor package 10c according to the present embodiment is lower than the core substrate 11 (semiconductor element 2) in the buildup layer constituting the package, as compared with the semiconductor package 10 (FIG. 1) according to the first embodiment described above. The difference is that the chip capacitor 1 is embedded in a build-up layer (resin layer 17b) laminated on the side opposite to the side on which is mounted. The chip capacitor 1 has one electrode connected to the power supply wiring layer 14b via a conductor (a part of the wiring layer 16b) filled in a via hole formed through the resin layer 15b in the thickness direction. The other electrode is connected to the ground wiring layer 18b through a conductor (a part of the wiring layer 18b) filled in a via hole formed through the resin layer 17b in the thickness direction. Other configurations and functions thereof are basically the same as those in the first embodiment, and thus description thereof is omitted.

  According to the fourth embodiment, since the chip capacitor 1 is sandwiched between the power plane (wiring layer 14b) and the ground plane (wiring layer 18b), each of the above-described embodiments (FIGS. 1 to 3). When the chip capacitor 1 is surface-mounted as shown in FIG. 1 (that is, the power plane (for example, the wiring layer 20b in FIG. 1) or the ground plane (for example, the wiring layer 18a in FIG. 3) is provided only on one side of the chip capacitor 1. Compared with the case of arrangement), the counter current (current flowing in each plane 14b, 18b) against the current flowing in the chip capacitor 1 is relatively increased. As a result, the ESL of the chip capacitor 1 can be further effectively reduced.

  In addition, since the chip capacitor 1 is embedded and mounted in the semiconductor package 10c, the thickness of the entire semiconductor package 10c can be reduced as compared with the cases of the first to third embodiments (FIGS. 1 to 3). it can. Further, since the chip capacitor 1 is embedded in a region below the semiconductor element mounting region, the chip capacitor 1 is placed around the semiconductor element mounting region as in the second and third embodiments (FIGS. 2 and 3). The size of the semiconductor package 10c can be reduced as compared with the case of surface mounting in the region.

  FIG. 5 schematically shows the configuration of a capacitor-mounted wiring board (semiconductor package) according to a fifth embodiment of the present invention in the form of a sectional view.

  Compared to the semiconductor package 10c according to the fourth embodiment described above (FIG. 4), the semiconductor package 10d according to the present embodiment has an upper side of the core substrate 11 (the semiconductor element 2 is included in the buildup layer constituting the package). The difference is that the chip capacitor 1 is embedded in the build-up layer (resin layer 17a) laminated on the same side as the mounting side. The chip capacitor 1 has one electrode connected to the power supply wiring layer 18a via a conductor (a part of the wiring layer 18a) filled in a via hole formed through the resin layer 17a in the thickness direction. The other electrode is connected to the ground wiring layer 14a through a conductor (a part of the wiring layer 16a) filled in a via hole formed through the resin layer 15a in the thickness direction. . Other configurations and their functions are basically the same as in the case of the fourth embodiment, and a description thereof will be omitted.

  According to the fifth embodiment, as compared with the case of the fourth embodiment, the chip capacitor 1 is embedded and mounted in the vicinity of the semiconductor element 2 to be mounted, and a through hole having a large inductance is not interposed. The electrical characteristics when viewed as a whole of the semiconductor device (semiconductor package 10d in which the semiconductor element 2 is mounted) can be further improved.

  FIG. 6 schematically shows the configuration of a capacitor-mounted wiring board (semiconductor package) according to a sixth embodiment of the present invention in the form of a sectional view.

  In the semiconductor package 10e according to the present embodiment, a ground plane (ground wiring layer 18a) is disposed immediately below the semiconductor element 2 to be mounted, as compared with the semiconductor package 10d according to the fifth embodiment described above (FIG. 5). Is different. Due to the difference in arrangement, the number of via holes existing on the path of the current flowing through the capacitor 1 (length) is smaller than that in the fifth embodiment, and is generated on the path of the current flowing through the capacitor. Therefore, the electrical characteristics of the semiconductor device (semiconductor package 10e in which the semiconductor element 2 is mounted) as a whole are improved. The chip capacitor 1 has a ground wiring layer 18a through a conductor (a part of the wiring layer 18a) having one electrode filled in a via hole formed through the resin layer 17a in the thickness direction. The other electrode is connected to the power supply wiring layer 14a through a conductor (a part of the wiring layer 16a) filled in a via hole formed through the resin layer 15a in the thickness direction. Yes. Other configurations and functions thereof are basically the same as those in the fifth embodiment, and thus description thereof is omitted.

  In the example of FIG. 6, the wiring layer 18a immediately below the semiconductor element 2 to be mounted is used for grounding, but this is the same even when it is used for power supply (power plane). In this case, the wiring layer 14a provided for power supply is changed to ground, and the wiring layer 14a is changed in pattern so as to be connected to the ground external connection terminal 22 (G). The pattern of the layer 18a is changed so as to be connected to the external connection terminal 22 (P) for power supply.

  FIG. 7 schematically shows the configuration of a capacitor-mounted wiring board (semiconductor package) according to a seventh embodiment of the present invention in the form of a sectional view.

  The semiconductor package 10f according to the present embodiment differs from the semiconductor package 10d according to the fifth embodiment described above (FIG. 5) in the connection form of the chip capacitor 1. That is, as shown in a portion CP1 surrounded by a broken line in the package 10f in FIG. 7, the chip capacitor 1 is mounted on the ground wiring layer 14a via the adhesive 30, and one of the electrodes (at least The end portion is locked and connected to a wiring layer 16a (which is connected to the wiring layer 14a) formed in a substantially L shape when viewed in cross section. The other electrode of the chip capacitor 1 is a conductor filled in a part of another wiring layer 16a and a via hole formed through the resin layer 17a in the thickness direction (a part of the wiring layer 18a). Is connected to the power supply wiring layer 18a. Other configurations and functions thereof are basically the same as those in the fifth embodiment, and thus description thereof is omitted.

  According to the seventh embodiment, since it is basically the same as the package structure according to the fifth embodiment, the same effects as in the case of the fifth embodiment can be obtained. Further, based on the above structural features (one electrode of the chip capacitor 1 is locked to the substantially L-shaped wiring layer 16a), the electrical connection between the electrode and the ground plane (wiring layer 14a) is achieved. Connection reliability can be improved.

  FIG. 8 schematically shows a configuration of a capacitor-mounted wiring board (semiconductor package) according to an eighth embodiment of the present invention in the form of a cross-sectional view.

  The semiconductor package 10g according to the present embodiment differs from the semiconductor package 10d according to the fifth embodiment described above (FIG. 5) in the connection form of the chip capacitor 1. That is, as shown in a part CP2 surrounded by a broken line in the package 10g in FIG. 8, the chip capacitor 1 is mounted in the resin layer 15a via the adhesive 30, and one electrode (at least the end part) is mounted. ) Is a wiring layer 16a formed in an L shape when viewed in cross section (this is a conductor filled in a via hole formed through the resin layer 15a in the thickness direction (a part of the wiring layer 16a)). And is connected to the ground wiring layer 14a via the contact). The other electrode of the chip capacitor 1 is a conductor filled in a part of another wiring layer 16a and a via hole formed through the resin layer 17a in the thickness direction (a part of the wiring layer 18a). Is connected to the power supply wiring layer 18a. Other configurations and functions thereof are basically the same as those in the fifth embodiment, and thus description thereof is omitted.

  Also in the eighth embodiment, since it is basically the same as the package structure according to the fifth embodiment, the same effects as in the fifth embodiment can be obtained. Further, based on the above structural features (one electrode of the chip capacitor 1 is locked to the L-shaped wiring layer 16a), as in the case of the seventh embodiment, The reliability of electrical connection with the ground plane (wiring layer 14a) can be increased.

  In the semiconductor packages 10f and 10g (FIGS. 7 and 8) according to the seventh and eighth embodiments, the connection configuration of the chip capacitor 1 is compared with the semiconductor package 10d (FIG. 5) according to the fifth embodiment. Although the case where the portions CP1 and CP2 according to the above are replaced is described as an example, this is applied to the semiconductor package 10c according to the fourth embodiment (FIG. 4) or the semiconductor package 10e according to the sixth embodiment (FIG. 6). Of course, it can be similarly replaced.

  Further, in the semiconductor packages 10f and 10g (FIGS. 7 and 8) according to the seventh and eighth embodiments, the portions other than the portions CP1 and CP2 according to the connection form of the chip capacitor 1 are well known to those skilled in the art. It can be manufactured by the build-up method. Therefore, the description of the parts other than the parts CP1 and CP2 is omitted for the sake of simplification, and only the manufacturing process of the parts CP1 and CP2 will be described below with reference to FIGS.

(Manufacturing process of the part CP1 according to the seventh embodiment: see FIGS. 9 and 10)
First, in the first step (see FIG. 9A), a ground plane (wiring layer 14a) is formed on the core substrate 11. The wiring layer 14a is formed on the entire surface of the core substrate 11 in the illustrated example, but is formed in a required pattern shape as shown in FIG. For example, a thin film of copper (Cu) is formed on the core substrate 11, and a required pattern is formed by the subtractive method using the thin film as a seed.

  In the next step (see FIG. 9B), a resin layer 15a as an interlayer insulating layer is formed on the patterned wiring layer 14a. For example, a thermosetting resin such as an epoxy resin or a polyimide resin is laminated on the wiring layer 14a, planarized and pressed, and then cured to form the resin layer 15a.

  In the next step (see FIG. 9C), a recess (cavity) RP is formed by router processing at a specific position of the resin layer 15a (a position corresponding to a portion where a chip capacitor described later is mounted). Instead of this router processing, the recess RP may be formed by sandblasting, etching or the like.

  In the next step (see FIG. 9D), the thin chip capacitor 1 having a thickness of about 100 μm is mounted on the wiring layer 14a in the recess (cavity) RP formed in the resin layer 15a. In this case, after adhering the adhesive 30 to the wiring layer 14 a, the capacitor 1 may be mounted in accordance with the position of the adhesive 30, or the adhesive 30 may be attached to the capacitor 1. After that, the capacitor 1 with the adhesive 30 may be mounted on the wiring layer 14a. When the chip capacitor 1 is mounted, the chip capacitor 1 is positioned so that the gap on one side (left side in the illustrated example) is relatively large in the recess RP. In the present embodiment, the left gap is selected to be about 100 μm to 200 μm. At this time, the gap on the right side is selected to be about 50 μm to 100 μm.

  In the next step (see FIG. 9E), a seed layer 31 serving as a plating base film for electrolytic plating performed in the subsequent step is formed on the entire surface by electroless Cu plating to a thickness of about 1 μm. Instead of electroless plating, the seed layer 31 may be formed by sputtering.

  In the next step (see FIG. 9F), a plating resist (resist layer) is formed so as to cover the entire surface so that specific portions of the wiring layer 14a, the resin layer 15a, and the chip capacitor 1 covered with the seed layer 31 are exposed. 32). As used herein, the “specific portion” refers to one electrode of the chip capacitor 1 (left electrode in the illustrated example) and the portion corresponding to the position of the wiring layer 14a on the same side, and the other electrode of the chip capacitor 1. This corresponds to the portion corresponding to the position of the right electrode in the illustrated example. The resist layer 32 is formed by, for example, laminating a photosensitive dry film (thickness of about 25 μm) on the entire surface, and performing exposure and development (patterning of the dry film) so as to follow the shape of the above “specific part”. A portion of the dry film corresponding to the region of the specific portion is opened. As a result, the resist layer 32 in which the specific portion is exposed is formed.

  In the next step (see FIG. 10A), electrolytic Cu plating is performed on the seed layer 31 exposed from the resist layer 32 using the seed layer as a power feeding layer to form a wiring layer 16a. As a result, wiring layers 16a are formed on the electrodes on both sides of the chip capacitor 1, and at this point, the wiring layer 16a on one side is connected to the ground plane (wiring layer 14a) via the seed layer 31. It will be.

  In the next step (see FIG. 10B), the dry film 32 is peeled and removed, and the exposed seed layer 31 (Cu) is removed by wet etching.

  In the next process (see FIG. 10C), an interlayer insulating layer is formed on the resin layer 15a, the wiring layers 14a and 16a, and the chip capacitor 1 in the same manner as the process performed in the process of FIG. 9B. The resin layer 17a is formed.

  In the next step (see FIG. 10D), the wiring layer 16a is placed at a specific position of the resin layer 17a (a position corresponding to a portion where the wiring layer 16a on the other electrode of the chip capacitor 1 is formed). Via hole VH1 is formed to reach For example, the via hole VH1 is formed by removing a corresponding portion of the resin layer 17a with a CO2 laser, a UV-YAG laser, or the like.

  In the last process (see FIG. 10E), electrolytic Cu plating is performed on the resin layer 17a including the inside of the via hole VH1 using the wiring layer 16a as a power feeding layer, and a power plane is formed into a required pattern shape by a semi-additive method. (Wiring layer 18a) is formed. As a result, the other electrode of the chip capacitor 1 is connected to the power supply plane (wiring layer 18a) via the wiring layer 16a (including the seed layer), and the portion CP1 relating to the connection form of the chip capacitor 1 is manufactured. Become.

(Manufacturing process of the part CP2 according to the eighth embodiment: see FIGS. 11 and 12)
First, in the first step (see FIG. 11A), a ground plane (wiring layer 14a) is formed on the core substrate 11 in the same manner as the processing performed in the step of FIG. 9A.

  In the next step (see FIG. 11B), a resin layer 15a as an interlayer insulating layer is formed on the patterned wiring layer 14a in the same manner as the processing performed in the step of FIG. 9B.

  In the next step (see FIG. 11C), the via hole is formed so as to reach the wiring layer 14a at a specific position of the resin layer 15a (a position corresponding to a portion where the end of one electrode of the chip capacitor 1 is located). VH2 is formed. For example, the via hole VH2 is formed by removing a corresponding portion of the resin layer 15a with a CO2 laser, a UV-YAG laser, or the like.

  In the next step (see FIG. 11D), the capacitor 1 is mounted so that one electrode of the chip capacitor 1 partially covers the opening region of the via hole VH2 formed in the resin layer 15a. In this case, after adhering the adhesive 30 to the resin layer 15 a, the capacitor 1 may be mounted according to the position of the adhesive 30, or the adhesive 30 may be applied to the capacitor 1. After that, the capacitor 1 with the adhesive 30 may be mounted on the resin layer 15a.

  In the next step (see FIG. 11E), the seed layer 33 is formed to a thickness of about 1 μm on the entire surface by electroless Cu plating in the same manner as the processing performed in the step of FIG.

  In the next step (see FIG. 11 (f)), a plating resist (resist layer) covering the entire surface so that a specific portion of the wiring layer 14a, the resin layer 15a, and the chip capacitor 1 covered with the seed layer 33 is exposed. 34). The “specific part” here is a part corresponding to a position where one electrode of the chip capacitor 1 partially covers the opening region of the via hole VH2, and a part corresponding to the position of the other electrode of the chip capacitor 1. It corresponds to. The formation of the resist layer 34 can be performed in the same manner as the process performed in the step of FIG.

  In the next step (see FIG. 12A), the wiring layer 16a is formed on the seed layer 33 exposed from the resist layer 34 in the same manner as the processing performed in the step of FIG. Thus, the wiring layer 16a is formed on the electrodes on both sides of the chip capacitor 1, and at this time, the wiring layer 16a on one side is connected to the ground plane (wiring layer 14a) via the seed layer 33. become.

  In the next step (see FIG. 12B), the dry film 34 is peeled and removed, and the exposed portion of the seed layer 33 (Cu) is removed by wet etching.

  In the next step (see FIG. 12C), a resin as an interlayer insulating layer is formed on the resin layer 15a, the wiring layer 16a, and the chip capacitor 1 in the same manner as the processing performed in the step of FIG. Layer 17a is formed.

  In the next step (see FIG. 12D), in the same manner as the processing performed in the step of FIG. 10D, a specific position of the resin layer 17a (the wiring layer 16a on the other electrode of the chip capacitor 1 is formed). A via hole VH3 is formed at a position corresponding to the formed portion) so as to reach the wiring layer 16a.

  In the last step (see FIG. 12E), electrolytic Cu plating is performed on the resin layer 17a including the inside of the via hole VH3 using the wiring layer 16a as a power feeding layer, and a power plane is formed into a required pattern shape by a semi-additive method. (Wiring layer 18a) is formed. As a result, the other electrode of the chip capacitor 1 is connected to the power supply plane (wiring layer 18a) via the wiring layer 16a (including the seed layer), and the portion CP2 according to the connection form of the chip capacitor 1 is manufactured. Become.

  FIG. 13 shows a comparison of the data (ESL of the capacitor) obtained when evaluating the package structure when the chip capacitor is mounted on the surface and when embedded. In the illustrated example, two types of chip capacitors A and B (3 for A and 2 for B) do not take into account the connection with the mounted semiconductor elements, but what happens if they are simply surface-mounted, and what happens if they are embedded and mounted. It shows the data when evaluating. In the case of embedded mounting, the chip capacitor is embedded in the insulating layer so as to be positioned on the ground line, and when a current is passed through the capacitor, the direction of the current and the direction of the current flowing through the ground line are reversed. In this way, evaluation is performed. Chip capacitors A and B have different capacities and are 10 nF and 5 nF, respectively. In addition, both sizes are vertical (1.0 mm) × horizontal (0.5 mm) × height (0.1 mm). Regarding the chip capacitor A, the ESL (pH) when surface-mounted is 209.0, the difference between the maximum value and the average value is 39.0, and the difference between the minimum value and the average value is 46.0. When mounted, the ESL (pH) had an average value of 84.0, a difference between the maximum value and the average value of 12.3, and a difference between the minimum value and the average value of 10.5. For the chip capacitor B, the ESL (pH) when mounted on the surface has an average value of 189.5, a difference between the maximum value and the average value of 18.5, and a difference between the minimum value and the average value of 18.5, As for ESL (pH) when embedded, the average value was 128.5, the difference between the maximum value and the average value was 4.5, and the difference between the minimum value and the average value was 4.5. Based on the knowledge obtained here, what has been devised what package structure can be realized when applied to an actual product is the structure of each of the above-described embodiments (FIGS. 1 to 8).

  In each of the above-described embodiments (FIGS. 1 to 8), the case where a chip capacitor as an electronic component is surface-mounted or embedded and mounted on the package has been described as an example, but as will be apparent from the gist of the present invention. A structure corresponding to a capacitor may be built in or on the surface of the package. A configuration example in that case is shown in FIG.

  In the configuration example shown in FIG. 14, in the semiconductor package 10 e (FIG. 6) according to the sixth embodiment, instead of the chip capacitor 1, a structure (capacitor portion) corresponding to a capacitor is built in the package. Is shown. In the configuration shown in the figure, the capacitor portion is formed between the upper and lower electrodes, the wiring layer 16a constituting one electrode (lower electrode), the wiring layer 16a constituting the other electrode (upper electrode), and the upper and lower electrodes. The lower electrode is connected to the power supply plane (wiring layer 14a), and the upper electrode is connected to the ground plane (wiring layer 18a). Various methods known in the art can be used as a method for forming the capacitor in the wiring board (package). For example, as described in JP-A-6-252528, for example, a film of tantalum, aluminum, or the like is formed on an electrode that is a part of a wiring layer by sputtering or vapor deposition, and this film is then used as an anode. There is known a method of oxidizing to form a dielectric film of a capacitor.

  In each of the above-described embodiments, the case where one capacitor is surface-mounted or embedded-mounted in one package has been described as an example. However, depending on the function required for a semiconductor element or the like mounted on the package. Thus, two or more capacitors may be appropriately mounted on the surface or embedded. Alternatively, capacitor surface mounting and embedded mounting may be used in combination as required.

  Further, in each of the embodiments shown in FIGS. 1 to 3, the case where the capacitor is surface-mounted on the same surface as the side on which the semiconductor element or the like of the package is mounted or the opposite surface is described as an example. Depending on the case, surface mounting may be performed on both sides of the package.

  Further, in each of the above-described embodiments, the case where the solder bumps 22 are joined as external connection terminals for mounting the package on a motherboard or the like has been described as an example. However, the form of the external connection terminals is not limited to this. For example, it may be in the form of a pin as used in PGA or the like.

1 ... capacitor (chip capacitor),
2 ... Semiconductor element (chip),
10, 10a, 10b, 10c, 10d, 10e, 10f, 10g ... capacitor mounting wiring board (semiconductor package),
11 ... Insulating substrate (core substrate),
14a, 14b, 16a, 16b, 18a, 18b, 20a, 20b ... wiring layer,
15a, 15b, 17a, 17b, 19a, 19b ... interlayer insulating layer (resin layer),
21a, 21b ... protective film (solder resist layer),
22: External connection terminals (solder bumps),
23 ... solder,
RP ... recess (cavity),
VH1, VH2, VH3 ... via holes.

Claims (1)

A plurality of wiring layers each patterned in a desired shape are stacked via an insulating layer and connected to each other via a conductor formed through the insulating layer in the thickness direction,
A capacitor is provided on at least one of the same surface as the side on which a semiconductor element or electronic component is mounted and the opposite surface, and is used as a power supply line or a ground line among the plurality of wiring layers. And when the current is passed through the capacitor, the direction of the current is opposite to the direction of the current flowing through the wiring layer, and the capacitor A capacitor-mounted wiring board that is surface-mounted so that a path of a current flowing through the wiring layer is substantially parallel to a path of a current flowing through the wiring layer.

Images