JP2004111415A - Circuit board, its manufacturing method, semiconductor device, and its manufacturing method - Google Patents

Circuit board, its manufacturing method, semiconductor device, and its manufacturing method Download PDF

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Publication number
JP2004111415A
JP2004111415A JP2002267846A JP2002267846A JP2004111415A JP 2004111415 A JP2004111415 A JP 2004111415A JP 2002267846 A JP2002267846 A JP 2002267846A JP 2002267846 A JP2002267846 A JP 2002267846A JP 2004111415 A JP2004111415 A JP 2004111415A
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substrate
semiconductor
wiring
insulating substrate
circuit board
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JP4380130B2 (en
Inventor
Naoto Sasaki
佐々木　直人
Yuji Takaoka
高岡　裕二
Hiroyuki Fukazawa
深澤　博之
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board that can suppress component cost to a low level while securing the number of inter-chip wiring by reducing the size of a semiconductor substrate used for connecting the semiconductor chips to each other, and to provide a method of manufacturing the circuit board, a semiconductor device, and a method of manufacturing the semiconductor device. <P>SOLUTION: The circuit board 1 is provided with inter-chip wiring 15 used for connecting a plurality of semiconductor chips 2 and 3 to each other and external wiring 13 used for connecting the chips 2 and 3 to external circuits. The board 1 is composed of an insulating substrate 5 provided with the external wiring 13 on its first surface 5a side and a semiconductor substrate 7 which is embedded in the central part of one main surface of the insulating substrate 5 and provided with the inter-chip wiring 15 on its surface exposed on the first surface 5a side of the substrate 5. The first surface 5a of the insulating substrate 5 and the surface of the semiconductor substrate 7 on which the inter-chip wiring 15 is formed are arranged in the same plane. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置及びその製造方法に関し、特には複数の半導体チップが一つの電子部品として組み立てられている、いわゆるマルチチップモジュール技術を適用した半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
電気製品の小型、軽量、低消費電力化といった要求に応えるため、半導体素子の高集積化技術と共に、これらの半導体素子を高密度に組み付ける実装技術も展開してきている。そのような実装技術のうち、さらなる高密度実装を実現するため、多層配線支持基板やベアチップ実装等に加え、複数の半導体素子（半導体チップ）を予め一つの電子部品として同一の支持基板に搭載して実装するマルチチップモジュール（Ｍｕｌｔｉ−Ｃｈｉｐ　Ｍｏｄｕｌｅ；以下ＭＣＭと記す）技術が開発されている。このＭＣＭ技術は、１つの基板上に２つ以上の半導体チップを組み込むことで、実質的な多機能化を実現している。
【０００３】
このようなＭＣＭ技術を用いた半導体装置としては、例えば日経マイクロデバイス（２００１−３−１）日経ＢＰ社ｐ．１１３−１３２に記載されているように、ＣＯＣ（ｃｈｉｐ　ｏｎ　ｃｈｉｐ）型、チップ・スタック型、パッケージ積層型、基板接続型等の様々な形態が提案、実用化されている。
【０００４】
このうち、基板接続型の半導体装置は、配線が形成された回路基板上に複数の半導体チップを搭載してなり、各半導体チップ間の接続および半導体チップと外部回路との接続は、回路基板上に形成された配線によって行われる。回路基板としては、樹脂基板やセラミック基板が用いられてきたが、近年、これらの基板に換えて半導体基板からなる回路基板（いわゆるシリコンインターポーザ）が用いられるようになってきている。
【０００５】
回路基板として半導体基板を用いた場合、半導体プロセスを適用した微細配線の形成により、半導体チップ間を接続する配線（チップ間配線）数の増加が可能である。
【０００６】
【発明が解決しようとする課題】
ところが、上述した基板接続型の半導体装置において用いられる回路基板は、搭載される半導体チップの総面積と同等か、それ以上の面積を備える必要がある。したがって、半導体基板を回路基板に用いた場合には、樹脂基板やセラミック基板を回路基板として用いた場合と比較して、部品コストが高くなると言った問題があった。
【０００７】
そこで本発明は、半導体チップの接続用に用いる半導体基板を縮小することで、チップ間配線数を確保しつつも、より部品コストを低く抑えることが可能な回路基板およびその製造方法並びに半導体装置およびその製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
このような目的を達成するための本発明の回路基板は、複数の半導体チップを搭載するためのものであり、半導体チップを外部回路に接続するための外部引出配線を一主面側に設けてなる絶縁性基板と、絶縁性基板における一主面側の中央部に埋め込まれた半導体基板とを備えている。そして、半導体基板における、絶縁性基板の一主面側に露出している面側に、半導体チップ間を接続するためのチップ間配線を設けた構成としている。
【０００９】
上述した構成の回路基板では、半導体チップ間を接続するためチップ間配線が半導体基板に設けられた構成となっているため、半導体プロセスを適用して微細に形成したチップ間配線を備えることができる。また、半導体チップと外部回路とを接続するための外部引出配線を絶縁性基板に設けた構成とすることで、半導体基板の大きさは、特に微細化が要求されるチップ間配線のみを形成するための必要最小限の大きさとすることができる。したがって、半導体基板にチップ間配線および外部引出配線の全てを形成してなる回路基板と比較して、半導体基板の使用面積が削減される。
【００１０】
また本発明は、このような回路基板を用いた半導体装置でもあり、複数の半導体チップの端子形成面側に、チップ間配線の形成面側を対向させて上述した半導体基板が配置される。そして、このように配置された状態において、半導体基板に形成されたチップ間配線によって複数の半導体チップが接続されると共に、これらの半導体チップの端子形成面に設けられた外部回路接続用端子が、半導体基板から露出していることとする。
【００１１】
上述した構成の半導体装置においては、複数の半導体チップの外部回路接続用端子が、これらの半導体チップに対向して配置された半導体基板から露出させており、半導体チップ間のみが半導体基板に形成されたチップ間配線によって接続されることになる。したがって、半導体基板は、チップ間配線のみが形成される必要最小限の大きさで有れば良く、半導体基板上に複数の半導体チップを全面で搭載する場合と比較して、半導体基板の使用面積が削減される。
【００１２】
また本発明は、上述した回路基板を製造する方法でもある。このうち、第１の方法は、次のように行う。先ず、絶縁性基板の中央に形成された貫通孔を塞ぐ状態で、当該絶縁性基板に支持基板を貼り合わせる。次いで、チップ間配線が形成された半導体基板を、チップ間配線の形成面を支持基板に対向させた状態で貫通孔内に挿入して当該支持基板に貼り合わせる。その後、半導体基板が挿入された貫通孔内を絶縁物で埋め込むことで絶縁性基板の一主面側に半導体基板を埋め込んだ状態とした後、当該絶縁性基板および半導体基板から前記支持基板を剥離する。また、絶縁性基板に支持基板を貼り合わせる前、または絶縁性基板から支持基板を剥離した後には、絶縁性基板の一主面側に外部引出配線を形成する工程を行う。
【００１３】
また、第２の方法は、次のように行う。先ず、チップ間配線が形成された半導体基板を、チップ間配線の形成面を支持基板に対向させた状態で当該支持基板に貼り合わせる。次いで、半導体基板を埋め込む状態で支持基板上に絶縁物を被着してこれを絶縁性基板とした後、当該絶縁性基板および半導体基板から支持基板を剥離する。次に、絶縁性基板における半導体基板が埋め込まれている側の面に外部引出配線を形成する。
【００１４】
また、本発明の半導体装置の製造方法は、上述した第１の方法または第２の方法で回路基板を形成した後、半導体基板のチップ間配線を介して複数の半導体チップを接続させると共に、これらの半導体チップの外部回路接続用端子を絶縁性基板の外部引出配線に接続させる状態で、これらの半導体チップを当該絶縁性基板および半導体基板上に搭載する工程を行う。
【００１５】
以上のような第１の方法または第２の方法およびこれに続けて行われる工程によって、上述した構成の回路基板および半導体装置を得ることができる。
【００１６】
【発明の実施の形態】
以下、本発明の回路基板およびその製造方法、並びに半導体装置およびその製造方法の実施の形態を図面に基づいて詳細に説明する。
【００１７】
＜第１実施形態＞
図１は本発明を適用した回路基板の第１実施形態を示す断面図であり、図２は図１に示す回路基板を用いた半導体装置の断面図である。以下、図１および図２を用いて、第１実施形態の回路基板とこれを用いた半導体装置を、この順に説明する。尚、回路基板の説明においては、図１に基づき図２を参照しつつ説明を行い、図２にのみ示されている部材には符号にカッコを付すこととする。
【００１８】
これらの図に示す回路基板１は、複数の半導体チップ（２），（３）を搭載してなる、いわゆるＭＣＭ型の半導体装置（４）を構成するものである。この回路基板１は、絶縁性基板５、絶縁性基板５の一主面（第１面５ａ）側に埋め込まれた半導体基板７、絶縁性基板５と半導体基板７との間に充填され、絶縁性基板７と一体化して絶縁性基板７の一部を構成する絶縁物９で構成されている。
【００１９】
このうち、絶縁性基板５は、セラミックや樹脂で構成され、その中央部に半導体基板７が嵌入される貫通孔１１が設けられている。そして、半導体基板７が埋め込まれている側の第１面５ａには、半導体チップ（２），（３）と外部回路とを接続するための外部引出配線１３が形成されている。尚、ここでの図示は省略したが、この外部引出配線１３は、絶縁性基板５を貫通して設けられたビアホール内を介して、絶縁性基板５の第１面５ａ側から第２面５ｂ側に引き出されても良い。
【００２０】
そして、半導体基板７は、絶縁性基板５の第１面５ａ側に、一方の面を露出させた状態で埋め込まれている。特に、埋め込まれた状態において、絶縁性基板５の第１面５ａ側に露出している半導体基板７の露出面７ａが、絶縁性基板５の第１面５ａと同一面（同一高さ）に配置されることが好ましい。また、この露出面７ａには、半導体チップ（２），（３）間を接続するための配線や電極パッド等として、いわゆるチップ間配線１５が設けられていることとする。
【００２１】
ここで、半導体基板７は、上述したチップ間配線１５が露出面７ａに設けられるだめの必要最小限の大きさで構成されることが好ましい。
【００２２】
次に、図２に基づいて、上述した構成の回路基板１を用いた半導体装置４の構成を説明する。
【００２３】
この図に示す半導体装置４は、回路基板１上に複数の半導体チップ２，３を搭載してなるＭＣＭ型の半導体装置であり、例えばロジック用の半導体チップやメモリ用の半導体チップ等、異なる機能の半導体チップ２，３が１つの回路基板１上に組み合わせて搭載され、システムインパッケージを構成している。
【００２４】
ここで、各半導体チップ２，３には、それぞれの機能を備えた機能回路と共に、この内部回路から引き出された端子が形成されている。例えば、半導体チップ２には、もう一方の半導体チップ３との接続を図るための内部回路用端子２０ａと、外部回路との接続を図るための外部回路接続用端子２０ｂとが、端子形成面２ａ側に露出した状態で設けられている。同様に、半導体チップ３には、もう一方の半導体チップ２との接続を図るための内部回路用端子３０ａと、外部回路との接続を図るための外部回路接続用端子３０ｂとが、端子形成面３ａ側に露出した状態で設けられている。
【００２５】
そして、このような半導体チップ２，３は、突起電極４１を介して半導体チップ２，３の各端子２０ａ，２０ｂ，３０ａ，３０ｂと、回路基板１の配線１３，１５とを接続させた状態で回路基板１上に搭載されている。具体的には、半導体チップ２，３は、回路基板１を構成する半導体基板７のチップ間配線１５に内部回路用端子２０ａ，３０ａを接続させると共に、回路基板１を構成する絶縁性基板５の外部引出配線１３に外部回路接続用端子２０ｂ，３０ｂを接続させる状態で、回路基板１上に搭載されていることとする。
【００２６】
尚、ここでの図示は省略したが、回路基板１と半導体チップ２，３との間には、接続強度を補うためのアンダーフィルが充填されていても良い。
【００２７】
また、このように構成された半導体装置４を、ここでの図示を省略した外部回路に接続するには、回路基板１を構成する絶縁性基板５に形成された外部引出電極１３に対してワイヤーボンディング（図示省略）を行うこととする。ただし、この外部引出配線１３が、絶縁性基板５の第１面５ａ側から第２面５ｂ側に引き出されている場合、第２面５ｂ側に引き出された外部引出配線部分に突起電極を形成することで、外部回路に対して半導体装置４をフリップチップ接続させることとする。
【００２８】
次に、上述した構成の回路基板１および半導体装置４の製造方法を、図３に基づいて説明する。
【００２９】
先ず、図３（ａ）に示すように、中央部に貫通孔１１を備えると共に一主面（第１面５ａ側に外部引出配線１３が形成された絶縁性基板５を作製する。この絶縁性基板５は、例えば通常のセラミック回路基板や樹脂回路基板の中央部に貫通孔５を形成した構成であって、外部引出配線１３は例えばプリント配線やメッキ法によって形成される。また、絶縁性基板５に対する貫通孔１１の形成と外部引出配線１３の形成とは、どちらを先に行っても良い。
【００３０】
次に、図３（ｂ）に示すように、貫通孔１１を塞ぐように、絶縁性基板５の第１面５ａ側に支持基板１０１を貼り合わせる。この際、例えば、接着剤１０２を介して絶縁性基板５と支持基板１０１とを貼り合わせることとする。ここで、支持基板１０１は、貫通孔１１を塞ぐ大きさよりも一回り大きな貼り合わせ面を有していれば良く、図示したように絶縁性基板５よりも大きく形成されている必要はない。また、接着剤１０２は、紫外線のような光照射によって粘着力が低下する材料や、絶縁性基板５に対して選択的に薬液除去可能な材料で構成されることとする。特に、光照射によって粘着力が低下する材料で接着剤１０２が構成されている場合、支持基板１０１には石英やガラス等の光透過性材料を用いることが好ましい。また、この接着剤１０２は、例えば図示したように、支持基板１０１の貼り合わせ面側の全面にあらかじめ設けられていても良く、また絶縁性基板５の第１面５ａ側に設けられていても良い。
【００３１】
以上の後、図３（ｃ）に示すように、一主面側にチップ間配線１５が形成された半導体基板７を用意する。このチップ間配線１５は、半導体プロセスによって形成された微細な配線であることとする。
【００３２】
そして、この半導体基板７のチップ間配線１５が設けられた面を支持基板１０１の接着剤１０２が設けられた面に対向させた状態で、この半導体基板７を絶縁性基板５の貫通孔１１内に挿入し、接着剤１０２を介して支持基板１０１に貼り合わせる。尚、接着剤１０２が、あらかじめ支持基板１０１の貼り合わせ面側の全面に設けられていない場合には、半導体基板７のチップ間配線１５が設けられた面側に接着剤１０２を設けておくこととする。
【００３３】
次に、図３（ｄ）に示すように、半導体基板７が挿入された貫通孔１１内を樹脂材料などからなる絶縁物９で埋め込み、硬化させる。これにより、絶縁物９と一体化させた絶縁性基板５の第１面５ａ側に半導体基板７を埋め込んだ状態とする。
【００３４】
その後、図３（ｅ）に示すように、絶縁性基板５および半導体基板７から支持基板１０１を剥離する。この際、接着剤１０２が、光照射によって粘着力が低下する材料からなる場合、支持基板１０１側からの光照射によって接着剤１０２の接着力を低下させ、支持基板１０１と共に接着剤１０２を絶縁性基板５および半導体基板７から剥離する。一方、接着剤１０２が、絶縁性基板５に対して選択的に薬液除去可能な材料からなる場合には、選択された薬液を用いたウェット処理によって、支持基板１０１と共に接着剤１０２を絶縁性基板５および半導体基板７から剥離する。この際、同時に支持基板１０１をエッチング除去しても良い。
【００３５】
以上により、図１を用いて説明した第１実施形態の回路基板１が得られる。尚、図３（ｅ）と図１とは、上下方向が逆であることとする。
【００３６】
そして、回路基板１を用いた半導体装置を得るためには、図２に示したように、先ず、半導体チップ２，３の内部回路用端子２０ａ，３０ａや外部回路接続用端子２０ｂ，３０ｂ、および回路基板１の外部取出取配線１３やチップ間配線１５の少なくとも一方に突起電極４０を形成する。そして、これらの突起電極４１を介して、半導体基板７のチップ間配線１５に半導体チップ２，３の内部回路用端子２０ａ，３０ａを接続させ、絶縁性基板５の外部取出配線１３に半導体チップの外部回路接続用端子２０ｂ，３０ｂを接続させるように、回路基板１上に半導体チップ２，３を搭載する。
【００３７】
以上により、図２を用いて説明した第１実施形態の半導体装置４を完成させる。
【００３８】
以上説明した第１実施形態の回路基板１および半導体装置４では、半導体チップ２，３間を接続するためチップ間配線１５を半導体基板７に設けた構成となっているため、半導体プロセスを適用して微細に形成したチップ間配線１５が用いられる。したがって、大容量のチップ間配線１５によって複数の半導体チップ２，３を接続することが可能になる。しかも、半導体チップ２，３と外部回路とを接続するための外部引出配線１３を絶縁性基板５に設けた構成とすることで、上述した半導体基板７は、特に微細化が要求されるチップ間配線１５のみが形成される必要最小限の大きさで有れば良い。したがって、半導体基板にチップ間配線および外部引出配線の全てを形成してなる回路基板（例えばシリコンインターポーザ）と比較して、半導体基板７の使用面積を削減することができる。
【００３９】
この結果、微細な配線によって半導体チップ２，３間を接続可能であるといった高機能性を維持しながらも、回路基板１および半導体装置４の部品コストの低下を図ることが可能になる。
【００４０】
尚、上述した第１実施形態の製造方法では、図３（ｂ）を用いて説明したように、外部引出配線１３が形成された絶縁性基板５を支持基板１０１に貼り合わせる手順としたが、外部引出配線１３の形成は、図３（ｅ）を用いて説明したように、絶縁性基板５から支持基板１０１を剥離した後に行っても良い。
【００４１】
また、外部引出配線は、先に説明したように、絶縁性基板５の第１面５ａ側から第２面５ｂ側に引き出されたものであっても良い。この場合、例えば、レーザ光により絶縁性基板５にヴィアホールを形成し、この内部にめっき法によって導電性材料（銅）を埋め込むことで、第１面５ａ側から第２面５ｂに引き出された外部引出配線を形成する。このような外部引出配線を形成した場合には、第１面５ａ側のみに外部引出配線１３を形成した場合よりも、回路基板１および半導体装置４の小型化を図ることができる。
【００４２】
＜第２実施形態＞
図４は本発明を適用した回路基板の第２実施形態を示す断面図であり、図５は図４に示す回路基板を用いた半導体装置の断面図である。以下、図４および図５を用いて、第２実施形態の回路基板とこれを用いた半導体装置を、この順に説明する。尚、回路基板の説明においては、図４に基づき図５を参照しつつ説明を行い、図５にのみ示されている部材には符号にカッコを付すこととする。また、第１実施形態と同様の構成要素には同一の符号を付し、重複する説明は省略する。
【００４３】
これらの図に示す第２実施形態の回路基板１’と、第１実施形態で図１および図２を用いて説明した回路基板との異なるところは、絶縁性基板５’の構成にあり、他の構成は第１実施形態と同様であることとする。
【００４４】
すなわち、絶縁性基板５’は、その一主面（第１面５ａ’）側に半導体基板７を埋め込む状態に形成された一体物であり、例えば樹脂からなる。そして、半導体基板７が埋め込まれている側の第１面５ａ’には、半導体チップ（２），（３）と外部回路とを接続するための外部引出配線１３’が形成されている。この外部引出配線１３’は、絶縁性基板５’を貫通するビアホール内に充填された状態で、絶縁性基板５’の第１面５ａ’側から第２面５ｂ’側に引き出されていることとする。尚、ここでの図示は省略したが、この外部引出配線１３’は、絶縁性基板５’の第１面５ａ’側のみに配置されていても良い。この場合、外部引出配線１３’の一端部は、絶縁性基板５’の周縁側に引き出されていることとする。
【００４５】
そして、このような構成の絶縁性基板５’の第１面５ａ’側に、第１実施形態で説明したと同様の半導体基板７が露出面７ａを露出させた状態で埋め込まれていることとする。
【００４６】
次に、図５に基づいて、上述した構成の回路基板１’を用いた半導体装置４’の構成を説明する。
【００４７】
この図に示す第２実施形態の半導体装置４’と、第１実施形態で図２を用いて説明した半導体装置との異なるところは、上述したような回路基板１’を用いた点にあり、他の構成は第１実施形態と同様であることとする。
【００４８】
すなわち、この半導体装置４’は、回路基板１’上に複数の半導体チップ２，３を搭載してなるＭＣＭ型の半導体装置である。そして、半導体チップ２，３は、突起電極４１を介して、半導体チップ２，３の各端子２０ａ，２０ｂ，３０ａ，３０ｂと、回路基板１’の配線１３’，１５とを接続させた状態で回路基板１’上に搭載されている。具体的には、半導体チップ２，３は、回路基板１’を構成する半導体基板７のチップ間配線１５に内部回路用端子２０ａ，３０ａを接続させると共に、回路基板１’を構成する絶縁性基板５’の外部引出配線１３’に外部回路接続用端子２０ｂ，３０ｂを接続させる状態で、回路基板１’上に搭載されているのである。
【００４９】
尚、ここでの図示は省略したが、回路基板１’と半導体チップ２，３との間には、接続強度を補うためにアンダーフィルが充填された構成であっても良い。
【００５０】
また、このように構成された半導体装置４’を、ここでの図示を省略した外部回路に接続させるには、回路基板１’の第２面５ｂ’側に引き出された外部引出配線１３’部分に突起電極を形成することで、外部回路に対して半導体装置４’をフリップチップ接続させることとする。ただし、この外部引出配線１３’が、絶縁性基板５’の第１面５ａ’側のみに配置されていている場合、半導体チップ２，３よりも絶縁性基板５’の周縁側に引き出されている外部引出配線部分に対してワイヤーボンディングを行うこととする。
【００５１】
次に、上述した構成の回路基板１’および半導体装置４’の製造方法を、図６に基づいて説明する。
【００５２】
先ず、図６（ａ）に示すように、第１実施形態と同様の半導体基板７を用意する。そして、半導体基板７のチップ間配線１５が形成された面を支持基板１０１側に対向させた状態で、接着剤１０２を介して半導体基板７と支持基板１０１とを貼り合わせる。この際、支持基板１０１の中央に半導体基板７を貼り合わせることとする。また支持基板１０１および接着剤１０２は、第１実施形態と同様のものが用いられる。ただし、支持基板１０１は、その貼り合わせ面が、ここで形成する回路基板の配線が形成される面と同様の形状であることとする。また、接着剤１０２は、支持基板１０１側の全面に設けられていることとする。
【００５３】
次いで、図６（ｂ）に示すように、支持基板１０２上に、例えばスピンコート法のような塗布法によって、半導体基板７を埋め込む状態で表面平坦に樹脂などからなる絶縁物を被着させ、次いでこれを硬化させて絶縁性基板５’とする。またこれにより、絶縁性基板５’の第１面５ａ’側に半導体基板７を埋め込んだ状態とする。
【００５４】
その後、図６（ｃ）に示すように、絶縁性基板５’および半導体基板７から支持基板１０２を剥離する。この工程は、第１実施形態において図３（ｅ）を用いて説明したと同様に行うこととする。尚、以上の図６（ａ）〜図６（ｃ）の工程には、特開２００１−３０８１１６に開示されている疑似ウェハの製造方法を適用することができる。
【００５５】
次に、図６（ｄ）に示すように、絶縁性基板５’における半導体基板７が埋め込まれている側の面に外部引出配線１３’を形成する。この際、例えば、レーザ光により絶縁性基板５’にヴィアホールを形成し、この内部にめっき法によって導電性材料（銅）を埋め込むことで、第１面５ａ’側から第２面５ｂ’に引き出された外部引出配線１３’を形成する。また、絶縁性基板５’の第１面５’側のみに、通常のプリント配線やメッキ法によって外部引出配線を形成しても良い。
【００５６】
以上により、図４を用いて説明した第２実施形態の回路基板１’が得られる。尚、図６（ｄ）と図４とは、上下方向が逆であることとする。
【００５７】
また、このような回路基板１’を用いた半導体装置を得るためには、図５に示したように、先ず、半導体チップ２，３の内部回路用端子２０ａ，３０ａや外部回路接続用端子２０ｂ，３０ｂ、および回路基板１の外部取出取配線１３’やチップ間配線１５の少なくとも一方に接続させた突起電極４１を形成する。そして、これらの突起電極４１を介して、半導体基板７のチップ間配線１５に半導体チップ２，３の内部回路用端子２０ａ，３０ａを接続させ、絶縁性基板５の外部取出配線１３’に半導体チップの外部回路接続用端子２０ｂ，３０ｂを接続させるように、回路基板１’上に半導体チップ２，３を搭載する。
【００５８】
以上により図５を用いて説明した第２実施形態の半導体装置４’を完成させる。
【００５９】
以上説明した構成の回路基板１’および半導体装置４’であっても、第１実施形態と同様に、半導体チップ２，３間を接続するためチップ間配線１５を半導体基板７に設けた構成となっているため、微細な配線によって半導体チップ２，３間を接続可能であるといった高機能化を維持しながらも、回路基板１’および半導体装置４’の部品コストの低下を図ることが可能になる。尚、回路基板１’における外部引出配線１３’を、図示したような第１面５ａ’側から第２面５ｂ’に引き出された構成とすることで、第１面側のみに外部引出配線を形成した場合よりも、回路基板および半導体装置の小型化を図ることができる。
【００６０】
【発明の効果】
以上説明したように本発明の回路基板および半導体装置によれば、半導体チップ間を接続するためのチップ間配線を設けた半導体基板を、絶縁性基板の外部引出配線の形成面側に埋め込んだ回路基板の構成を採用したことで、半導体プロセスを適用した微細配線によって半導体チップ間を接続可能であるといった高機能化を維持しながらも、半導体基板を必要最小限の大きさに抑えることで、回路基板および半導体装置の部品コストの低下を図ることが可能である。
また、本発明の回路基板の製造方法によれば上述した構成の回路基板を得ることが可能であり、同様に本発明の半導体装置の製造方法によればこのような回路基板を用いた半導体装置を得ることが可能である。
【図面の簡単な説明】
【図１】第１実施形態の回路基板の断面構成図である。
【図２】第１実施形態の半導体装置の断面構成図である。
【図３】第１実施形態の回路基板の製造手順を示す断面工程図である。
【図４】第２実施形態の回路基板の断面構成図である。
【図５】第２実施形態の半導体装置の断面構成図である。
【図６】第２実施形態の回路基板の製造手順を示す断面工程図である。
【符号の説明】
１，１’…回路基板、２，３…半導体チップ、２ａ，３ａ…端子形成面（半導体チップ）、４，４’…半導体装置、５，５’…絶縁性基板、５ａ，５ａ’…第１面（絶縁性基板の一主面）、７…半導体基板、９…絶縁物、１１…貫通孔、１３，１３’…外部引出配線、１５…チップ間配線、２０ｂ，３０ｂ…外部回路接続用端子（半導体チップ）、１０１，１０２…支持基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device to which a plurality of semiconductor chips are assembled as one electronic component, which employs a so-called multichip module technology, and a method of manufacturing the same.
[0002]
[Prior art]
In order to meet demands for smaller, lighter, and lower power consumption electric appliances, mounting technologies for assembling these semiconductor elements with high density have been developed along with high integration techniques for semiconductor elements. Among such mounting technologies, in order to realize even higher density mounting, in addition to a multilayer wiring support substrate, bare chip mounting, etc., a plurality of semiconductor elements (semiconductor chips) are mounted in advance as one electronic component on the same support substrate. A multi-chip module (hereinafter, referred to as MCM) technology for mounting on a chip has been developed. This MCM technology realizes substantial multifunctionality by incorporating two or more semiconductor chips on one substrate.
[0003]
As a semiconductor device using such MCM technology, for example, Nikkei Micro Device (2001-3-1) Nikkei BP, p. As described in 113-132, various forms such as a COC (chip on chip) type, a chip stack type, a package stack type, and a substrate connection type have been proposed and put into practical use.
[0004]
Of these, a board-connected semiconductor device has a plurality of semiconductor chips mounted on a circuit board on which wiring is formed, and the connection between each semiconductor chip and the connection between the semiconductor chip and an external circuit are performed on the circuit board. Is performed by the wiring formed on the substrate. As the circuit board, a resin substrate or a ceramic substrate has been used. In recent years, a circuit board (a so-called silicon interposer) made of a semiconductor substrate has been used instead of these substrates.
[0005]
When a semiconductor substrate is used as a circuit substrate, the number of wirings (wirings between chips) connecting between semiconductor chips can be increased by forming fine wirings using a semiconductor process.
[0006]
[Problems to be solved by the invention]
However, the circuit board used in the above-described substrate connection type semiconductor device needs to have an area equal to or larger than the total area of the mounted semiconductor chips. Therefore, when the semiconductor substrate is used as the circuit board, there is a problem that the component cost is higher than when the resin substrate or the ceramic substrate is used as the circuit board.
[0007]
Accordingly, the present invention provides a circuit board, a method of manufacturing the same, a semiconductor device, and a semiconductor device, which can reduce the cost of parts while securing the number of wires between chips by reducing the size of the semiconductor substrate used for connecting the semiconductor chips. It is an object of the present invention to provide a manufacturing method thereof.
[0008]
[Means for Solving the Problems]
The circuit board of the present invention for achieving such an object is for mounting a plurality of semiconductor chips, and is provided with an external lead-out wiring for connecting the semiconductor chip to an external circuit on one main surface side. And a semiconductor substrate buried in a central portion of one side of the insulating substrate. The semiconductor substrate has a configuration in which inter-chip wiring for connecting between semiconductor chips is provided on a surface of the insulating substrate that is exposed on one main surface side.
[0009]
The circuit board having the above-described configuration has a configuration in which the inter-chip wiring is provided on the semiconductor substrate for connecting the semiconductor chips. Therefore, it is possible to provide a finely formed inter-chip wiring by applying a semiconductor process. . In addition, by employing a configuration in which external lead-out wiring for connecting a semiconductor chip to an external circuit is provided on an insulating substrate, the size of the semiconductor substrate is limited to forming only inter-chip wiring particularly required to be miniaturized. Required minimum size. Therefore, the use area of the semiconductor substrate is reduced as compared with a circuit board in which all of the inter-chip wiring and the external lead wiring are formed on the semiconductor substrate.
[0010]
The present invention is also a semiconductor device using such a circuit board, wherein the above-described semiconductor substrate is arranged on the terminal forming surface side of a plurality of semiconductor chips with the inter-chip wiring forming surface side facing. In this arrangement, a plurality of semiconductor chips are connected by inter-chip wiring formed on the semiconductor substrate, and external circuit connection terminals provided on the terminal formation surfaces of these semiconductor chips are It is assumed that it is exposed from the semiconductor substrate.
[0011]
In the semiconductor device having the above-described configuration, the external circuit connection terminals of the plurality of semiconductor chips are exposed from the semiconductor substrate disposed to face the semiconductor chips, and only the semiconductor chips are formed on the semiconductor substrate. It is connected by the inter-chip wiring. Therefore, the semiconductor substrate only needs to have a minimum necessary size in which only the wiring between the chips is formed, and the use area of the semiconductor substrate is smaller than when a plurality of semiconductor chips are mounted on the entire surface of the semiconductor substrate. Is reduced.
[0012]
The present invention is also a method for manufacturing the above-described circuit board. Among them, the first method is performed as follows. First, a support substrate is attached to the insulating substrate in a state where the through hole formed in the center of the insulating substrate is closed. Next, the semiconductor substrate on which the inter-chip wiring is formed is inserted into the through hole with the surface on which the inter-chip wiring is formed facing the support substrate, and is bonded to the support substrate. Thereafter, the through hole into which the semiconductor substrate is inserted is buried with an insulator so that the semiconductor substrate is buried on one principal surface side of the insulating substrate, and then the support substrate is peeled from the insulating substrate and the semiconductor substrate. I do. Further, before bonding the support substrate to the insulating substrate or after peeling the support substrate from the insulating substrate, a step of forming an external lead wiring on one main surface side of the insulating substrate is performed.
[0013]
The second method is performed as follows. First, the semiconductor substrate on which the wiring between chips is formed is bonded to the supporting substrate with the surface on which the wiring between chips is formed facing the supporting substrate. Next, an insulator is attached to the supporting substrate in a state where the semiconductor substrate is embedded, and the insulating substrate is used as an insulating substrate. Then, the supporting substrate is separated from the insulating substrate and the semiconductor substrate. Next, external lead wires are formed on the surface of the insulating substrate on the side where the semiconductor substrate is embedded.
[0014]
Further, in the method of manufacturing a semiconductor device according to the present invention, after forming a circuit board by the above-described first method or second method, a plurality of semiconductor chips are connected via inter-chip wiring of the semiconductor substrate. In a state where the external circuit connection terminals of the semiconductor chips are connected to the external lead-out wiring of the insulating substrate, a step of mounting these semiconductor chips on the insulating substrate and the semiconductor substrate is performed.
[0015]
The circuit board and the semiconductor device having the above-described configurations can be obtained by the first method or the second method as described above and the steps performed subsequently thereto.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a circuit board and a method of manufacturing the same, and a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.
[0017]
<First embodiment>
FIG. 1 is a sectional view showing a first embodiment of a circuit board to which the present invention is applied, and FIG. 2 is a sectional view of a semiconductor device using the circuit board shown in FIG. Hereinafter, the circuit board of the first embodiment and a semiconductor device using the same will be described in this order with reference to FIGS. In the description of the circuit board, description will be given based on FIG. 1 with reference to FIG. 2, and members shown only in FIG.
[0018]
The circuit board 1 shown in these figures constitutes a so-called MCM type semiconductor device (4) on which a plurality of semiconductor chips (2) and (3) are mounted. The circuit board 1 is filled with an insulating substrate 5, a semiconductor substrate 7 embedded on one main surface (first surface 5 a) side of the insulating substrate 5, and a space between the insulating substrate 5 and the semiconductor substrate 7. It is composed of an insulator 9 which forms a part of the insulating substrate 7 integrally with the insulating substrate 7.
[0019]
Among these, the insulating substrate 5 is made of ceramic or resin, and has a through hole 11 in the center of which the semiconductor substrate 7 is fitted. On the first surface 5a on the side where the semiconductor substrate 7 is embedded, an external lead-out line 13 for connecting the semiconductor chips (2) and (3) to an external circuit is formed. Although not shown here, the external lead-out wiring 13 is connected to the second surface 5b from the first surface 5a side of the insulating substrate 5 through a via hole provided through the insulating substrate 5. May be pulled out to the side.
[0020]
The semiconductor substrate 7 is buried on the first surface 5a side of the insulating substrate 5 with one surface exposed. In particular, in the buried state, the exposed surface 7a of the semiconductor substrate 7 exposed on the first surface 5a side of the insulating substrate 5 is flush with the first surface 5a of the insulating substrate 5 (same height). Preferably, they are arranged. The exposed surface 7a is provided with a so-called inter-chip wiring 15 as a wiring or an electrode pad for connecting the semiconductor chips (2) and (3).
[0021]
Here, it is preferable that the semiconductor substrate 7 has a minimum necessary size for providing the inter-chip wiring 15 on the exposed surface 7a.
[0022]
Next, a configuration of the semiconductor device 4 using the circuit board 1 having the above configuration will be described with reference to FIG.
[0023]
The semiconductor device 4 shown in this figure is an MCM type semiconductor device in which a plurality of semiconductor chips 2 and 3 are mounted on a circuit board 1, and has different functions such as a semiconductor chip for logic and a semiconductor chip for memory. Are mounted in combination on one circuit board 1 to constitute a system-in-package.
[0024]
Here, on each of the semiconductor chips 2 and 3, a terminal drawn out from the internal circuit is formed together with a functional circuit having the respective functions. For example, the semiconductor chip 2 includes an internal circuit terminal 20a for connection with the other semiconductor chip 3 and an external circuit connection terminal 20b for connection with an external circuit. It is provided in a state exposed to the side. Similarly, the semiconductor chip 3 includes an internal circuit terminal 30a for connection with the other semiconductor chip 2 and an external circuit connection terminal 30b for connection with an external circuit. It is provided in a state exposed on the 3a side.
[0025]
The semiconductor chips 2 and 3 are connected with the terminals 20 a, 20 b, 30 a and 30 b of the semiconductor chips 2 and 3 and the wirings 13 and 15 of the circuit board 1 via the protruding electrodes 41. It is mounted on a circuit board 1. Specifically, the semiconductor chips 2 and 3 connect the internal circuit terminals 20 a and 30 a to the inter-chip wiring 15 of the semiconductor substrate 7 forming the circuit board 1, and form the insulating substrate 5 forming the circuit board 1. It is assumed that the external lead wiring 13 is mounted on the circuit board 1 in a state where the external circuit connection terminals 20b and 30b are connected.
[0026]
Although not shown here, the space between the circuit board 1 and the semiconductor chips 2 and 3 may be filled with an underfill to supplement the connection strength.
[0027]
In order to connect the semiconductor device 4 configured as described above to an external circuit (not shown), a wire is connected to the external lead-out electrode 13 formed on the insulating substrate 5 constituting the circuit board 1. Bonding (not shown) is performed. However, when the external lead-out wiring 13 is drawn from the first surface 5a side of the insulating substrate 5 to the second surface 5b side, a projecting electrode is formed on the external lead-out wiring part drawn out to the second surface 5b side. Thus, the semiconductor device 4 is flip-chip connected to the external circuit.
[0028]
Next, a method of manufacturing the circuit board 1 and the semiconductor device 4 having the above-described configurations will be described with reference to FIG.
[0029]
First, as shown in Fig. 3A, an insulating substrate 5 having a through hole 11 in the center and an external lead-out wiring 13 formed on one principal surface side of the first surface 5a is manufactured. The substrate 5 has, for example, a structure in which a through hole 5 is formed in the center of a normal ceramic circuit board or a resin circuit board, and the external lead-out wiring 13 is formed by, for example, a printed wiring or plating method. Either the formation of the through-hole 11 or the formation of the external lead-out wiring 13 may be performed first.
[0030]
Next, as shown in FIG. 3B, a support substrate 101 is bonded to the first surface 5a side of the insulating substrate 5 so as to cover the through hole 11. At this time, for example, the insulating substrate 5 and the supporting substrate 101 are bonded via the adhesive 102. Here, the support substrate 101 only needs to have a bonding surface that is slightly larger than the size that closes the through-hole 11, and need not be formed larger than the insulating substrate 5 as illustrated. The adhesive 102 is made of a material whose adhesive strength is reduced by light irradiation such as ultraviolet rays, or a material which can selectively remove a chemical solution from the insulating substrate 5. In particular, when the adhesive 102 is formed of a material whose adhesive strength is reduced by light irradiation, it is preferable to use a light-transmitting material such as quartz or glass for the support substrate 101. The adhesive 102 may be provided in advance on the entire surface of the bonding surface of the support substrate 101 as shown in the drawing, or may be provided on the first surface 5a of the insulating substrate 5. good.
[0031]
After the above, as shown in FIG. 3C, the semiconductor substrate 7 having the inter-chip wiring 15 formed on one main surface side is prepared. The inter-chip wiring 15 is a fine wiring formed by a semiconductor process.
[0032]
The semiconductor substrate 7 is placed in the through hole 11 of the insulating substrate 5 with the surface of the semiconductor substrate 7 on which the inter-chip wiring 15 is provided facing the surface of the support substrate 101 on which the adhesive 102 is provided. And bonded to the support substrate 101 via the adhesive 102. If the adhesive 102 is not provided in advance on the entire surface of the support substrate 101 on the bonding surface side, the adhesive 102 should be provided on the surface of the semiconductor substrate 7 on which the inter-chip wiring 15 is provided. And
[0033]
Next, as shown in FIG. 3D, the inside of the through hole 11 into which the semiconductor substrate 7 is inserted is filled with an insulator 9 made of a resin material or the like, and is cured. Thus, the semiconductor substrate 7 is buried on the first surface 5a side of the insulating substrate 5 integrated with the insulator 9.
[0034]
Thereafter, as shown in FIG. 3E, the supporting substrate 101 is separated from the insulating substrate 5 and the semiconductor substrate 7. At this time, when the adhesive 102 is made of a material whose adhesive strength is reduced by light irradiation, the adhesive force of the adhesive 102 is reduced by light irradiation from the support substrate 101 side, and the adhesive 102 is insulated together with the support substrate 101. Peeled from the substrate 5 and the semiconductor substrate 7. On the other hand, when the adhesive 102 is made of a material that can be selectively removed from the insulating substrate 5 by a chemical solution, the adhesive 102 and the supporting substrate 101 are combined with the insulating substrate 5 by wet processing using the selected chemical solution. 5 and the semiconductor substrate 7. At this time, the support substrate 101 may be removed by etching at the same time.
[0035]
As described above, the circuit board 1 according to the first embodiment described with reference to FIG. 1 is obtained. Note that FIG. 3E and FIG. 1 are upside down.
[0036]
Then, in order to obtain a semiconductor device using the circuit board 1, first, as shown in FIG. 2, the internal circuit terminals 20a and 30a, the external circuit connection terminals 20b and 30b of the semiconductor chips 2 and 3, and The protruding electrode 40 is formed on at least one of the external extraction wiring 13 and the inter-chip wiring 15 of the circuit board 1. Then, via these protruding electrodes 41, the internal circuit terminals 20a, 30a of the semiconductor chips 2, 3 are connected to the inter-chip wiring 15 of the semiconductor substrate 7, and the semiconductor chip is connected to the external extraction wiring 13 of the insulating substrate 5. Semiconductor chips 2 and 3 are mounted on circuit board 1 so as to connect external circuit connection terminals 20b and 30b.
[0037]
As described above, the semiconductor device 4 of the first embodiment described with reference to FIG. 2 is completed.
[0038]
In the circuit board 1 and the semiconductor device 4 of the first embodiment described above, the inter-chip wiring 15 for connecting the semiconductor chips 2 and 3 is provided on the semiconductor substrate 7, so that the semiconductor process is applied. A finely formed inter-chip wiring 15 is used. Therefore, a plurality of semiconductor chips 2 and 3 can be connected by the large-capacity inter-chip wiring 15. Moreover, by providing the external lead-out wiring 13 for connecting the semiconductor chips 2 and 3 and the external circuit to the insulating substrate 5, the above-mentioned semiconductor substrate 7 can be provided between the chips which are particularly required to be miniaturized. What is necessary is just to have the minimum required size in which only the wiring 15 is formed. Therefore, the use area of the semiconductor substrate 7 can be reduced as compared with a circuit board (for example, a silicon interposer) in which all of the inter-chip wiring and the external lead wiring are formed on the semiconductor substrate.
[0039]
As a result, it is possible to reduce the component cost of the circuit board 1 and the semiconductor device 4 while maintaining high functionality such that the semiconductor chips 2 and 3 can be connected by fine wiring.
[0040]
In the manufacturing method of the first embodiment described above, as described with reference to FIG. 3B, the procedure is such that the insulating substrate 5 on which the external lead-out wiring 13 is formed is bonded to the support substrate 101. The formation of the external extraction wiring 13 may be performed after the support substrate 101 is separated from the insulating substrate 5 as described with reference to FIG.
[0041]
Further, as described above, the external lead wiring may be drawn from the first surface 5a side of the insulating substrate 5 to the second surface 5b side. In this case, for example, a via hole is formed in the insulating substrate 5 by a laser beam, and a conductive material (copper) is buried therein by a plating method, so that the via hole is drawn out from the first surface 5a side to the second surface 5b. External lead wiring is formed. When such external lead-out lines are formed, the size of the circuit board 1 and the semiconductor device 4 can be reduced more than when the external lead-out lines 13 are formed only on the first surface 5a side.
[0042]
<Second embodiment>
FIG. 4 is a sectional view showing a second embodiment of a circuit board to which the present invention is applied, and FIG. 5 is a sectional view of a semiconductor device using the circuit board shown in FIG. Hereinafter, a circuit board according to the second embodiment and a semiconductor device using the same will be described in this order with reference to FIGS. In the description of the circuit board, description will be made based on FIG. 4 with reference to FIG. 5, and members shown only in FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and the duplicate description will be omitted.
[0043]
The difference between the circuit board 1 'of the second embodiment shown in these figures and the circuit board described in the first embodiment with reference to FIGS. 1 and 2 lies in the configuration of the insulating substrate 5'. Is similar to that of the first embodiment.
[0044]
That is, the insulating substrate 5 'is an integral body formed so that the semiconductor substrate 7 is embedded on one principal surface (first surface 5a') side, and is made of, for example, resin. On the first surface 5a 'on the side where the semiconductor substrate 7 is embedded, an external lead-out wiring 13' for connecting the semiconductor chips (2) and (3) and an external circuit is formed. The external lead-out wiring 13 ′ is drawn from the first surface 5 a ′ side of the insulating substrate 5 ′ to the second surface 5 b ′ while being filled in a via hole penetrating the insulating substrate 5 ′. And Although not shown here, the external lead-out wiring 13 'may be arranged only on the first surface 5a' side of the insulating substrate 5 '. In this case, it is assumed that one end of the external lead-out wiring 13 'is drawn out to the peripheral side of the insulating substrate 5'.
[0045]
Then, a semiconductor substrate 7 similar to that described in the first embodiment is embedded in the insulating substrate 5 ′ having such a configuration on the first surface 5a ′ side with the exposed surface 7a exposed. I do.
[0046]
Next, a configuration of the semiconductor device 4 'using the circuit board 1' having the above configuration will be described with reference to FIG.
[0047]
The difference between the semiconductor device 4 'of the second embodiment shown in this figure and the semiconductor device described with reference to FIG. 2 in the first embodiment is that the circuit board 1' as described above is used. Other configurations are the same as in the first embodiment.
[0048]
That is, the semiconductor device 4 'is an MCM type semiconductor device having a plurality of semiconductor chips 2 and 3 mounted on a circuit board 1'. The semiconductor chips 2 and 3 are connected with the terminals 20 a, 20 b, 30 a and 30 b of the semiconductor chips 2 and 3 and the wirings 13 ′ and 15 of the circuit board 1 ′ via the protruding electrodes 41. It is mounted on a circuit board 1 '. Specifically, the semiconductor chips 2 and 3 are configured such that the internal circuit terminals 20a and 30a are connected to the inter-chip wiring 15 of the semiconductor substrate 7 forming the circuit board 1 ', and the insulating substrate forming the circuit board 1' is formed. It is mounted on the circuit board 1 'in a state where the external circuit connection terminals 20b and 30b are connected to the 5' external lead-out wiring 13 '.
[0049]
Although illustration is omitted here, a configuration in which an underfill is filled between the circuit board 1 'and the semiconductor chips 2 and 3 to supplement the connection strength may be employed.
[0050]
Further, in order to connect the semiconductor device 4 ′ configured as described above to an external circuit (not shown), a portion of the external lead-out wiring 13 ′ drawn to the second surface 5b ′ side of the circuit board 1 ′ is required. The semiconductor device 4 ′ is flip-chip connected to an external circuit by forming a protruding electrode on the semiconductor device 4 ′. However, when the external lead-out wiring 13 ′ is arranged only on the first surface 5 a ′ side of the insulating substrate 5 ′, it is drawn out to the peripheral side of the insulating substrate 5 ′ with respect to the semiconductor chips 2 and 3. Wire bonding is performed on the external lead-out wiring portion.
[0051]
Next, a method for manufacturing the circuit board 1 ′ and the semiconductor device 4 ′ having the above-described configuration will be described with reference to FIG.
[0052]
First, as shown in FIG. 6A, a semiconductor substrate 7 similar to that of the first embodiment is prepared. Then, the semiconductor substrate 7 and the support substrate 101 are bonded via the adhesive 102 in a state where the surface of the semiconductor substrate 7 on which the inter-chip wiring 15 is formed faces the support substrate 101 side. At this time, the semiconductor substrate 7 is bonded to the center of the support substrate 101. The same support substrate 101 and adhesive 102 as those in the first embodiment are used. However, the bonding surface of the support substrate 101 has the same shape as the surface on which the wiring of the circuit board formed here is formed. The adhesive 102 is provided on the entire surface on the support substrate 101 side.
[0053]
Next, as shown in FIG. 6B, an insulator made of a resin or the like is applied to the support substrate 102 by a coating method such as a spin coating method to flatten the surface while the semiconductor substrate 7 is embedded. Next, this is cured to form an insulating substrate 5 '. Thus, the semiconductor substrate 7 is buried on the first surface 5a 'side of the insulating substrate 5'.
[0054]
Thereafter, as shown in FIG. 6C, the supporting substrate 102 is peeled off from the insulating substrate 5 ′ and the semiconductor substrate 7. This step is performed in the same manner as described in the first embodiment with reference to FIG. The pseudo wafer manufacturing method disclosed in JP-A-2001-308116 can be applied to the steps shown in FIGS. 6A to 6C.
[0055]
Next, as shown in FIG. 6D, an external lead-out wiring 13 'is formed on the surface of the insulating substrate 5' on the side where the semiconductor substrate 7 is embedded. At this time, for example, a via hole is formed in the insulating substrate 5 ′ by a laser beam, and a conductive material (copper) is buried in the inside of the via hole by a plating method, so that the first surface 5a ′ is changed to the second surface 5b ′. The extracted external lead-out wiring 13 'is formed. Further, external lead-out wiring may be formed only on the first surface 5 'side of the insulating substrate 5' by a normal printed wiring or plating method.
[0056]
Thus, the circuit board 1 'of the second embodiment described with reference to FIG. 4 is obtained. Note that FIG. 6D and FIG. 4 are upside down.
[0057]
In order to obtain a semiconductor device using such a circuit board 1 ′, first, as shown in FIG. 5, the internal circuit terminals 20 a and 30 a of the semiconductor chips 2 and 3 and the external circuit connection terminals 20 b , 30b, and a protruding electrode 41 connected to at least one of the external extraction wiring 13 'of the circuit board 1 and the inter-chip wiring 15. Then, the internal circuit terminals 20a and 30a of the semiconductor chips 2 and 3 are connected to the inter-chip wiring 15 of the semiconductor substrate 7 via these protruding electrodes 41, and the semiconductor chip is connected to the external extraction wiring 13 'of the insulating substrate 5. The semiconductor chips 2 and 3 are mounted on the circuit board 1 'so as to connect the external circuit connection terminals 20b and 30b.
[0058]
Thus, the semiconductor device 4 'of the second embodiment described with reference to FIG. 5 is completed.
[0059]
Similarly to the first embodiment, the circuit board 1 'and the semiconductor device 4' having the above-described configuration have a configuration in which the inter-chip wiring 15 is provided on the semiconductor substrate 7 for connecting the semiconductor chips 2 and 3 to each other. As a result, it is possible to reduce the component cost of the circuit board 1 ′ and the semiconductor device 4 ′ while maintaining the high functionality such that the semiconductor chips 2 and 3 can be connected by fine wiring. Become. The external lead-out wiring 13 ′ on the circuit board 1 ′ is drawn from the first surface 5 a ′ side to the second surface 5 b ′ as shown in the figure, so that the external lead-out wiring is provided only on the first surface side. It is possible to reduce the size of the circuit board and the semiconductor device as compared with the case where they are formed.
[0060]
【The invention's effect】
As described above, according to the circuit board and the semiconductor device of the present invention, the circuit board in which the inter-chip wiring for connecting the semiconductor chips is provided is embedded on the surface of the insulating substrate on which the external lead-out wiring is formed. By adopting the substrate configuration, while maintaining high functionality such that semiconductor chips can be connected by fine wiring using a semiconductor process, the circuit size is reduced by minimizing the size of the semiconductor substrate. It is possible to reduce the cost of parts for the substrate and the semiconductor device.
Further, according to the method for manufacturing a circuit board of the present invention, it is possible to obtain a circuit board having the above-described configuration. Similarly, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device using such a circuit board is provided. It is possible to obtain
[Brief description of the drawings]
FIG. 1 is a cross-sectional configuration diagram of a circuit board according to a first embodiment.
FIG. 2 is a sectional configuration diagram of the semiconductor device of the first embodiment.
FIG. 3 is a cross-sectional process diagram illustrating a procedure for manufacturing the circuit board of the first embodiment.
FIG. 4 is a cross-sectional configuration diagram of a circuit board according to a second embodiment.
FIG. 5 is a cross-sectional configuration diagram of a semiconductor device according to a second embodiment.
FIG. 6 is a sectional process view showing a manufacturing procedure of the circuit board of the second embodiment.
[Explanation of symbols]
1, 1 'circuit board, 2, 3 semiconductor chip, 2a, 3a terminal forming surface (semiconductor chip), 4, 4' semiconductor device, 5, 5 'insulating substrate, 5a, 5a' One surface (one main surface of the insulating substrate), 7: semiconductor substrate, 9: insulator, 11: through hole, 13, 13 ': external lead-out wiring, 15: inter-chip wiring, 20b, 30b: for external circuit connection Terminals (semiconductor chips), 101, 102 ... support substrate

Claims (8)

複数の半導体チップ間を接続するためのチップ間配線と、これらの半導体チップと外部回路とを接続するための外部引出配線とを備えた回路基板であって、
前記外部引出配線を一主面側に設けてなる絶縁性基板と、
前記絶縁性基板の一主面側の中央部に埋め込まれ、当該絶縁性基板の一主面側に露出している面に前記チップ間配線を設けてなる半導体基板とからなる
ことを特徴とする回路基板。A circuit board comprising inter-chip wiring for connecting a plurality of semiconductor chips, and external lead-out wiring for connecting these semiconductor chips and an external circuit,
An insulating substrate provided with the external lead-out wiring on one main surface side,
A semiconductor substrate which is embedded in a central portion on one main surface side of the insulating substrate and has the inter-chip wiring provided on a surface exposed on the one main surface side of the insulating substrate. Circuit board. 請求項１記載の回路基板において、
前記絶縁性基板の一主面と前記半導体基板における前記チップ間配線の形成面とは、同一面に配置されている
ことを特徴とする回路基板。The circuit board according to claim 1,
A circuit board, wherein one main surface of the insulating substrate and a surface of the semiconductor substrate on which the inter-chip wiring is formed are arranged on the same plane. 複数の半導体チップと、これらの半導体チップの端子形成面側に配置され当該半導体チップ間を接続するチップ間配線を備えた半導体基板とを有する半導体装置であって、
前記半導体基板は、前記複数の半導体チップの端子形成面に設けられた外部回路接続用端子を露出させる大きさで前記複数の半導体チップに対向配置されている
ことを特徴とする半導体装置。A semiconductor device comprising: a plurality of semiconductor chips; and a semiconductor substrate provided with a chip-to-chip wiring disposed on a terminal forming surface side of these semiconductor chips and connecting the semiconductor chips,
The semiconductor device according to claim 1, wherein the semiconductor substrate is arranged to face the plurality of semiconductor chips in such a size as to expose an external circuit connection terminal provided on a terminal formation surface of the plurality of semiconductor chips. 請求項３記載の半導体装置において、
前記半導体基板は、前記複数の半導体チップが搭載される絶縁性基板の一主面側に埋め込まれており、
前記複数の半導体チップの外部回路接続用端子は、前記絶縁性基板に形成された外部引出配線に接続されている
ことを特徴とする半導体装置。The semiconductor device according to claim 3,
The semiconductor substrate is embedded on one main surface side of the insulating substrate on which the plurality of semiconductor chips are mounted,
The semiconductor device according to claim 1, wherein the external circuit connection terminals of the plurality of semiconductor chips are connected to external lead-out wires formed on the insulating substrate. 複数の半導体チップ間を接続するためのチップ間配線と、これらの半導体チップと外部回路とを接続するための外部引出配線とを備えた回路基板の製造方法であって、
絶縁性基板の中央に形成された貫通孔を塞ぐ状態で、当該絶縁性基板に支持基板を貼り合わせる工程と、
前記チップ間配線が形成された半導体基板を、当該チップ間配線の形成面を前記支持基板に対向させた状態で前記貫通孔内に挿入して当該支持基板に貼り合わせる工程と、
前記半導体基板が挿入された貫通孔内を絶縁物で埋め込むことで前記絶縁性基板の一主面側に前記半導体基板を埋め込んだ状態で一体化した後、当該絶縁性基板および半導体基板から前記支持基板を剥離する工程とを行うと共に、
前記絶縁性基板に前記支持基板を貼り合わせる前、または前記絶縁性基板から前記支持基板を剥離した後に、前記絶縁性基板の一主面側に前記外部引出配線を形成する工程を行う
ことを特徴とする回路基板の製造方法。A method of manufacturing a circuit board including inter-chip wiring for connecting a plurality of semiconductor chips, and external lead-out wiring for connecting these semiconductor chips and an external circuit,
A step of attaching a support substrate to the insulating substrate while closing the through hole formed at the center of the insulating substrate,
A step of inserting the semiconductor substrate on which the inter-chip wiring is formed, inserting the semiconductor substrate with the formation surface of the inter-chip wiring facing the support substrate into the through hole, and bonding the semiconductor substrate to the support substrate;
By embedding the semiconductor substrate on one main surface side of the insulating substrate by embedding the inside of the through-hole into which the semiconductor substrate is inserted with an insulator, the support from the insulating substrate and the semiconductor substrate is performed. And a step of peeling the substrate,
Before bonding the support substrate to the insulating substrate, or after peeling the support substrate from the insulating substrate, a step of forming the external lead wiring on one main surface side of the insulating substrate is performed. Manufacturing method of a circuit board. 複数の半導体チップ間を接続するためのチップ間配線と、これらの半導体チップと外部回路とを接続するための外部引出配線とを備えた回路基板の製造方法であって、
前記チップ間配線が形成された半導体基板を、当該チップ間配線の形成面を支持基板に対向させた状態で当該支持基板に貼り合わせる工程と、
前記半導体基板を埋め込む状態で前記支持基板上に被着させた絶縁物を絶縁性基板として当該半導体基板と一体化した後、当該絶縁性基板および半導体基板から前記支持基板を剥離する工程と、
前記絶縁性基板における前記半導体基板が埋め込まれている側の面に外部引出配線を形成する工程とを行う
ことを特徴とする回路基板の製造方法。A method of manufacturing a circuit board including inter-chip wiring for connecting a plurality of semiconductor chips, and external lead-out wiring for connecting these semiconductor chips and an external circuit,
Bonding the semiconductor substrate on which the inter-chip wiring is formed to the support substrate in a state where the formation surface of the inter-chip wiring is opposed to the support substrate;
After integrating the insulator attached to the support substrate with the semiconductor substrate as an insulating substrate in a state where the semiconductor substrate is embedded, removing the support substrate from the insulating substrate and the semiconductor substrate,
Forming an external lead-out wiring on a surface of the insulating substrate on which the semiconductor substrate is embedded. 絶縁性基板の中央に形成された貫通孔を塞ぐ状態で、当該当該絶縁性基板に支持基板を貼り合わせる工程と、
チップ間配線が形成された半導体基板を、当該チップ間配線の形成面を前記支持基板に対向させた状態で前記貫通孔内に挿入して当該支持基板に貼り合わせる工程と、
前記半導体基板が挿入された貫通孔内を絶縁物で埋め込むことで前記絶縁性基板の一主面側に前記半導体基板を埋め込んだ状態で一体化した後、当該絶縁性基板および半導体基板から前記支持基板を剥離する工程と、
前記半導体基板のチップ間配線を介して複数の半導体チップを接続させると共に、これらの半導体チップの外部回路接続用端子を前記絶縁性基板に設けられた外部引出配線に接続させる状態で、これらの半導体チップを当該絶縁性基板および半導体基板上に搭載する工程とを行う
ことを特徴とする半導体装置の製造方法。In a state in which the through-hole formed in the center of the insulating substrate is closed, a step of attaching a support substrate to the insulating substrate,
A step of inserting the semiconductor substrate on which the wiring between chips is formed, inserting the semiconductor substrate on which the formation surface of the wiring between chips is opposed to the support substrate into the through hole, and bonding the semiconductor substrate to the support substrate;
By embedding the semiconductor substrate on one main surface side of the insulating substrate by embedding the inside of the through-hole into which the semiconductor substrate is inserted with an insulator, the support from the insulating substrate and the semiconductor substrate is performed. Removing the substrate;
A plurality of semiconductor chips are connected via inter-chip wiring of the semiconductor substrate, and these semiconductor chips are connected in a state where external circuit connection terminals of these semiconductor chips are connected to external lead-out wiring provided on the insulating substrate. Mounting a chip on the insulating substrate and the semiconductor substrate. チップ間配線が形成された半導体基板を、当該チップ間配線の形成面を前記支持基板に対向させた状態で当該支持基板に貼り合わせる工程と、
前記半導体基板を埋め込む状態で前記支持基板上に被着させた絶縁物を絶縁性基板として当該半導体基板と一体化した後、当該絶縁性基板および半導体基板から前記支持基板を剥離する工程と、
前記絶縁性基板における前記半導体基板が埋め込まれている側の面に外部引出配線を形成する工程と、
前記半導体基板のチップ間配線を介して複数の半導体チップを接続させると共に、これらの半導体チップの外部回路接続用端子を前記絶縁性基板の外部引出配線に接続させる状態で、これらの半導体チップを当該絶縁性基板および半導体基板上に搭載する工程とを行う
ことを特徴とする半導体装置の製造方法。Bonding the semiconductor substrate on which the inter-chip wiring is formed to the support substrate in a state where the formation surface of the inter-chip wiring is opposed to the support substrate;
After integrating the insulator attached to the support substrate with the semiconductor substrate as an insulating substrate in a state where the semiconductor substrate is embedded, removing the support substrate from the insulating substrate and the semiconductor substrate,
Forming an external lead-out wiring on a surface of the insulating substrate on which the semiconductor substrate is embedded,
A plurality of semiconductor chips are connected via inter-chip wiring of the semiconductor substrate, and these semiconductor chips are connected in a state where external circuit connection terminals of these semiconductor chips are connected to external lead-out wiring of the insulating substrate. Mounting the semiconductor device on an insulating substrate and a semiconductor substrate.
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