CN110544634A - chip integration method - Google Patents

chip integration method Download PDF

Info

Publication number
CN110544634A
CN110544634A CN201811266071.0A CN201811266071A CN110544634A CN 110544634 A CN110544634 A CN 110544634A CN 201811266071 A CN201811266071 A CN 201811266071A CN 110544634 A CN110544634 A CN 110544634A
Authority
CN
China
Prior art keywords
chip
substrate
glue
cured
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811266071.0A
Other languages
Chinese (zh)
Inventor
冯雪
刘兰兰
陈颖
叶柳顺
张柏诚
蒋晔
付浩然
李波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Institute of Flexible Electronics Technology of THU Zhejiang
Original Assignee
Tsinghua University
Institute of Flexible Electronics Technology of THU Zhejiang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University, Institute of Flexible Electronics Technology of THU Zhejiang filed Critical Tsinghua University
Priority to CN201811266071.0A priority Critical patent/CN110544634A/en
Publication of CN110544634A publication Critical patent/CN110544634A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

the invention discloses a chip integration method, which relates to the field of semiconductor manufacturing process, and comprises the following steps: providing a substrate, and forming adhesive glue at a chip mounting position of the substrate; providing a chip, and adhering the chip to the substrate through the adhesive glue; coating insulating glue on the side surface of the chip and the substrate around the chip; curing the insulating glue; and manufacturing a chip lead, wherein the chip lead extends from the chip to the substrate along the surface of the cured insulating glue. By adopting the technical scheme, the problems of breakage, debonding failure and the like of the connecting wire between the chip and the substrate can be inhibited, and the influence caused by the stress concentration phenomenon is reduced.

Description

Chip integration method
the invention relates to a divisional application of the invention application, which is filed on 2018, 5, 28 and 2018105225940 application numbers, and has the application name of a chip integration method and a chip integration structure.
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a chip integration method.
Background
Chip integration refers to the integration of chip leads and their off-chip circuitry onto the substrate of a device. In the conventional process, a packaged chip is used for chip integration. The packaged chip has leads which lead from contact pads in the chip (Die) for providing electrical contact to circuit elements within the chip. When the packaged chip is integrated into a device, the chip is wire-bonded to a substrate, and a circuit external to the chip is prepared on the substrate of the device to realize electrical connection of the chip.
The inventor finds that the prior art has at least the following defects in the process of implementing the invention:
because the size and the material property of the chip are different from those of the substrate, in the process of using the device, the phenomenon of stress concentration is generated at the joint of the chip and the substrate due to the sudden change of the geometric dimension and the material property, particularly, the stress concentration phenomenon is more likely to occur in the use process of the flexible electronic device, and the stress concentration phenomenon easily causes the problems of fracture, debonding failure and the like of a connecting wire between the chip and the substrate.
Disclosure of Invention
accordingly, there is a need for a chip integration method that can reduce the impact of stress concentration.
The embodiment of the invention provides a chip integration method, which comprises the following steps:
Providing a substrate, and forming adhesive glue at a chip mounting position of the substrate;
Providing a chip, and adhering the chip to the substrate through the adhesive glue;
Forming a buffer layer on a side surface of the chip and a substrate around the chip;
And manufacturing a chip lead, wherein the chip lead extends from the chip to the substrate along the surface of the buffer layer, and the chip lead is insulated from the side surface of the chip under the buffer layer and the surface of the substrate under the buffer layer.
in an alternative embodiment, the buffer layer is formed by printing using a 3D printing technique.
In an optional embodiment, the buffer layer is an ultraviolet light curing adhesive, and the buffer layer is cured by an ultraviolet light curing method.
in an alternative embodiment, the step of forming a buffer layer on the side of the chip and the substrate around the chip includes:
Printing a buffer layer on the side face of the chip and the substrate around the chip by adopting a 3D printing technology, so that the buffer layer forms a slope extending from the side face of the chip to the substrate.
In an alternative embodiment, the step of fabricating the chip leads includes:
Printing and forming a wire to be cured by taking the conductive paste as a raw material, wherein the wire to be cured extends from the chip to the substrate along the surface of the cured buffer layer;
And curing the wire to be cured to obtain the chip lead, wherein the chip lead is formed by printing by adopting a 3D printing technology.
In an alternative embodiment, the conductive paste is a thermally curable paste; and the lead to be cured is cured in a thermosetting mode.
In an alternative embodiment, after the step of fabricating the chip leads, the method further comprises:
forming a chip external circuit on the substrate;
and extending the chip lead from the chip to the substrate along the surface of the solidified buffer layer and connecting the chip lead with a chip external circuit.
In an alternative embodiment, the chip external circuit is printed by using a 3D printing technology, and the chip external circuit is integrally printed with the chip lead.
In an optional implementation, the chip integration method further includes:
printing the conductive paste serving as a raw material on the substrate to form a line to be cured;
And curing the line to be cured to obtain the chip external circuit.
In an optional embodiment, the adhesive glue is formed by printing through a 3D printing technology, and the adhesive glue is a thermosetting glue; the adhesive glue is cured in a thermosetting mode.
Compared with the prior art, the invention has the following outstanding beneficial effects:
The invention provides a chip integration method, which is characterized in that a chip is bonded on a substrate through bonding glue, so that the bonding capability between the chip and the substrate can be improved; the bonding capability of the chip and the substrate is enhanced by curing the insulating adhesive on the side surface of the chip and the substrate around the chip, the problems of fracture, debonding failure and the like of a connecting lead between the chip and the substrate are inhibited, and because a chip lead extends from the chip to the substrate along the surface of the cured insulating adhesive, the stress on the substrate is weakened by the buffering of the insulating adhesive when reaching the connecting lead, so that the influence of the stress concentration phenomenon on the connecting lead is reduced.
Drawings
fig. 1 is a flowchart of a chip integration method according to an embodiment of the present invention;
FIG. 2 is a schematic view of a substrate according to a second embodiment of the present invention;
Fig. 3 is a schematic diagram of a first step of a chip integration method according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of a second step of a chip integration method according to a second embodiment of the present invention;
fig. 5 is another schematic diagram of a second step of the chip integration method according to the second embodiment of the present invention;
fig. 6 is a schematic diagram of a fourth step of a chip integration method according to a second embodiment of the present invention;
FIG. 7 is a partial enlarged view of A in FIG. 6;
Fig. 8 is another schematic diagram of step four of a chip integration method according to a second embodiment of the present invention;
fig. 9 is a schematic diagram of step six of a chip integration method according to a second embodiment of the present invention;
fig. 10 is another schematic diagram of step six of a chip integration method according to a second embodiment of the present invention;
Fig. 11 is a schematic diagram of a seventh step of a chip integration method according to a second embodiment of the present invention;
fig. 12 is another schematic diagram of a seventh step of a chip integration method according to a second embodiment of the present invention;
fig. 13 is a schematic diagram of a chip integrated structure according to a third embodiment of the present invention;
fig. 14 is another schematic diagram of a chip integrated structure according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.
Example one
Fig. 1 is a flowchart of a chip integration method according to an embodiment.
Specifically, referring to fig. 1, the method for integrating chips provided in this embodiment includes:
S110, providing a substrate, and forming adhesive glue at the chip mounting position of the substrate;
S120, providing a chip, and adhering the chip to the substrate through the adhesive glue;
s130, coating insulating glue on the side surface of the chip and the substrate around the chip;
wherein the insulating glue has electrical insulation; the contact pads of the chip are used for providing electrical contact to the circuit elements inside the chip; by leading out the chip lead from the contact pad, the connection between the chip internal circuit and the chip external circuit is realized through the chip lead. The substrate around the chip refers to a substrate in a preset area around the chip.
S140, curing the insulating glue;
s150, manufacturing a chip lead, wherein the chip lead extends to the substrate from the chip along the surface of the cured insulating glue.
The chip is bonded on the substrate through the bonding glue, so that the bonding capability between the chip and the substrate can be improved; the bonding capability of the chip and the substrate is enhanced by curing the insulating adhesive on the side surface of the chip and the substrate around the chip, the problems of fracture, debonding failure and the like of a connecting lead between the chip and the substrate are inhibited, and because a chip lead extends from the chip to the substrate along the surface of the cured insulating adhesive, the stress on the substrate is weakened by the buffering of the insulating adhesive when reaching the connecting lead, so that the influence of the stress concentration phenomenon on the connecting lead is reduced.
the angle formed between the insulating glue and the substrate is adjusted by controlling the viscosity of the insulating glue, the printing thickness of the insulating glue and the setting angle of a printer, the angle formed between the printed and cured insulating glue and the substrate is 0-45 degrees, preferably 10 degrees, and the optimal bonding strength can be obtained by the angle.
In an alternative embodiment, the insulating glue is formed by printing through a 3D printing technology.
furthermore, the printing thickness of the insulating glue can be adjusted according to actual requirements; for example, the printing thickness of the insulating glue is determined according to the requirement of the volume of the chip.
Further, coating an insulating glue on the side surface of the chip and the substrate around the chip, specifically: printing an insulating glue on the side surface of the chip and the substrate around the chip by adopting a 3D printing technology, so that the insulating glue forms an inclined surface extending from the side surface of the chip to the substrate; the included angle between the inclined plane and the substrate is 0-45 degrees. Preferably, the included angle is 10 degrees, which is beneficial to improving the bonding strength of the insulating glue and the substrate. Optionally, the inclined surface is a linear inclined surface, a concave inclined surface, a convex inclined surface, a concave-convex inclined surface, or the like. Specifically, the included angle can be set through the preset viscosity of the insulating adhesive, the printing thickness of the insulating adhesive and the setting angle of the printer, so that the insulating adhesive meets the actual design requirement. Among them, the 3D printing technology is a technology for constructing an object by layer-by-layer printing using an adhesive material based on a digital model file. Through the 3D printing technology, the insulating glue can be coated more accurately, the reliability of the chip integrated structure is improved, and the automation of the manufacturing process is more favorably realized. Specifically, the insulating glue is a photo-curing glue. The light curing adhesive is adopted to improve the bonding strength, improve the reliability of a chip integrated structure and further improve the reliability of a device, and compared with the heat curing adhesive, the light curing adhesive reduces the energy consumption.
further, the insulating glue is ultraviolet curing glue, and the insulating glue is cured in an ultraviolet curing mode.
The low temperature of the ultraviolet curing adhesive during curing is utilized, so that the low temperature of the chip integration process is realized, the applicable substrate range is greatly increased, the ultraviolet curing adhesive can be applied to devices with requirements on welding temperature environments, and the stability of the devices is improved.
Specifically, the insulating glue is at least one or a mixture of at least two of acrylic resin glue, unsaturated polyester glue and polyurethane glue. Preferably, the insulating glue is acrylic resin glue, unsaturated polyester glue or polyurethane glue.
further, the chip lead is formed by printing through a 3D printing technology.
Specifically, the step of fabricating the chip lead includes: printing conductive paste serving as a raw material to form a wire to be cured, wherein the wire to be cured extends from the chip to the substrate along the surface of the cured insulating glue;
And curing the wire to be cured to obtain the chip lead.
Specifically, the conductive paste is used as a raw material to print and form a to-be-cured wire, and the to-be-cured wire extends from the chip to the substrate along the cured surface of the insulating adhesive, specifically:
based on a chip lead design rule, the conductive paste is used as a raw material to be printed to form a wire to be cured, and the wire to be cured extends from the chip to the substrate along the cured surface of the insulating adhesive.
through 3D printing technique promptly, can realize making the chip lead wire more accurately, for traditional corrosion process, it has saved loaded down with trivial details step, has characteristics such as environmental protection, manufacturing process are simple, quick.
optionally, the chip lead design rule includes a lead-out position of a contact pad on the chip and a position of a chip lead at one end of the substrate; the design rule of the chip lead wire can also comprise the leading-out sequence of each contact pad on the chip.
specifically, the conductive paste is thermosetting paste, and the wire to be cured is cured in a thermosetting manner; optionally, the curing temperature of the thermosetting slurry can be selected according to the high temperature resistance degree of the substrate, so as to prevent the curing temperature of the thermosetting slurry from exceeding the resistant temperature of the substrate; in this embodiment, the curing temperature of the conductive paste is 80 to 100 ℃.
Compared with the method of welding the chip lead to the substrate at high temperature in the traditional process, the method has the advantages that the chip lead is led out by the thermosetting slurry with the curing temperature of 80-100 ℃, and the optional range of the substrate can be increased.
Further, the conductive filler in the conductive paste is at least one or a mixture of at least two of micron silver powder, nanometer silver powder, micron copper powder, nanometer copper powder, silver-coated copper powder, micron gold powder, nanometer gold powder, graphene and carbon nanotubes.
Specifically, the conductive paste further includes a resin; through materials such as resin, the conductive paste has viscosity, has good adhesive force after being cured, is favorable for being in close contact with the insulating glue after being cured, and avoids sliding from the insulating glue.
Specifically, the conductive paste further includes other functional additives, for example, functional additives for imparting environmental aging resistance to the conductive paste after curing.
Furthermore, the thickness, curing time and curing temperature of the conductive paste can be adjusted according to actual requirements. For example, the curing temperature of the conductive paste is determined according to the temperature requirements of the substrate.
Specifically, the method further comprises:
after the insulating glue is cured, forming a chip external circuit on the substrate;
and extending the chip lead from the chip to the substrate along the cured surface of the insulating glue and connecting the chip lead with a chip external circuit.
After the insulating adhesive is cured, a chip external circuit may be formed on the substrate before step 150 is performed, after step 150 is performed, or simultaneously with step 150, which is not limited in the embodiment of the present invention.
further, the chip external circuit is formed by printing through a 3D printing technology.
optionally, the chip external circuit and the chip lead are integrally printed.
Specifically, the chip integration method further includes:
printing the conductive paste serving as a raw material on the substrate to form a line to be cured;
And curing the line to be cured to obtain the chip external circuit.
By ensuring the consistency of the medium between the external circuit of the chip and the lead of the chip, the working stability of the chip is improved, and the simplification of the manufacturing process is facilitated.
Further, the bonding glue is formed by printing through a 3D printing technology.
The 3D printing technology is adopted to print the adhesive glue, the insulating glue and the conductive paste, the implementation method of the process is unified, the control of the manufacturing process is simplified, and the reliability is improved.
Specifically, the glue applying thickness of the adhesive glue can be adjusted according to the height requirement of the chip.
Specifically, the formula components of the adhesive can be adjusted according to the heat dissipation requirement of the chip so as to improve the heat dissipation function.
specifically, the bonding glue is thermosetting glue, and the bonding glue is cured in a thermosetting mode; optionally, the curing temperature of the thermal curing adhesive can be selected according to the high temperature resistance degree of the substrate, so as to prevent the curing temperature of the thermal curing adhesive from exceeding the tolerance temperature of the substrate; in the present embodiment, the curing temperature of the adhesive is 80 to 100 ℃.
compared with the method of welding the chip lead to the substrate at high temperature in the traditional process, the method has the advantages that the chip is adhered to the substrate by the thermosetting adhesive with the curing temperature of 80-100 ℃, and the optional range of the substrate can be increased.
Specifically, the adhesive glue is at least one of epoxy resin glue, polyester resin glue, organic silicon resin glue and conductive glue or a mixture of at least two of the epoxy resin glue, the polyester resin glue, the organic silicon resin glue and the conductive glue.
preferably, the bonding glue is epoxy resin glue, polyester resin glue, organic silicon resin glue or conductive glue; if the bonding glue is epoxy resin glue, polyester resin glue or organic silicon resin glue, the bonding effect between the substrate and the chip is better; if the bonding glue is conductive glue, the chip can radiate heat through the conductive glue due to the good heat radiation performance of the conductive material.
Specifically, the conductive filler of the conductive adhesive is at least one or a mixture of at least two of micron silver powder, nanometer silver powder, micron copper powder, nanometer copper powder, silver-coated copper powder, micron gold powder, nanometer gold powder, graphene and carbon nanotubes.
The chip integration method provided by the second embodiment of the invention is described in detail below with reference to fig. 2 to 12.
The method comprises the following steps: providing a substrate, and forming adhesive glue at a chip mounting position of the substrate;
Fig. 2 is a schematic view of a substrate according to a second embodiment of the present invention; fig. 3 is a schematic diagram of a first step of a chip integration method according to a second embodiment of the present invention; as shown in fig. 3, adhesive paste 2 is printed on a predetermined position of the substrate 1.
step two: providing a chip, and adhering the chip to the substrate through the adhesive glue;
Fig. 4 is a schematic diagram of a second step of a chip integration method according to a second embodiment of the present invention; fig. 5 is another schematic diagram of a second step of the chip integration method according to the second embodiment of the present invention; as shown in fig. 4, the chip 3 is adhered to the substrate 1 by the adhesive 2. The adhesive glue 2 is not shown in fig. 5.
Step three: curing the bonding glue;
In this embodiment, the adhesive 2 is a thermal curing adhesive, which is cured by thermal curing at 80-100 ℃. In other embodiments, other curing temperatures of the adhesive can be selected.
Step four: coating insulating glue on the side surface of the chip and the substrate around the chip;
Fig. 6 is a schematic diagram of a fourth step of a chip integration method according to a second embodiment of the present invention; FIG. 7 is a partial enlarged view of A in FIG. 6; fig. 8 is another schematic diagram of step four of a chip integration method according to a second embodiment of the present invention; as shown in fig. 6, an insulating paste 4 is coated on the side of the chip 3 and the substrate around the chip 3; as shown in fig. 7, the insulating paste 4 forms a concave slope 7 from the side of the chip 3 to the substrate 1; in the embodiment, the included angle theta between the concave inclined surface 7 and the substrate is 0-45 degrees; preferably, the included angle θ is 10 degrees. As shown in fig. 8, an insulating paste 4 is coated on the substrate around the chip 3; the adhesive glue 2 is not shown in fig. 8.
Step five: curing the insulating glue;
Specifically, the insulating glue 4 is an ultraviolet curing glue, and is cured by an ultraviolet curing method.
Step six: manufacturing a chip lead;
Fig. 9 is a schematic diagram of step six of a chip integration method according to a second embodiment of the present invention; fig. 10 is another schematic diagram of step six of a chip integration method according to a second embodiment of the present invention. As shown in fig. 9 and 10, the chip leads 5 extend from the chip 3 to the substrate 1 along the surface of the cured insulating adhesive 4, it should be noted that the gaps between the chip leads 5 and the insulating adhesive 4 shown in fig. 9 are only for distinguishing the chip leads 5 from the insulating adhesive 4, and in actual processes, the chip leads 5 should be in contact with the insulating adhesive 4. The adhesive glue 2 is not shown in fig. 10.
step seven: a chip external circuit is formed on the substrate.
Fig. 11 is a schematic diagram of a seventh step of a chip integration method according to a second embodiment of the present invention; fig. 12 is another schematic diagram of step seven of a chip integration method according to a second embodiment of the present invention. It should be noted that, in fig. 11 and 12, a part of the wiring 6 of the chip external circuit is shown, but not all the circuits of the chip external circuit are shown, the thickness of the wires 6, and the chip external circuit formed on the substrate 1 should be based on the actual circuit design, and the embodiment of the present invention is not limited thereto. And forming a chip external circuit 6 on the substrate 1, and extending the chip lead 5 from the chip 3 to the substrate 1 along the surface of the cured insulating glue 4 and connecting the chip external circuit 6. The adhesive glue 2 is not shown in fig. 12.
EXAMPLE III
Fig. 13 is a schematic diagram of a chip integrated structure according to a third embodiment of the present invention; fig. 14 is another schematic diagram of a chip integrated structure according to a third embodiment of the present invention.
as shown in fig. 13 and 14, the chip integrated structure includes:
a substrate 11, a chip 13 adhered on the substrate 11, an insulating glue 14 positioned on the side surface of the chip 13 and the substrate around the chip, and a chip lead 15; the chip lead 15 extends from the chip 13 to the substrate 11 along the surface of the cured insulating adhesive 14.
The chip lead extends from the chip to the substrate along the surface of the cured insulating glue, and the stress on the substrate is weakened by the buffer of the insulating glue when reaching the connecting lead, so that the influence of the stress concentration phenomenon on the connecting lead is reduced.
Specifically, the insulating paste 14 is a photo-curing paste.
Further, the insulating glue is at least one or a mixture of at least two of acrylic resin glue, unsaturated polyester glue and polyurethane glue. Preferably, the insulating glue is acrylic resin glue, unsaturated polyester glue or polyurethane glue.
Specifically, the chip integrated structure further includes a chip external circuit (not shown in fig. 13 and 14) formed on the substrate, and the chip leads are connected to the chip external circuit.
It should be noted that the external circuit of the chip is based on the actual circuit design, and the embodiment of the present invention is not limited.
Specifically, the chip leads are integrally formed with the chip external circuit.
further, the chip integrated structure further includes an adhesive 12 located between the chip 13 and the substrate 11, the chip 13 is adhered to the substrate 11 by the adhesive 12, and the insulating glue 14 covers a side portion of the adhesive 12.
Namely, the chip is bonded on the substrate of the device through the bonding glue, so that the bonding capability between the chip and the substrate can be improved.
Specifically, the adhesive 12 is a heat-curable adhesive; the curing temperature of the bonding glue is 80-100 ℃.
Specifically, the adhesive glue 12 is at least one of epoxy resin glue, polyester resin glue, silicone resin glue and conductive glue or a mixture of at least two of the epoxy resin glue, the polyester resin glue, the silicone resin glue and the conductive glue.
Preferably, the adhesive glue 12 is an epoxy resin glue, a polyester resin glue, an organic silicon resin glue or a conductive glue; if the bonding glue 12 is an epoxy resin glue, a polyester resin glue or an organic silicon resin glue, the bonding effect between the substrate and the chip is better; if the bonding glue is conductive glue, the chip can radiate heat through the conductive glue due to the good heat radiation performance of the conductive material.
Specifically, the conductive filler of the conductive adhesive is at least one or a mixture of at least two of micron silver powder, nanometer silver powder, micron copper powder, nanometer copper powder, silver-coated copper powder, micron gold powder, nanometer gold powder, graphene and carbon nanotubes.
further, the insulating paste 14 has a slope extending from the side of the chip to the substrate; the included angle between the inclined plane and the substrate is 0-45 degrees; preferably, the included angle is 10 degrees, which is beneficial to improving the bonding strength of the insulating glue and the substrate.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
the above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method of chip integration, comprising:
Providing a substrate, and forming adhesive glue at a chip mounting position of the substrate;
providing a chip, and adhering the chip to the substrate through the adhesive glue;
Forming a buffer layer on a side surface of the chip and a substrate around the chip;
And manufacturing a chip lead, wherein the chip lead extends from the chip to the substrate along the surface of the buffer layer, and the chip lead is insulated from the side surface of the chip under the buffer layer and the surface of the substrate under the buffer layer.
2. The chip integration method according to claim 1, wherein the buffer layer is formed by printing using a 3D printing technique.
3. The chip integration method of claim 2, wherein the buffer layer is an ultraviolet-curable adhesive, and the buffer layer is cured by an ultraviolet curing method.
4. The chip integration method according to claim 2, wherein the step of forming a buffer layer on the side of the chip and the substrate around the chip comprises:
printing a buffer layer on the side face of the chip and the substrate around the chip by adopting a 3D printing technology, so that the buffer layer forms a slope extending from the side face of the chip to the substrate.
5. the chip integration method according to any one of claims 1 to 3, wherein the step of fabricating the chip leads comprises:
Printing and forming a wire to be cured by taking the conductive paste as a raw material, wherein the wire to be cured extends from the chip to the substrate along the surface of the cured buffer layer;
And curing the wire to be cured to obtain the chip lead, wherein the chip lead is formed by printing by adopting a 3D printing technology.
6. the chip integration method according to claim 5, wherein the conductive paste is a thermally cured paste; and the lead to be cured is cured in a thermosetting mode.
7. The chip integration method according to any one of claims 1 to 3, wherein after the step of fabricating chip leads, the method further comprises:
forming a chip external circuit on the substrate;
And extending the chip lead from the chip to the substrate along the surface of the solidified buffer layer and connecting the chip lead with a chip external circuit.
8. the chip integration method according to claim 7, wherein the chip external circuit is printed using a 3D printing technique, and the chip external circuit is printed integrally with the chip lead.
9. The chip integration method of claim 8, further comprising:
printing the conductive paste serving as a raw material on the substrate to form a line to be cured;
And curing the line to be cured to obtain the chip external circuit.
10. The chip integration method according to any one of claims 1 to 3, wherein the adhesive glue is formed by printing with a 3D printing technology, and the adhesive glue is a thermosetting glue; the adhesive glue is cured in a thermosetting mode.
CN201811266071.0A 2018-05-28 2018-05-28 chip integration method Pending CN110544634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811266071.0A CN110544634A (en) 2018-05-28 2018-05-28 chip integration method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810522594.0A CN110544633A (en) 2018-05-28 2018-05-28 Chip integration method and chip integration structure
CN201811266071.0A CN110544634A (en) 2018-05-28 2018-05-28 chip integration method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201810522594.0A Division CN110544633A (en) 2018-05-28 2018-05-28 Chip integration method and chip integration structure

Publications (1)

Publication Number Publication Date
CN110544634A true CN110544634A (en) 2019-12-06

Family

ID=68701242

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201811265966.2A Pending CN110544674A (en) 2018-05-28 2018-05-28 chip integrated structure
CN201811266071.0A Pending CN110544634A (en) 2018-05-28 2018-05-28 chip integration method
CN201810522594.0A Pending CN110544633A (en) 2018-05-28 2018-05-28 Chip integration method and chip integration structure

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201811265966.2A Pending CN110544674A (en) 2018-05-28 2018-05-28 chip integrated structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201810522594.0A Pending CN110544633A (en) 2018-05-28 2018-05-28 Chip integration method and chip integration structure

Country Status (1)

Country Link
CN (3) CN110544674A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112072880A (en) * 2020-09-02 2020-12-11 申艳华 Glue filling method for improving sealing and insulating capabilities of glue and conductor coating

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068714A (en) * 1989-04-05 1991-11-26 Robert Bosch Gmbh Method of electrically and mechanically connecting a semiconductor to a substrate using an electrically conductive tacky adhesive and the device so made
JP2004111415A (en) * 2002-09-13 2004-04-08 Sony Corp Circuit board, its manufacturing method, semiconductor device, and its manufacturing method
CN1531075A (en) * 2003-03-13 2004-09-22 ������������ʽ���� Electronic device and producing method thereof
US20080179726A1 (en) * 2007-01-31 2008-07-31 Siliconware Precision Industries Co., Ltd. Multi-chip semiconductor package and method for fabricating the same
US20080191324A1 (en) * 2007-02-08 2008-08-14 Chipmos Technologies (Bermuda) Ltd. Chip package structure and method of fabricating the same
US20110138600A1 (en) * 2009-12-11 2011-06-16 International Business Machines Corporation Electro-optical Assembly Fabrication
CN102751257A (en) * 2011-04-22 2012-10-24 三星半导体(中国)研究开发有限公司 Chip on board (COB) module and manufacture method thereof
CN103674399A (en) * 2013-12-25 2014-03-26 北京必创科技有限公司 Stress dispersion MEMS (Micro-Electro-Mechanical Systems) plastic package pressure sensor and preparation method thereof
CN104576570A (en) * 2013-10-25 2015-04-29 佳能株式会社 Electronic component, electronic apparatus, and method for manufacturing the electronic component
CN104851961A (en) * 2015-03-24 2015-08-19 湘能华磊光电股份有限公司 Chip scale packaging method and structure for light-emitting device
CN105161432A (en) * 2015-09-17 2015-12-16 中芯长电半导体（江阴）有限公司 Chip packaging method
CN105895785A (en) * 2016-04-25 2016-08-24 湘能华磊光电股份有限公司 Optical source assembly structure of flip LED chip integrated package and manufacturing method thereof
CN106847716A (en) * 2017-02-28 2017-06-13 上海图正信息科技股份有限公司 A kind of chip package process
CN106876344A (en) * 2017-01-23 2017-06-20 杰群电子科技（东莞）有限公司 A kind of semiconductor package and method for packing
CN107610803A (en) * 2017-09-11 2018-01-19 中山大学 A kind of 3D printing composite conducting wire rod and preparation method thereof
CN108010877A (en) * 2017-12-29 2018-05-08 中芯长电半导体（江阴）有限公司 The encapsulating structure and method for packing of semiconductor chip

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278726A (en) * 1992-01-22 1994-01-11 Motorola, Inc. Method and apparatus for partially overmolded integrated circuit package
TW411595B (en) * 1999-03-20 2000-11-11 Siliconware Precision Industries Co Ltd Heat structure for semiconductor package device
JP2001230360A (en) * 2000-02-18 2001-08-24 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
US6756252B2 (en) * 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US20080308914A1 (en) * 2006-03-17 2008-12-18 Chipmos Technologies Inc. Chip package
US8779569B2 (en) * 2010-01-18 2014-07-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
CN102097342B (en) * 2010-11-29 2013-04-17 南通富士通微电子股份有限公司 Packaging system and method for controlling thickness of chip loading adhesive
US8866274B2 (en) * 2012-03-27 2014-10-21 Infineon Technologies Ag Semiconductor packages and methods of formation thereof
CN109727935A (en) * 2016-04-08 2019-05-07 Oppo广东移动通信有限公司 A kind of chip-packaging structure, terminal device and method

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068714A (en) * 1989-04-05 1991-11-26 Robert Bosch Gmbh Method of electrically and mechanically connecting a semiconductor to a substrate using an electrically conductive tacky adhesive and the device so made
JP2004111415A (en) * 2002-09-13 2004-04-08 Sony Corp Circuit board, its manufacturing method, semiconductor device, and its manufacturing method
CN1531075A (en) * 2003-03-13 2004-09-22 ������������ʽ���� Electronic device and producing method thereof
US20080179726A1 (en) * 2007-01-31 2008-07-31 Siliconware Precision Industries Co., Ltd. Multi-chip semiconductor package and method for fabricating the same
US20080191324A1 (en) * 2007-02-08 2008-08-14 Chipmos Technologies (Bermuda) Ltd. Chip package structure and method of fabricating the same
US20110138600A1 (en) * 2009-12-11 2011-06-16 International Business Machines Corporation Electro-optical Assembly Fabrication
CN102751257A (en) * 2011-04-22 2012-10-24 三星半导体(中国)研究开发有限公司 Chip on board (COB) module and manufacture method thereof
CN104576570A (en) * 2013-10-25 2015-04-29 佳能株式会社 Electronic component, electronic apparatus, and method for manufacturing the electronic component
CN103674399A (en) * 2013-12-25 2014-03-26 北京必创科技有限公司 Stress dispersion MEMS (Micro-Electro-Mechanical Systems) plastic package pressure sensor and preparation method thereof
CN104851961A (en) * 2015-03-24 2015-08-19 湘能华磊光电股份有限公司 Chip scale packaging method and structure for light-emitting device
CN105161432A (en) * 2015-09-17 2015-12-16 中芯长电半导体（江阴）有限公司 Chip packaging method
CN105895785A (en) * 2016-04-25 2016-08-24 湘能华磊光电股份有限公司 Optical source assembly structure of flip LED chip integrated package and manufacturing method thereof
CN106876344A (en) * 2017-01-23 2017-06-20 杰群电子科技（东莞）有限公司 A kind of semiconductor package and method for packing
CN106847716A (en) * 2017-02-28 2017-06-13 上海图正信息科技股份有限公司 A kind of chip package process
CN107610803A (en) * 2017-09-11 2018-01-19 中山大学 A kind of 3D printing composite conducting wire rod and preparation method thereof
CN108010877A (en) * 2017-12-29 2018-05-08 中芯长电半导体（江阴）有限公司 The encapsulating structure and method for packing of semiconductor chip

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
仓田正也: "高技术事典-九十年代新技术新材料", 31 December 1989, 化学工业部科学技术情报研究所, pages: 146 - 148 *
黄志超: "精细化工应用配方之二——2600例", 28 February 1995, 广东科技出版社, pages: 589 - 592 *

Also Published As

Publication number Publication date
CN110544633A (en) 2019-12-06
CN110544674A (en) 2019-12-06

Similar Documents

Publication Publication Date Title
US8896111B2 (en) Semiconductor device and method for manufacturing the same
JP4941509B2 (en) Electronic control device
TWI415228B (en) Semiconductor package structures, flip chip packages, and methods for manufacturing semiconductor flip chip package
JP2000260918A (en) Semiconductor device with heat sink and manufacture thereof
WO2014010220A1 (en) Submount, sealed semiconductor element, and method for fabricating same
US20070102190A1 (en) Circuit device and method of manufacturing the same
JP6279162B2 (en) Semiconductor device and manufacturing method thereof
JP5822656B2 (en) Semiconductor device and manufacturing method thereof
JP2008192984A (en) Semiconductor device and method of manufacturing the same
CN110544634A (en) chip integration method
JP5898575B2 (en) Semiconductor device
CN108573935B (en) Semiconductor device and method for manufacturing the same
JP5691794B2 (en) Electronic control unit
CN103311197A (en) Substrate for power module
JP3666576B2 (en) Multilayer module and manufacturing method thereof
JP5404468B2 (en) Circuit board
JP4590294B2 (en) Manufacturing method of three-dimensional molded circuit components
JP4979542B2 (en) Mounting structure and manufacturing method thereof
JP5998033B2 (en) Semiconductor device and manufacturing method thereof
JP4735378B2 (en) Electronic component mounting structure and manufacturing method thereof
JP2008235492A (en) Semiconductor device and method of manufacturing the same
CN209434178U (en) The integrated morphology of semiconductor element
WO2024095812A1 (en) Circuit board and electronic module
WO2024095813A1 (en) Component mounting board, method for manufacturing component mounting board, electronic module, and method for manufacturing electronic module
CN209471948U (en) Integrated chip structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination