CN106847716A - A kind of chip package process - Google Patents
A kind of chip package process Download PDFInfo
- Publication number
- CN106847716A CN106847716A CN201710116561.1A CN201710116561A CN106847716A CN 106847716 A CN106847716 A CN 106847716A CN 201710116561 A CN201710116561 A CN 201710116561A CN 106847716 A CN106847716 A CN 106847716A
- Authority
- CN
- China
- Prior art keywords
- conducting wire
- printing
- chip
- chip package
- package process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000008569 process Effects 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 39
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052709 silver Inorganic materials 0.000 claims abstract description 9
- 239000004332 silver Substances 0.000 claims abstract description 9
- 238000007641 inkjet printing Methods 0.000 claims abstract description 7
- 238000007639 printing Methods 0.000 claims description 46
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 238000011017 operating method Methods 0.000 abstract description 2
- 239000000976 ink Substances 0.000 description 13
- 230000005540 biological transmission Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 241000218202 Coptis Species 0.000 description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 description 2
- 238000010924 continuous production Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010425 computer drawing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The present invention relates to circuit board production techniques field, more particularly to a kind of chip package process.The chip package process utilizes printed electronics ink-jet printer, nano silver conductive ink is printed as required conducting wire by the way of inkjet printing, and it is toasted after silver ink is condensed into solid-state silver wire so that chip is connected conducting with substrate external circuit.Said chip packaging technology step is simple, and operating desk is electronics ink-jet printer, and for the operating desk for using in the prior art, production cost is substantially reduced, and operating procedure also become it is more simple, while technology controlling and process is also more simple.
Description
Technical field
The present invention relates to circuit board production techniques field, more particularly to a kind of chip package process.
Background technology
Chip-packaging structure be by chip package on a substrate to protect chip.Trace and Exichnia in being set on substrate
Line connects external circuit, each other by means of through hole conducting.Interior trace is respectively provided with interior conductive welding pad and outer conductive welding pad with outer trace
As chip and the tie point of external circuit.Then, interior trace, outer trace and through hole are covered using green enamelled coating in order to avoid being damaged
Evil.Finally, it is packaged on substrate with interior conductive welding pad and with capsulation material using conducting element conducting chip.
The current chip encapsulation wire bonding routing techniques for using, as shown in figure 1, connecting the He of chip 2 with gold thread 3 more
Substrate 1 turns on external circuit.Though the method is ripe, operation machine is expensive, and operational sequence is various, technology controlling and process compared with
Complexity, it is relatively costly.
Therefore, a kind of chip package process how is proposed, the behaviour that chip package process is used in the prior art is can solve the problem that
Make that machine is expensive, operation is various, technology controlling and process is complicated, is those skilled in the art's technical issues that need to address.
The content of the invention
It is an object of the invention to propose a kind of chip package process, can solve the problem that chip package process makes in the prior art
Operation machine is expensive, the problem that operation is various, technology controlling and process is complicated.
It is that, up to this purpose, the present invention uses following technical scheme：
A kind of chip package process is provided, using printed electronics ink-jet printer, nano silver conductive ink ink-jet is used into
The mode of printing is printed as required conducting wire, and it is toasted after silver ink is condensed into solid-state silver wire so that core
Piece is connected conducting with substrate external circuit.
Said chip packaging technology step is simple, and operating desk is ink-jet printer, relative to what is used in the prior art
For operating desk, production cost is substantially reduced, and operating procedure also become it is more simple, while technology controlling and process step simplify, phase
It is more simple for prior art.
Preferably, it is described nano silver conductive ink is printed as required conducting wire by the way of the inkjet printing before
Including：
Insulating barrier is printed on the chip side wall of pre- hot substrate and substrate after preheat.
The purpose for setting insulating barrier is to prevent the ink print of printing conducting wire from causing short to chip to chip
Road.
Preferably, including before the pre- hot substrate：
Send the conducting wire printing layout data of required printing to printer.
The step is not performed in continuous production, when printing conducting wire is changed, then needs to perform technique step
Suddenly.
Preferably, the conducting wire printing domain is BMP forms.
Preferably, also including before the pre- hot substrate：
To be fitted with the substrate of chip feeding printer.
Preferably, the insulating barrier is obtained by way of printing dielectric ink is used into inkjet printing.
Preferably, temperature needed for the baking is 70-150 DEG C.
The step can make silver ink form solid-state silver wire, and then make conducting wire form more stable, prevent
Conducting wire form is unstable in subsequent step causes conducting wire to be broken.
Preferably, the conducting wire by required printing is printed before layout data sends printer to including：
Draw printing domain in position according to chip and substrate.
For different packaged chip structures, printing domain is differed, it is therefore desirable to repaint printing domain so as to lead
Electric line is printed to connect chip and substrate.
Preferably, the conducting wire printing layout data includes conducting wire section thickness data and conducting wire
Position coordinate data.
Because required conducting wire thickness is different, therefore printing layout data needs to include that conducting wire thickness can make
Conducting wire reaches predetermined thickness in print procedure.
Brief description of the drawings
Fig. 1 is the structural representation of the chip package that background of invention is provided；
Fig. 2 is the flow chart of chip package process provided in an embodiment of the present invention；
Fig. 3 is the structural representation of chip package provided in an embodiment of the present invention.
In figure：
1st, substrate；2nd, chip；3rd, gold thread；4th, conducting wire.
Specific embodiment
In order that those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and by specific
Implementation method further illustrates technical scheme.
As shown in Fig. 2 a kind of chip package process is provided in the present embodiment, and using printed electronics ink-jet printer, will
Nano silver conductive ink is printed as required conducting wire by the way of inkjet printing, and it is toasted after condense silver ink
Into solid-state silver wire, so that chip is connected conducting with substrate external circuit.
Wherein, nano silver conductive ink is printed as being needed before required conducting wire by the way of inkjet printing first pre-
Insulating barrier is printed on the chip side wall of hot substrate and substrate after preheat.The purpose for setting insulating barrier is under preventing liquid condition
Silver ink and the sidewall contact of chip 2 cause the short circuit of chip 2.
And by computer the conducting wire of printing should will be needed to print layout data before pre- hot substrate and send printing to
Machine, printing layout data refers to the data of the figure for being completed by computer drawing, in order to intuitively react needs
The data of the conducting wire 4 of printing, need the artificial printing edition drawn printing domain or obtain needs printing before the printing
Figure, then passes to printer so that printer realizes print job as needed by printing layout data again.The step is even
Need not be repeated in continuous production process, it is however noted that, in continuous producing initial stage, it is thus necessary to determine that in printer whether
Have been introduced into needing the conducting wire printing layout data of printing, can so ensure that electronics ink-jet printer is normally performed and beat
Print task.
Also need to be fitted with the substrate of chip feeding printer before pre- hot substrate, to ensure that silver ink is printed
On substrate.
Signified pre- hot substrate 1 refers to that the temperature of substrate 1 integrally heats up in the present embodiment, and nanometer silver inks are printed in the step
Water touches substrate 1 can accelerate evaporation rate, separate out Nano Silver and condense into silver-colored conducting wire 4.Prevent from being received in print procedure
Meter Yin Mo water not easy-formation, causes the waste of substrate 1, silver ink, and then reduce substandard products output capacity.
Wherein, also needed to before sending the conducting wire of required printing printing layout data to printer according to chip with
Draw printing domain in the position of substrate.When conducting wire 4 is different from existing printing domain, it is necessary to repaint on computers
Printing domain.Drafting printing domain is draws the position of conducting wire 4 and setting conduction according to the position of chip 2 and substrate 1
The length of circuit 4, width, height.Wherein conducting wire printing layout format should be BMP forms.BMP forms are Windows operations
Standard image file format in system, can be supported by various window applications.BMP forms are printers simultaneously
Default form.
Conducting wire printing layout data includes the section thickness data of conducting wire 4 and conducting wire 4 in the present embodiment
Position coordinate data, wherein the section thickness of required conducting wire 4 is different when different chips 2 are encapsulated, and single printing conductor wire
The section thickness of road 4 is limited, therefore, needing to carry out the conducting wire 4 of same position duplicate printing ability during printing conducting wire 4
The thickness of the conducting wire 4 after printing is enough set to reach desired value.
Chip 2 is fitted in the step on the corresponding position of substrate 1 can be with the position for drawing printer printing conducting wire 4
The step for putting is while carry out, and the substrate 1 for being fitted with chip 2 then can be transferred to printing by streamline automatic transmission mechanism
In machine.Streamline automatic transmission mechanism is prior art, be will not be repeated here.
Wherein printer nozzle should be arranged on the surface of the side wall of chip 2, and then conducting wire 4 is printed.
It should be noted that from the electronics ink-jet printer that positioning precision is ± 5 μm of (X, Y, Z), printing in the present embodiment
A width of 50 μm of conducting wire.And the PAD sizes of chip 2 are 90*90 μm, spacing is 200 μm.With existing wire bonding
Routing technique is compared, the printer low cost that the packaging technology of chip 2 provided in the present embodiment is used, and processing step
Simply, control simply, to make to be substantially reduced on production cost while chip package quality is ensured.
The high-temperature baking of substrate 1 of conducting wire 4 will be printed with, and then the silver-colored conducting wire under half curdled appearance can be made complete
Full solidification, strengthens the stability of conducting wire 4.Temperature needed for the baking of the present embodiment high temperature is 70-150 DEG C.Preferably, can
To select 70 DEG C, 80 DEG C, 90 DEG C, 100 DEG C, 110 DEG C, 120 DEG C, 130 DEG C, 140 DEG C, 150 DEG C of equivalent points, different value point is corresponded to,
Time needed for high-temperature baking is accordingly reduced with the raising of temperature.Preferred value point is 150 DEG C in the present embodiment.
Finished product is obtained after being printed with the high-temperature baking of substrate 1 of conducting wire 4, finished product is again by automatic transmission mechanism from printer
Inside spread out of.
The packaging effect figure of chip 2 is as shown in figure 3, the conducting wire 4 for wherein being printed by printer is by substrate 1 and chip 2
Connect so that chip 2 is packed.
Note, general principle of the invention and principal character and advantages of the present invention has been shown and described above.The industry
Technical staff it should be appreciated that the present invention is not limited to the embodiments described above, described in above-mentioned implementation method and specification
Merely illustrate the principles of the invention, without departing from the spirit and scope of the present invention, the present invention also have various change and
Improve, these changes and improvements all fall within the protetion scope of the claimed invention, and claimed scope of the invention is by appended
Claims and its equivalent thereof.
Claims (9)
1. a kind of chip package process, it is characterised in that utilize printed electronics ink-jet printer, nano silver conductive ink is used
The mode of inkjet printing is printed as required conducting wire, and it is toasted after silver ink is condensed into solid-state silver wire so that
Chip is set to be connected conducting with substrate external circuit.
2. chip package process according to claim 1, it is characterised in that described that nano silver conductive ink is used into ink-jet
The mode of printing is printed as including before required conducting wire：
Insulating barrier is printed on the chip side wall of pre- hot substrate and substrate after preheat.
3. chip package process according to claim 2, it is characterised in that include before the pre- hot substrate：
Send the conducting wire printing layout data of required printing to printer.
4. chip package process according to claim 3, it is characterised in that the conducting wire printing domain is BMP lattice
Formula.
5. the chip package process according to Claims 2 or 3, it is characterised in that also include before the pre- hot substrate：
To be fitted with the substrate of chip feeding printer.
6. chip package process according to claim 5, it is characterised in that the insulating barrier will be by that will print dielectric ink
Obtained by the way of inkjet printing.
7. chip package process according to claim 5, it is characterised in that temperature needed for the baking is 70-150 DEG C.
8. chip package process according to claim 3, it is characterised in that the conducting wire by required printing is printed
Layout data includes before sending printer to：
Draw printing domain in position according to chip and substrate.
9. chip package process according to claim 3, it is characterised in that the conducting wire printing layout data includes
Conducting wire section thickness data and conducting wire position coordinate data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710116561.1A CN106847716A (en) | 2017-02-28 | 2017-02-28 | A kind of chip package process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710116561.1A CN106847716A (en) | 2017-02-28 | 2017-02-28 | A kind of chip package process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106847716A true CN106847716A (en) | 2017-06-13 |
Family
ID=59137624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710116561.1A Pending CN106847716A (en) | 2017-02-28 | 2017-02-28 | A kind of chip package process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106847716A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109352985A (en) * | 2018-09-17 | 2019-02-19 | 上海航天设备制造总厂有限公司 | The 3D printing integrated manufacturing method of aerospace intelligent material sandwich structure |
| CN110481180A (en) * | 2019-07-05 | 2019-11-22 | 成都科愿慧希科技有限公司 | The method that ink jet printing prepares antenna |
| CN110544634A (en) * | 2018-05-28 | 2019-12-06 | 浙江清华柔性电子技术研究院 | chip integration method |
| CN111083877A (en) * | 2018-10-22 | 2020-04-28 | 广东聚华印刷显示技术有限公司 | Conductive circuit and preparation method thereof |
| US11081632B2 (en) | 2018-09-27 | 2021-08-03 | Chengdu Vistar Optoelectronics Co., Ltd. | Micro-LED chips and methods for manufacturing the same and display devices |
| CN113985652A (en) * | 2021-10-19 | 2022-01-28 | 惠州视维新技术有限公司 | Backlight plate, display device and preparation process of backlight plate |
| CN114953432A (en) * | 2022-05-20 | 2022-08-30 | 合肥本源量子计算科技有限责任公司 | Method for manufacturing signal transmission line by aerosol jet printing and application |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101560349A (en) * | 2009-04-22 | 2009-10-21 | 北京印刷学院 | Jet conductive ink |
| US20120175667A1 (en) * | 2011-10-03 | 2012-07-12 | Golle Aaron J | Led light disposed on a flexible substrate and connected with a printed 3d conductor |
| US20130344232A1 (en) * | 2012-06-22 | 2013-12-26 | Xerox Corporation | Methods of forming conductive features on three-dimensional objects |
| WO2014184960A1 (en) * | 2013-05-17 | 2014-11-20 | 富士機械製造株式会社 | Inspection device, inspection method, and control device |
| US20150207254A1 (en) * | 2014-01-22 | 2015-07-23 | Apple Inc. | Molded Plastic Structures With Graphene Signal Paths |
-
2017
- 2017-02-28 CN CN201710116561.1A patent/CN106847716A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101560349A (en) * | 2009-04-22 | 2009-10-21 | 北京印刷学院 | Jet conductive ink |
| US20120175667A1 (en) * | 2011-10-03 | 2012-07-12 | Golle Aaron J | Led light disposed on a flexible substrate and connected with a printed 3d conductor |
| US20130344232A1 (en) * | 2012-06-22 | 2013-12-26 | Xerox Corporation | Methods of forming conductive features on three-dimensional objects |
| WO2014184960A1 (en) * | 2013-05-17 | 2014-11-20 | 富士機械製造株式会社 | Inspection device, inspection method, and control device |
| US20150207254A1 (en) * | 2014-01-22 | 2015-07-23 | Apple Inc. | Molded Plastic Structures With Graphene Signal Paths |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110544634A (en) * | 2018-05-28 | 2019-12-06 | 浙江清华柔性电子技术研究院 | chip integration method |
| CN109352985A (en) * | 2018-09-17 | 2019-02-19 | 上海航天设备制造总厂有限公司 | The 3D printing integrated manufacturing method of aerospace intelligent material sandwich structure |
| US11081632B2 (en) | 2018-09-27 | 2021-08-03 | Chengdu Vistar Optoelectronics Co., Ltd. | Micro-LED chips and methods for manufacturing the same and display devices |
| CN111083877A (en) * | 2018-10-22 | 2020-04-28 | 广东聚华印刷显示技术有限公司 | Conductive circuit and preparation method thereof |
| CN110481180A (en) * | 2019-07-05 | 2019-11-22 | 成都科愿慧希科技有限公司 | The method that ink jet printing prepares antenna |
| CN113985652A (en) * | 2021-10-19 | 2022-01-28 | 惠州视维新技术有限公司 | Backlight plate, display device and preparation process of backlight plate |
| CN114953432A (en) * | 2022-05-20 | 2022-08-30 | 合肥本源量子计算科技有限责任公司 | Method for manufacturing signal transmission line by aerosol jet printing and application |
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| PB01 | Publication | ||
| PB01 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20170613 |