JP5822656B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP5822656B2
JP5822656B2 JP2011238163A JP2011238163A JP5822656B2 JP 5822656 B2 JP5822656 B2 JP 5822656B2 JP 2011238163 A JP2011238163 A JP 2011238163A JP 2011238163 A JP2011238163 A JP 2011238163A JP 5822656 B2 JP5822656 B2 JP 5822656B2
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semiconductor
semiconductor device
pellet
sintered
semiconductor pellet
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JP2013098266A (en
Inventor
良一 梶原
良一 梶原
元脇　成久
成久 元脇
聡 松吉
聡 松吉
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Hitachi Power Semiconductor Device Ltd
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Hitachi Power Semiconductor Device Ltd
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Description

本発明は、自動車、鉄道等に用いられる高耐熱・高信頼な鉛フリーの半導体装置にかかる。   The present invention relates to a highly heat-resistant and highly reliable lead-free semiconductor device used for automobiles, railways and the like.

従来、半導体装置において、半導体素子は鉛系はんだを用いて固定部材上に固定されていた。しかし、近年環境への影響が考慮され、はんだの鉛フリー対応が迫られている。   Conventionally, in a semiconductor device, a semiconductor element is fixed on a fixing member using lead-based solder. However, in recent years, the impact on the environment has been taken into consideration, and lead-free soldering has been urged.

そこで、高温はんだの代替材料となるナノＡｇ粒子等を用いた半導体装置及び半導体装置の接合方法が提案されている（特許文献１）。   Then, the semiconductor device using the nano Ag particle | grains etc. which become an alternative material of high temperature solder, and the joining method of a semiconductor device are proposed (patent document 1).

特許文献１では、半導体チップと絶縁基板との接合信頼性を高めるために、接合層に金属コアを用いることによって、ペーストが含有する揮発性有機成分を蒸散させる蒸散経路を確保することによって、接合面全域で未接合部の無い接合が達成されることが開示されている。   In Patent Document 1, in order to increase the bonding reliability between the semiconductor chip and the insulating substrate, by using a metal core for the bonding layer, by securing a transpiration path for evaporating the volatile organic components contained in the paste, It is disclosed that joining without unjoined parts is achieved over the entire surface.

特開２００８−１０７０３号公報JP 2008-10703 A

しかし、上述した構成では、焼結Ａｇペーストの回り込みによる上下電極の短絡を防止することができない。さらに、上述した構成では、半導体チップと絶縁基板との間に金属コア材を挟んでいるため、温度サイクルの繰り返しによって、クラックが入る可能性がある。さらに、半導体装置が高温環境下で使用される場合、高温下と常温下での温度変化が大きいため、特にクラックが入る可能性が大きくなる。   However, in the above-described configuration, it is impossible to prevent the upper and lower electrodes from being short-circuited due to the wraparound of the sintered Ag paste. Furthermore, in the above-described configuration, since the metal core material is sandwiched between the semiconductor chip and the insulating substrate, there is a possibility that cracks may occur due to repeated temperature cycles. Further, when the semiconductor device is used in a high temperature environment, the temperature change between high temperature and normal temperature is large, so that the possibility of cracking increases.

本発明の目的は、上下電極の短絡を防止し、かつ高温環境下であっても優れた接合信頼性を確保した半導体装置を提供することである。   An object of the present invention is to provide a semiconductor device that prevents a short circuit between upper and lower electrodes and ensures excellent bonding reliability even in a high temperature environment.

本発明における半導体装置は、半導体ペレットと、前記半導体ペレットの一方の面に接合される絶縁シートと、前記半導体ペレットの他方の面と接合される金属板と、を備える半導体装置であって、前記絶縁シートは、前記半導体ペレットにおける外周部よりも突出しており、前記半導体素子の他方の面と、前記金属板とは焼結銀層を介して接続され、当該焼結銀層は、前記半導体ペレットの他方の面及び側面部を覆って接合されていることを特徴とする。   A semiconductor device according to the present invention is a semiconductor device comprising a semiconductor pellet, an insulating sheet bonded to one surface of the semiconductor pellet, and a metal plate bonded to the other surface of the semiconductor pellet, The insulating sheet protrudes from the outer peripheral portion of the semiconductor pellet, the other surface of the semiconductor element is connected to the metal plate via a sintered silver layer, and the sintered silver layer is connected to the semiconductor pellet. It is characterized in that the other surface and the side surface portion of the material are joined together.

本発明によると、上下電極の短絡を防止し、かつ高温環境下であっても優れた接合信頼性を確保した半導体装置を提供することが可能となる。   According to the present invention, it is possible to provide a semiconductor device that prevents a short circuit between upper and lower electrodes and ensures excellent bonding reliability even in a high temperature environment.

（ａ）第一の実施形態に係る半導体素子２００の上面図を示したものである。（ｂ）は（ａ）におけるＡ−Ａの断面図である。(A) The top view of the semiconductor element 200 which concerns on 1st embodiment is shown. (B) is sectional drawing of AA in (a). 第一の実施例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on a 1st Example. （ａ）〜（ｈ）は、第一の実施形態に係る半導体装置の製造方法を示した図である。(A)-(h) is the figure which showed the manufacturing method of the semiconductor device which concerns on 1st embodiment. 第二の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 2nd embodiment. 第三の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 3rd embodiment. 第四の実施形態に係る半導体素子２０２の上面図を示したものである。（ｂ）は（ａ）におけるＢ−Ｂの断面図である。The top view of the semiconductor element 202 which concerns on 4th embodiment is shown. (B) is sectional drawing of BB in (a). 図６の半導体装置２０２を実装した半導体装置の断面図である。It is sectional drawing of the semiconductor device which mounted the semiconductor device 202 of FIG. 第五の実施形態に係る半導体装置の上面図を示したものである。（ｂ）は（ａ）におけるＣ−Ｃの断面図である。FIG. 10 is a top view of a semiconductor device according to a fifth embodiment. (B) is CC sectional drawing in (a). 第六の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 6th embodiment. 第七の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 7th embodiment. 第八の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 8th embodiment.

以下、本発明の実施例を図面を用いて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

《第一の実施形態》
図１は、第一の実施形態にかかる半導体素子２００の平面及び断面構造を示すものである。 First embodiment
FIG. 1 shows a plan and sectional structure of a semiconductor element 200 according to the first embodiment.

ｎ型の半導体基板２の上部には、ＳｉＯ2膜６をマスクとしてホウ素を拡散したＰ型半導体領域５が形成され、最表面が貴金属で構成された金属電極４が形成され、半導体基板２の裏面全面に最表面が貴金属で構成された金属電極３が形成され、半導体ペレット１が構成されている。半導体ペレット１の上面には、パターニングされた金属電極４のサイズより小さい開口部８が形成され、外形が辺の中央領域でペレットサイズより大きく加工されたポリイミドまたはフッ素樹脂の有機絶縁シート７が、アクリル系またはシリコーン系の粘着剤９によって接着されている。有機絶縁シート７のコーナー部は切断されてペレットのコーナーと同サイズの形状となっている。なお、有機絶縁シート７のコーナー部は切断されていなくてもよい。しかし、後述するように、金属電極４に塗布された焼結Ａｇペーストは、圧力がかかることによって同心円状に広がっていくので、絶縁シート７のコーナー部を切断した方が、本発明の効果を維持でき、かつコストを低減することができるので望ましい。 A p-type semiconductor region 5 in which boron is diffused using the SiO 2 film 6 as a mask is formed on the n-type semiconductor substrate 2, and a metal electrode 4 having an outermost surface made of a noble metal is formed. A metal electrode 3 having an outermost surface made of a noble metal is formed on the entire back surface, thereby forming a semiconductor pellet 1. An opening 8 smaller than the size of the patterned metal electrode 4 is formed on the upper surface of the semiconductor pellet 1, and an organic insulating sheet 7 of polyimide or fluororesin whose outer shape is processed larger than the pellet size in the central region of the side, It is adhered by an acrylic or silicone adhesive 9. The corner portion of the organic insulating sheet 7 is cut to have the same size as the corner of the pellet. In addition, the corner part of the organic insulating sheet 7 does not need to be cut | disconnected. However, as will be described later, since the sintered Ag paste applied to the metal electrode 4 spreads concentrically when pressure is applied, it is more effective to cut the corner portion of the insulating sheet 7. This is desirable because it can be maintained and the cost can be reduced.

図２は、図１の半導体素子２００を用いて組み立てたダイオードパッケージ３００の断面構造を示したものである。図では、半導体素子２００の詳細を省略して描いている。図において、Ｃｕのベース電極部材１３とリード電極部材１５には、全面に約５μｍ厚のＡｇめっきを施している。ベース電極部材１３の台座１４は逆台形に加工されており、リード電極部材１５先端の接合用ヘッド１６は、有機絶縁シート１２の開口部の中に納まるサイズに加工されている。なお、ここで言う逆台形形状とは、例えば、搭載面と平行に台座１４を切断したときの面の面積よりも、半導体ペレット１を搭載する面の面積の方が、大きくなるような形状のことを言う。また、実施形態ではベース電極部材１３の周辺部が台座１４と同じ高さになっているが、ベース電極部材１３の周辺部の高さは、台座１４の根元の高さと同じでも問題ない。半導体ペレット１の裏面は、下側のポーラスな焼結Ａｇ１７を介してベース電極部材の台座に金属接合されている。焼結Ａｇ１７は、半導体ペレット１の側面まで回り込み、有機絶縁シート７で高さが抑えられている。   FIG. 2 shows a cross-sectional structure of a diode package 300 assembled using the semiconductor element 200 of FIG. In the figure, the details of the semiconductor element 200 are omitted. In the figure, the Cu base electrode member 13 and the lead electrode member 15 are subjected to Ag plating with a thickness of about 5 μm on the entire surface. The base 14 of the base electrode member 13 is processed into an inverted trapezoid, and the bonding head 16 at the tip of the lead electrode member 15 is processed to a size that fits within the opening of the organic insulating sheet 12. The inverted trapezoidal shape referred to here is, for example, a shape in which the area of the surface on which the semiconductor pellet 1 is mounted is larger than the area of the surface when the pedestal 14 is cut in parallel with the mounting surface. Say that. In the embodiment, the peripheral portion of the base electrode member 13 has the same height as the pedestal 14, but there is no problem even if the height of the peripheral portion of the base electrode member 13 is the same as the height of the base of the pedestal 14. The back surface of the semiconductor pellet 1 is metal-bonded to the base of the base electrode member via the lower porous Ag 17. Sintered Ag 17 wraps around to the side surface of the semiconductor pellet 1 and is suppressed in height by the organic insulating sheet 7.

当該半導体ペレット１に設けられた有機絶縁シート７によって、焼結Ａｇペースト１７０が半導体ペレット１の上面に回り込むことなくダイオードパッケージ３００を作成することが可能になる。そのため、半導体ペレット１の上下面が短絡することを防ぐことができる。さらに、有機絶縁シート７によって、半導体ペレット１の裏面部だけでなく側面部についても焼結Ａｇ１７で覆うことが可能になり、接合強度が向上するので、高温状況下においても接合信頼性が向上する。   The organic insulating sheet 7 provided on the semiconductor pellet 1 makes it possible to produce the diode package 300 without the sintered Ag paste 170 going around the upper surface of the semiconductor pellet 1. Therefore, it is possible to prevent the upper and lower surfaces of the semiconductor pellet 1 from being short-circuited. Furthermore, since the organic insulating sheet 7 can cover not only the back surface portion but also the side surface portion of the semiconductor pellet 1 with the sintered Ag 17 and the bonding strength is improved, the bonding reliability is improved even under high temperature conditions. .

半導体ペレット１の上面は上側のポーラスな焼結Ａｇ１８によってリード電極部材１５の接合用ヘッド１６と金属接合されている。焼結Ａｇ１８は、有機絶縁シート７の開口部からはみ出して有機絶縁シート７上に拡がっているが、シートサイズより拡がってはいない。ベース電極部材１３及びリード電極部材１５の一部と、半導体ペレット１を含む接合部はシリカフィラーを混錬したエポキシ樹脂２０で封止されている。エポキシ樹脂２０とダイオード構成部材の界面のうち面積比率５０％以上の領域には金属と接着性に優れるイミド系またはアミドイミド系の有機皮膜１９が形成されている。   The upper surface of the semiconductor pellet 1 is metal bonded to the bonding head 16 of the lead electrode member 15 by the upper porous Ag 18. Sintered Ag 18 protrudes from the opening of the organic insulating sheet 7 and spreads on the organic insulating sheet 7, but does not extend beyond the sheet size. Part of the base electrode member 13 and the lead electrode member 15 and the joint including the semiconductor pellet 1 are sealed with an epoxy resin 20 kneaded with silica filler. An imide-based or amide-imide-based organic film 19 having excellent adhesion to a metal is formed in a region having an area ratio of 50% or more in the interface between the epoxy resin 20 and the diode component.

図３（ａ）〜（ｈ）は、本発明によるダイオードパッケージ３００の製造方法を説明する図である。図３（ａ）において、まずプレーナ型半導体ペレット１の上面に、電極サイズより一回り小さい開口部を有し外形が辺の部分でペレットサイズより大きい有機絶縁シート７を接着する。   3A to 3H are views for explaining a method of manufacturing a diode package 300 according to the present invention. In FIG. 3A, first, an organic insulating sheet 7 having an opening that is slightly smaller than the electrode size and having an outer shape that is larger than the pellet size is adhered to the upper surface of the planar semiconductor pellet 1.

次に図３（ｂ）に示すように、Ａｇめつきしたベース電極部材１３の台座部１４で半導体ペレット１を接合する領域に、焼結Ａｇペースト１７０を、中央部が盛り上がった状態にして供給する。なお、焼結Ａｇペースト１７０、及び後述する焼結Ａｇペースト１８０は、粒子径が０.２〜３μｍのマイクロＡｇ粒子を７０〜９４.５ｗｔ％含み、合計の金属成分含有量が９２〜９５ｗｔ％で残りが揮発性の有機溶剤と１.０ｗｔ％以下の低分子系樹脂から成る焼結Ａｇペーストであって粘度が６０〜１５０Ｐａ・ｓに調整されている。   Next, as shown in FIG. 3 (b), the sintered Ag paste 170 is supplied in a state where the central portion is raised in the region where the semiconductor pellet 1 is joined at the base portion 14 of the base electrode member 13 which is attached to Ag. To do. The sintered Ag paste 170 and the sintered Ag paste 180 described later contain 70 to 94.5 wt% of micro Ag particles having a particle diameter of 0.2 to 3 μm, and the total metal component content is 92 to 95 wt%. The remainder is a sintered Ag paste made of a volatile organic solvent and a low molecular weight resin of 1.0 wt% or less, and the viscosity is adjusted to 60 to 150 Pa · s.

また、図３（ｃ）に示すように、半導体ペレット１の上面の絶縁シート開口部の電極上に、焼結Ａｇペースト１８０を中央部が盛り上がった状態にして供給する。   Moreover, as shown in FIG.3 (c), the sintering Ag paste 180 is supplied in the state which raised the center part on the electrode of the insulating sheet opening part of the upper surface of the semiconductor pellet 1. FIG.

続いて、図３（ｄ）に示すように、半導体ペレット１を、ペレットコーナー部の２〜４か所で保持し、ベース電極部材１３の焼結Ａｇペースト１７０上に位置合わせして搭載し、所定荷重を加えて停止するところまで押し込む。   Subsequently, as shown in FIG. 3 (d), the semiconductor pellet 1 is held at 2 to 4 locations in the pellet corner portion, and aligned and mounted on the sintered Ag paste 170 of the base electrode member 13, Apply the specified load and push until it stops.

次に、図３（ｅ）に示すように、Ａｇめっきしたリード電極部材１５を半導体素子２００の焼結Ａｇペースト１８０上に位置合わせして搭載し、所定荷重を加えて停止するところまで押し込む。このとき、焼結Ａｇペースト１８０はペレット下から押し出されてペレット周辺で盛り上がりつつ周辺に流れ出し、リード電極部材１５の接合用ヘッド１６下から押し出された焼結Ａｇペースト１７０も同様にヘッド周辺で盛り上がりつつ周辺に流れ出す。押し出される焼結Ａｇペーストの量が多い位置は各辺の中央部付近で、コーナー部から押し出される焼結Ａｇペーストの量は少ない。これは、粘性のある流動体の拡がり方が同心円状となるためである。また、固形の金属粒子比率が高いと、所定荷重で押し込んだときに金属粒子が互いに接触した状態になって流動性が低下し、それ以上は押し込めない状態になる。   Next, as shown in FIG. 3 (e), the Ag-plated lead electrode member 15 is positioned and mounted on the sintered Ag paste 180 of the semiconductor element 200, and is pushed in until a predetermined load is applied. At this time, the sintered Ag paste 180 is extruded from the bottom of the pellet and swells around the pellet and flows out to the periphery, and the sintered Ag paste 170 extruded from under the bonding head 16 of the lead electrode member 15 similarly swells around the head. While flowing around. The position where the amount of the extruded Ag paste to be extruded is large is near the center portion of each side, and the amount of the sintered Ag paste extruded from the corner portion is small. This is because the viscous fluid spreads concentrically. Further, when the ratio of solid metal particles is high, the metal particles come into contact with each other when they are pushed in with a predetermined load, the fluidity is lowered, and no further pushing is possible.

この組立て部材を大気雰囲気中で無加圧かつ２００〜３００℃／０.２〜３.０ｈの条件で加熱処理を加え、焼結接合して一体化する。すると、図３（ｆ）に示すような状態になる。   The assembly member is subjected to heat treatment under pressureless conditions of 200 to 300 ° C./0.2 to 3.0 hours in an air atmosphere, and sintered and integrated. Then, a state as shown in FIG.

次に、図３（ｇ）に示すように、ベース電極部材１３とリード電極部材１５の一部を含む接合用ヘッド１６全体に、金属と接着性に優れるイミド系、アミド系、アミドイミド系樹脂いずれかを有機溶剤で低粘度化した液状樹脂を薄く塗布し、加熱硬化処理して有機皮膜１９として固着させる。有機皮膜１９で半導体ペレット１や、当該半導体ペレット１と接合している接合用ヘッド１６、台座１４及び焼結Ａｇの剥離を防止することが可能となる。さらにこのとき、硬化レベルは１００％ではなく５０〜９０％程度の硬化状態とすることによって、後述するトランスファーモールドをする際に、有機皮膜１９とエポキシ樹脂２０の接合をより高められるため、半導体ペレット１と接合用ヘッド１６、半導体ペレット１と台座１４との接合信頼性が向上する。   Next, as shown in FIG. 3G, any of imide-based, amide-based, and amide-imide-based resins excellent in metal and adhesiveness is formed on the entire bonding head 16 including a part of the base electrode member 13 and the lead electrode member 15. A liquid resin whose viscosity is reduced with an organic solvent is thinly applied and heat-cured to fix it as an organic film 19. The organic coating 19 can prevent the semiconductor pellet 1 and the bonding head 16, the base 14, and the sintered Ag that are bonded to the semiconductor pellet 1 from being peeled off. Further, at this time, by setting the curing level to about 50 to 90% instead of 100%, the bonding between the organic film 19 and the epoxy resin 20 can be further enhanced during the transfer molding described later. 1 and the bonding head 16 and the bonding reliability between the semiconductor pellet 1 and the pedestal 14 are improved.

図３（ｈ）は、有機皮膜１９を形成した状態で、当該有機皮膜１９を覆った状態でフィラー含有のエポキシ封止樹脂２０をトランスファーモールドした様子を示したものである。このとき、エポキシ樹脂２０を加熱して硬化処理が、この加熱の際に、有機皮膜１９の未硬化分が完全に硬化する。なお、製造工程中、エポキシ樹脂２０が硬化するとき、焼結Ａｇ１７、１８にクラックが入ったり、剥離したりする危険性が最も高い。しかし、本実施例に示すようにベース電極部材１３に設けられた台座１４を逆台形形状にすることにより、エポキシ樹脂２０が硬化する際の圧縮応力が、ダイオードパッケージ３００の中心部方向にかけることができる。したがって、本来剥離やクラックを生じさせる原因となる樹脂が硬化する際の応力を、締め付け応力として利用することができるため、接合信頼性の高いダイオードパッケージ３００を作成することが可能となる。   FIG. 3 (h) shows a state in which the epoxy sealing resin 20 containing filler is transfer molded in a state where the organic film 19 is formed and the organic film 19 is covered. At this time, the epoxy resin 20 is heated and cured, and the uncured portion of the organic film 19 is completely cured during the heating. In addition, when the epoxy resin 20 hardens | cures during a manufacturing process, the danger that a crack will enter into sintering Ag17 and 18 or peels is the highest. However, as shown in the present embodiment, the pedestal 14 provided on the base electrode member 13 has an inverted trapezoidal shape, so that the compressive stress when the epoxy resin 20 is cured is applied toward the center of the diode package 300. Can do. Therefore, since the stress when the resin that originally causes peeling and cracking is cured can be used as the fastening stress, the diode package 300 with high bonding reliability can be produced.

本実施形態によれば、半導体ペレット１のパターン形成面に電極サイズより小さい開口部を有し外形が辺の領域でペレットサイズより大きい有機絶縁シート７を接着して空間遮蔽物を形成したことにより、半導体ペレット１の上下電極を上下の電極部材に焼結Ａｇペーストで接合する場合に、接合層を厚くするため多量の焼結Ａｇペーストを供給して接合する場合においても、上下電極間が焼結Ａｇで短絡して電気特性不良を発生するということが少なくなり、組立歩留まりの高い鉛フリーの半導体装置とその製造方法を提供できる。   According to the present embodiment, the space shielding material is formed by bonding the organic insulating sheet 7 having an opening smaller than the electrode size on the pattern forming surface of the semiconductor pellet 1 and having an outer shape larger than the pellet size in the side region. Even when the upper and lower electrodes of the semiconductor pellet 1 are joined to the upper and lower electrode members with the sintered Ag paste, even when a large amount of the sintered Ag paste is supplied and joined to increase the thickness of the joining layer, the upper and lower electrodes are sintered. It is possible to provide a lead-free semiconductor device having a high assembly yield and a method for manufacturing the same, because the occurrence of a short circuit in Ag and the occurrence of defective electrical characteristics are reduced.

また本実施形態によれば、逆台形形状の台座１４に半導体ペレット１を搭載し、半導体ペレット１を上下の電極部材に焼結Ａｇペースト１７０、１８０で接合した構造体に対して、焼結Ａｇ接合部１７、１８周辺の領域に金属と接着性に優れる有機皮膜１９を形成し、その上から熱硬化性の封止樹脂をモールドした構造としたことにより、封止樹脂の圧縮応力をうまく利用できるため、高湿度環境や高温環境に繰り返し曝されても封止樹脂と下地の構造体とが剥離することが無くなる。また、封止樹脂によって長期に渡って焼結Ａｇ接合部に圧縮力を加え続けられるので、焼結Ａｇ接合部に部材の熱膨張差に起因した熱応力が加わってもクラック等の劣化が生じることが少なくなり、接合信頼性の高い鉛フリーの半導体装置を提供することができる。   According to the present embodiment, the semiconductor pellet 1 is mounted on the inverted trapezoidal pedestal 14, and the sintered Ag is bonded to the upper and lower electrode members with the sintered Ag pastes 170 and 180. The organic film 19 having excellent adhesion to the metal is formed in the area around the joints 17 and 18, and a thermosetting sealing resin is molded on the organic film 19, thereby making good use of the compressive stress of the sealing resin. Therefore, the sealing resin and the underlying structure are not peeled even when repeatedly exposed to a high humidity environment or a high temperature environment. In addition, since the compressive force can be continuously applied to the sintered Ag joint by the sealing resin, deterioration such as cracks occurs even if thermal stress due to the thermal expansion difference of the member is applied to the sintered Ag joint. Therefore, a lead-free semiconductor device with high bonding reliability can be provided.

《第二の実施形態》
図４は、本発明にかかる第二の実施形態によるダイオードパッケージ４００の断面構造を示したものである。なお、第一の実施形態で使用しているものと同じものには、第一の実施形態と同じ図面番号を用いている。 << Second Embodiment >>
FIG. 4 shows a cross-sectional structure of a diode package 400 according to the second embodiment of the present invention. In addition, the same drawing number as 1st embodiment is used for the same thing as what is used in 1st embodiment.

図４において、Ｃｕのベース電極部材１３とリード電極部材１５には、全面に約５μｍ厚のＡｇめっきを施している。ベース電極部材１３の台座１４は逆台形に加工されており、リード電極部材１５先端の接合用ヘッド１６は、半導体ペレット１の上側の電極より小さいサイズに加工されている。半導体ペレット１の裏面は下側のポーラスな焼結Ａｇ１７を介してベース電極部材１３の台座１４に金属接合されている。焼結Ａｇ１７は、半導体ペレットの側面まで回り込んでいるが、半導体ペレットの上面の高さを超えてはいない。半導体ペレットの上側の電極はポーラスな焼結Ａｇ１７によってリード電極部材１５の接合用ヘッド１６と金属接合されている。焼結Ａｇ１８は、上側中空では電極サイズより横に拡がっている箇所があるが、半導体ペレット１と接しているのは電極領域内に限られている。   In FIG. 4, the Cu base electrode member 13 and the lead electrode member 15 are subjected to Ag plating with a thickness of about 5 μm on the entire surface. The base 14 of the base electrode member 13 is processed into an inverted trapezoid, and the bonding head 16 at the tip of the lead electrode member 15 is processed to a size smaller than the upper electrode of the semiconductor pellet 1. The back surface of the semiconductor pellet 1 is metal-bonded to the base 14 of the base electrode member 13 through the lower porous Ag 17. Sintered Ag17 extends to the side surface of the semiconductor pellet, but does not exceed the height of the upper surface of the semiconductor pellet. The upper electrode of the semiconductor pellet is metal bonded to the bonding head 16 of the lead electrode member 15 by porous sintered Ag 17. In the upper hollow, the sintered Ag 18 has a portion extending laterally from the electrode size, but the contact with the semiconductor pellet 1 is limited to the electrode region.

第一の実施形態と異なる点は、図１と同様の有機絶縁シート１２を半導体ペレット１に接着した状態で接合し、接合後に半導体ペレット１から有機絶縁シート１２を除去して、有機皮膜１９を形成している点である。   The difference from the first embodiment is that an organic insulating sheet 12 similar to that in FIG. 1 is bonded to the semiconductor pellet 1 and bonded, and after the bonding, the organic insulating sheet 12 is removed from the semiconductor pellet 1 to form an organic film 19. It is a point that is formed.

本実施形態のように、接合後に半導体ペレット１から有機絶縁シート１２を除去することによって、第一の実施形態で記載した効果のほかに、有機絶縁シート１２の張り出しによる封止樹脂の切り欠け形状を無くすことができる。そのため上下方向の引張に対する封止樹脂の変形が小さくなりかつ破断荷重が増加するため、焼結Ａｇ１７、１８接合部により高い圧縮力を付与することができてダイオードパッケージ４００の熱疲労寿命を延ばすことが可能となる。   As in this embodiment, by removing the organic insulating sheet 12 from the semiconductor pellet 1 after bonding, in addition to the effects described in the first embodiment, the notch shape of the sealing resin due to the overhang of the organic insulating sheet 12 Can be eliminated. Therefore, since the deformation of the sealing resin with respect to the tensile force in the vertical direction is reduced and the breaking load is increased, a high compressive force can be applied to the sintered Ag17 and 18 joints, thereby extending the thermal fatigue life of the diode package 400. Is possible.

《第三の実施形態》
図５は、本発明にかかる第三の実施形態によるダイオードパッケージ５００の断面構造を示したものである。なお、第一の実施形態で使用しているものと同じものには、第一の実施形態と同じ図面番号を用いている。 << Third embodiment >>
FIG. 5 shows a cross-sectional structure of a diode package 500 according to the third embodiment of the present invention. In addition, the same drawing number as 1st embodiment is used for the same thing as what is used in 1st embodiment.

図５において、Ｃｕのベース電極部材１３とリード電極部材１５には、全面に約３μｍ厚のＡｇめっきを施している。また、ベース電極部材１３の台座１４は逆台形に加工されている。   In FIG. 5, the Cu base electrode member 13 and the lead electrode member 15 are subjected to Ag plating with a thickness of about 3 μm on the entire surface. Further, the base 14 of the base electrode member 13 is processed into an inverted trapezoid.

第一の実施形態と異なる第一の点は、半導体ペレット１と同等サイズで厚さの厚い絶縁遮蔽体１１２が、半導体ペレット１に形成されている点である。絶縁遮蔽体１１２は、表面を熱酸化したＳｉまたはコストの安いアルミナセラミックから成る。接着は２００℃以上の耐熱性がある粘着剤で行っている。   The first point different from the first embodiment is that an insulating shield 112 having the same size and thickness as the semiconductor pellet 1 is formed on the semiconductor pellet 1. The insulating shield 112 is made of Si whose surface is thermally oxidized or low-cost alumina ceramic. Adhesion is performed with an adhesive having heat resistance of 200 ° C. or higher.

本実施形態の絶縁遮蔽体１１２の高さを高くするという構成によって、上下の焼結Ａｇ１７、１８の短絡を防止しながら、焼結Ａｇ接合層の厚さをより高くすることが可能となり、接合部に発生する熱応力を低減して熱疲労寿命を大幅に延ばすことができる。   The configuration of increasing the height of the insulating shield 112 of the present embodiment makes it possible to increase the thickness of the sintered Ag bonding layer while preventing the upper and lower sintered Ags 17 and 18 from being short-circuited. The thermal stress generated in the part can be reduced and the thermal fatigue life can be greatly extended.

《第四の実施形態》
図６（ａ）及び（ｂ）は、本発明にかかる半導体ペレット２０１の平面及び断面構造を示したものである。図６（ａ）において、半導体基板２１の上部にはトランジスター素子が形成されており、ＳｉＯ2の絶縁膜２５とポリイミドのパッシベーション膜２８によって遮断された主電極と制御電極の２つの電極が形成されている。主電極は素子とオーミックコンタクトを取るためのＡｌ電極膜２３と、その上に形成された焼結Ａｇの接合性を良くするＮｉ／Ａｕ電極膜２６から成り、制御電極も同様にＡｌ電極膜２４とＮｉ／Ａｕ電極膜２７から成る。半導体ペレットの上面には、主電極及び制御電極のサイズより小さい開口部４８、４９を有し、外形がペレットサイズより大きく加工されたポリイミドやポリアミドイミドの絶縁シート２９がアクリル系またはシリコーン系の粘着剤３０によって接着されている。 << Fourth Embodiment >>
FIGS. 6A and 6B show the planar and cross-sectional structure of the semiconductor pellet 201 according to the present invention. 6A, a transistor element is formed on an upper portion of a semiconductor substrate 21, and two electrodes, a main electrode and a control electrode, which are blocked by an insulating film 25 made of SiO 2 and a passivation film 28 made of polyimide, are formed. ing. The main electrode is composed of an Al electrode film 23 for making ohmic contact with the element and a Ni / Au electrode film 26 for improving the bonding property of the sintered Ag formed thereon, and the control electrode is similarly formed of the Al electrode film 24. And a Ni / Au electrode film 27. An insulating sheet 29 of polyimide or polyamideimide having openings 48 and 49 smaller than the size of the main electrode and the control electrode on the upper surface of the semiconductor pellet and whose outer shape is processed to be larger than the pellet size is an acrylic or silicone adhesive. Bonded by the agent 30.

図７は、図６に示した、絶縁シート２９を張り付けた半導体ペレット２０１を用いて組み立てた本発明によるトランジスターパッケージ６００の一実施例を示す。図において、Ｃｕのダイパッド３８上のペレット接合領域には約５μｍ厚さのＡｇめっき膜３９が形成され、その上に半導体基板２１の裏面電極２２がポーラスな焼結Ａｇ４３によって接合されている。Ｃｕの主電極リード４０には主電極３３と接合する領域に約５μｍ厚のＡｇめっき膜４１が施されてポーラスな焼結Ａｇ４４によって接合されている。半導体ペレット２０１の上面に接着された絶縁シート２９は、ダイパッド側の焼結Ａｇがペレット上面に回り込む現象を防ぎ、同時に主電極上の焼結Ａｇが流れ出して制御電極と短絡する現象を防いでいる。さらに、当該絶縁シート２９を有することによって、半導体ペレット２０１の側面部まで焼結Ａｇで覆うことが可能になるため、半導体素子２０２とダイパッド３８との接合強度を十分確保できるため、接合信頼性が向上した半導体装置を提供することが可能となる。   FIG. 7 shows an embodiment of the transistor package 600 according to the present invention assembled by using the semiconductor pellet 201 with the insulating sheet 29 attached thereto shown in FIG. In the figure, an Ag plating film 39 having a thickness of about 5 μm is formed in the pellet bonding region on the Cu die pad 38, and the back electrode 22 of the semiconductor substrate 21 is bonded thereto by porous sintered Ag 43. The Cu main electrode lead 40 is provided with an Ag plating film 41 having a thickness of about 5 μm in a region to be bonded to the main electrode 33 and bonded by porous sintered Ag 44. The insulating sheet 29 adhered to the upper surface of the semiconductor pellet 201 prevents the phenomenon that the sintered Ag on the die pad side wraps around the upper surface of the pellet, and at the same time prevents the phenomenon that the sintered Ag on the main electrode flows out and short-circuits with the control electrode. . Furthermore, since the insulating sheet 29 is provided, it is possible to cover the side surface portion of the semiconductor pellet 201 with the sintered Ag. Therefore, the bonding strength between the semiconductor element 202 and the die pad 38 can be sufficiently ensured, so that the bonding reliability is high. An improved semiconductor device can be provided.

Ｃｕの制御電極リード４２は、Ａｌワイヤ４５で半導体基板２１上の制御電極３４と電気的に接続されている。ダイパッド３８や主電極リード４０を含めて焼結Ａｇで接合した領域には金属と接着性に優れた有機皮膜４６が形成されており、半導体素子２０２と焼結Ａｇ接合部とＡｌワイヤ４５の全体及びダイパッド３８と主電極リードと制御電極リード４２の一部を覆うようにシリカフィラーを混入した熱硬化性のエポキシ樹脂４７で封止している。   The Cu control electrode lead 42 is electrically connected to the control electrode 34 on the semiconductor substrate 21 by an Al wire 45. An organic film 46 having excellent adhesion to the metal is formed in a region bonded with sintered Ag including the die pad 38 and the main electrode lead 40, and the entire semiconductor element 202, sintered Ag bonded portion, and Al wire 45 are formed. The die pad 38, the main electrode lead, and a part of the control electrode lead 42 are sealed with a thermosetting epoxy resin 47 mixed with silica filler.

本実施例によれば、半導体ペレット２０１の裏面電極２１と主電極を流動性があり樹脂やＳｉにも濡れる焼結Ａｇペーストを使ってダイパッド３８やリード部材と接合しているが、絶縁シート２９を使って焼結Ａｇによる電極間の短絡現象を防ぐことができ、焼結Ａｇの電気及び熱伝導特性が錫や鉛を主体とする半田材料より優れていることから、組立歩留まりが高くかつ電力損失が小さく、高温や高湿度や繰返し温度変動する環境に強い高信頼な鉛フリーの半導体装置を提供できる。また、上述したように、当該絶縁シート２９によって、半導体ペレット２０１の側面部まで焼結Ａｇで覆うことが可能になるため、高温環境下においても、接合信頼性を十分に確保した半導体装置を提供することが可能となる。   According to the present embodiment, the back electrode 21 and the main electrode of the semiconductor pellet 201 are joined to the die pad 38 and the lead member using a sintered Ag paste that is fluid and wets with resin and Si. Can prevent the short-circuit phenomenon between electrodes due to sintered Ag, and the electrical and thermal conductivity characteristics of sintered Ag are superior to those of solder materials mainly composed of tin and lead. It is possible to provide a highly reliable lead-free semiconductor device that has low loss and is resistant to high temperature, high humidity, and repeated temperature fluctuations. In addition, as described above, the insulating sheet 29 can cover the side surface of the semiconductor pellet 201 with the sintered Ag, so that a semiconductor device that sufficiently secures the bonding reliability even in a high temperature environment is provided. It becomes possible to do.

《第五の実施形態》
図８（ａ）及び（ｂ）は、上述した実施形態で説明した半導体素子を実装した半導体装置の一実施形態を示す。図８（ａ）及び（ｂ）において、トランジスター基板５１には裏面電極５２と主電極５４と制御電極５３が形成され、半導体基板５１における主電極５４が形成された面側には、主電極５４と制御電極５３を囲うように絶縁層５５が形成され、トランジスターペレット３０１が構成されている。また、主電極側の半導体基板面には、主電極５３及び制御電極５４部にそれらサイズより小さい開口部が形成され、外形の少なくとも辺の領域が半導体基板サイズより大きい絶縁性のポリイミドからなる絶縁シート５６が接着されている。また、ダイオード基板５７には全面に金属膜が形成された裏面電極５８と周囲に絶縁領域６０を形成したパターン電極５９が形成されてダイオードペレット４０１が構成されており、パターン電極５９側の半導体基板面にはパターン電極５９のサイズより小さい開口部を有し、外形の少なくとも辺の領域が半導体基板サイズより大きい絶縁性のポリイミドからなる絶縁シート６１が接着されている。セラミック基板６２の裏面にはセラミック基板サイズより一回り小さいＣｕパターン６６が形成され、上面には制御電極用と主電極用とベース電極用の３つのＣｕパターン６３、６４、６５が形成され、セラミック配線基板が構成されている。セラミック配線基板の各Ｃｕパターン表面には、無電解Ｎｉ／フラッシュＡｕめっきが施されている。ベース電極用Ｃｕパターン６３、６４、６５にはトランジスターペレット３０１とダイオードペレット４０１がポーラス構造を有する焼結Ａｇ７１、７３で金属接合され、ペレット側面の焼結Ａｇペーストの這い上がりはポリイミドからなる絶縁シート５６、６１で各ペレット上面の高さ以下となるように抑えられている。 << Fifth Embodiment >>
8A and 8B show an embodiment of a semiconductor device in which the semiconductor element described in the above embodiment is mounted. 8A and 8B, a back electrode 52, a main electrode 54, and a control electrode 53 are formed on the transistor substrate 51, and the main electrode 54 is formed on the surface of the semiconductor substrate 51 where the main electrode 54 is formed. An insulating layer 55 is formed so as to surround the control electrode 53, and a transistor pellet 301 is formed. In addition, an opening smaller than these sizes is formed in the main electrode 53 and the control electrode 54 on the surface of the semiconductor substrate on the main electrode side, and at least the side region of the outer shape is made of insulating polyimide larger than the size of the semiconductor substrate. A sheet 56 is adhered. Further, the diode substrate 57 is formed with a back electrode 58 having a metal film formed on the entire surface and a pattern electrode 59 having an insulating region 60 formed around it to form a diode pellet 401. The semiconductor substrate on the pattern electrode 59 side is formed. An insulating sheet 61 made of insulating polyimide having an opening smaller than the size of the pattern electrode 59 on the surface and having at least a side region of the outer shape larger than the size of the semiconductor substrate is bonded. A Cu pattern 66 that is slightly smaller than the size of the ceramic substrate is formed on the back surface of the ceramic substrate 62, and three Cu patterns 63, 64, and 65 for the control electrode, the main electrode, and the base electrode are formed on the top surface. A wiring board is configured. Electroless Ni / flash Au plating is applied to the surface of each Cu pattern of the ceramic wiring board. Transistor pellets 301 and diode pellets 401 are metal-bonded to the base electrode Cu patterns 63, 64, and 65 with sintered Ag 71 and 73 having a porous structure, and the sintered Ag paste on the side surfaces of the pellets is an insulating sheet made of polyimide. 56 and 61 are suppressed to be equal to or less than the height of the upper surface of each pellet.

トランジスターペレット３０１の主電極５４及び、ダイオードペレット４０１のパターン電極５９は、上側に配置されたＡｇめっきリード７０に焼結Ａｇ７２、７４で金属的に接合され、Ａｇめっきリード７０はセラミック配線基板の主電極Ｃｕパターン６４に焼結Ａｇで接合されている。トランジスターペレット３０１の制御電極５３とセラミック配線基板の制御電極Ｃｕパターン６５は、Ａｌボンディングワイヤ７６で接続されている。セラミック配線基板の上面の３つのＣｕパターンには、外部導出用のＣｕリード６７、６８、６９が超音波接合されており、各Ｃｕリード及びセラミック配線基板の一部を除いて全体を熱硬化性の封止樹脂７６でモールドしている。セラミック配線基板の熱膨張率は各板厚を最適化して５〜１０ppmの範囲になるよう調整しており、封止樹脂の熱膨張率は低熱膨張率のフィラーを混ぜて１０〜１７ppmの範囲で調整している。Ａｇめっきリード７０は、低熱膨張の金属繊維あるいは炭素繊維を複合化して面内方向の熱膨張率を１０ppm以下に小さくしたＣｕ板で構成している。焼結Ａｇ接合部は、直径０.５〜２.０μｍのＡｇ粒子を９２.５〜９４.３ｗｔ％含有する焼結Ａｇペーストを無加圧条件で２５０℃に加熱・焼結して形成した組織で、空孔率が３０〜５０vol％の網目状構造となっており、弾性率が１０ＭＰａ以下の物性となっている。また、絶縁シート５６、６１の構成により、トランジスターパッケージ３０１及びダイオードパッケージ４０１の側面部は、上面電極と短絡することなく、それぞれを焼結Ａｇ７１、７３で覆うことが可能となる。そのため、接合信頼性が向上することが可能となる。   The main electrode 54 of the transistor pellet 301 and the pattern electrode 59 of the diode pellet 401 are metallically joined to the Ag plating lead 70 disposed on the upper side with sintered Ag 72 and 74. The Ag plating lead 70 is the main electrode of the ceramic wiring board. The electrode Cu pattern 64 is joined with sintered Ag. The control electrode 53 of the transistor pellet 301 and the control electrode Cu pattern 65 of the ceramic wiring substrate are connected by an Al bonding wire 76. Cu leads 67, 68, and 69 for external lead-out are ultrasonically bonded to the three Cu patterns on the upper surface of the ceramic wiring board, and the whole is thermosetting except a part of each Cu lead and the ceramic wiring board. The sealing resin 76 is used for molding. The thermal expansion coefficient of the ceramic wiring board is adjusted to be in a range of 5 to 10 ppm by optimizing each plate thickness, and the thermal expansion coefficient of the sealing resin is in a range of 10 to 17 ppm by mixing a filler having a low thermal expansion coefficient. It is adjusted. The Ag plating lead 70 is composed of a Cu plate in which a low thermal expansion metal fiber or carbon fiber is combined to reduce the thermal expansion coefficient in the in-plane direction to 10 ppm or less. The sintered Ag joint was formed by heating and sintering a sintered Ag paste containing 92.5 to 94.3 wt% of Ag particles having a diameter of 0.5 to 2.0 μm at 250 ° C. under no pressure condition. The structure has a network structure with a porosity of 30 to 50 vol% and a physical property of an elastic modulus of 10 MPa or less. Further, the side surfaces of the transistor package 301 and the diode package 401 can be covered with the sintered Ag 71 and 73 without being short-circuited with the upper electrode by the configuration of the insulating sheets 56 and 61, respectively. As a result, the bonding reliability can be improved.

以上、本実施形態によれば、トランジスターやダイオードの主電流が流れる電極と配線部材をポーラスな焼結Ａｇによって広い面積で金属接合しているため、接合信頼性向上という効果に加え、モジュール実装部の電力損失を最小限まで小さくすることが可能となり、高効率な半導体装置を提供できる。   As described above, according to the present embodiment, the electrode through which the main current of the transistor and the diode flows and the wiring member are metal-bonded in a wide area by porous sintered Ag. In addition to the effect of improving the bonding reliability, the module mounting portion Power loss can be reduced to a minimum, and a highly efficient semiconductor device can be provided.

《第六の実施形態》
図９は、実施形態１に記載した半導体素子を、ゲルを用いて封止した半導体装置の一実施形態を示す。図９において、熱膨張率を１０ppm以下に下げた放熱板９４と、内部にＮｉめっきＣｕリード９６、９７を埋設した熱可塑性樹脂の筐体９５が接着されてモジュールケースが構成されている。セラミック絶縁基板８４の上下に形成されたＣｕパターン８５、８６、８７から成るセラミック配線基板は、Ｃｕパターン８７を下側として、放熱板９４にＳｎ、Ａｇ、Ｃｕを主要構成元素とする鉛フリーはんだ８１で接合されている。セラミック配線基板のベース電極用Ｃｕパターン８５には、ポリアミドイミドから成る絶縁シート８３が接着された半導体ペレット８１が空孔率２０〜４０vol％のポーラスな焼結Ａｇ８９でダイボンディングされ、半導体ペレット８１の上側の主電極８２と金属リード８８及び金属リード８８と主電極用Ｃｕパターン８６が焼結Ａｇ９０、９２で金属的に接合されている。主電極用Ｃｕパターン８６とＮｉめっきＣｕリード９７はＣｕボンディングワイヤ９９で接続され、ベース電極用Ｃｕパターン８５とＮｉめっきＣｕリード９６はＣｕボンディングワイヤ９８で接続されている。焼結Ａｇで接合した領域は、熱硬化性のエポキシ樹脂９１、９３で部分的にポッティングで封止し、モジュールケース内全体を覆うようにシリコーンゲル１００で覆っている。最終的にはモジュールケースの上部に樹脂製の蓋を被せて、モジュールが完成する。 << Sixth Embodiment >>
FIG. 9 shows an embodiment of a semiconductor device in which the semiconductor element described in Embodiment 1 is sealed with gel. In FIG. 9, a heat sink 94 having a thermal expansion coefficient lowered to 10 ppm or less and a thermoplastic resin casing 95 in which Ni plating Cu leads 96 and 97 are embedded are bonded to form a module case. A ceramic wiring board made of Cu patterns 85, 86 and 87 formed on the upper and lower sides of the ceramic insulating substrate 84 is a lead-free solder having the Cu pattern 87 as a lower side and the heat sink 94 having Sn, Ag and Cu as main constituent elements. 81 is joined. A semiconductor pellet 81 to which an insulating sheet 83 made of polyamideimide is bonded is die-bonded to porous Cu Ag 89 having a porosity of 20 to 40 vol% on the base electrode Cu pattern 85 of the ceramic wiring board. The upper main electrode 82 and the metal lead 88, and the metal lead 88 and the main electrode Cu pattern 86 are joined metallically by sintered Ag 90 and 92. The main electrode Cu pattern 86 and the Ni plated Cu lead 97 are connected by a Cu bonding wire 99, and the base electrode Cu pattern 85 and the Ni plated Cu lead 96 are connected by a Cu bonding wire 98. The region joined by the sintered Ag is partially potted with thermosetting epoxy resins 91 and 93 and covered with the silicone gel 100 so as to cover the entire inside of the module case. Ultimately, the module case is completed by covering the top of the module case with a resin lid.

以上、本実施形態によれば、樹脂のモジュールケースを使い、主にゲルで封止した従来構造のパワーモジュールであっても、接続信頼性が高く、かつ鉛フリーのパワーモジュールを作製でき、低コストで環境に優しい半導体装置を提供できる。   As described above, according to the present embodiment, a power module having a connection reliability is high and a lead-free power module can be manufactured even with a conventional power module using a resin module case and sealed mainly with gel. We can provide environmentally friendly semiconductor devices at low cost.

《第七の実施形態》
図１０は、本実施形態による半導体装置の他の実施例を示す。図１０において、Ｃｕのベース電極部材１２６とリード電極部材１２８には、全面に約３μｍ厚のＡｇめっきを施している。ベース電極部材１２８の台座１２７は逆台形に加工されており、リード電極部材１２８先端の接合用ヘッド１２９は、有機絶縁シート１２５の開口部の中に納まるサイズに加工されている。ダイオードチップ１２１の下面に形成された裏面電極１２２は、下側のポーラスな焼結Ａｇ１３０を介してベース電極部材１２６の台座に金属接合されている。ポーラスな焼結Ａｇ１３０は、ダイオードペレット１２４の側面を這い上がって有機絶縁シート１２５まで達しているが、有機絶縁シート１２５によって、ダイオードペレット１２４の上面電極への焼結Ａｇの回り込みが抑えられている。そのため、半導体装置作成時における上下電極の短絡を、確実に防止することが可能となる。ダイオードペレット１２４の上面のパターン電極１２３は上側のポーラスな焼結Ａｇ１３２によってリード電極部材１２８と金属接合されている。焼結Ａｇ１３２は、有機絶縁シート１２５の開口部からはみ出して有機絶縁シート１２５上に拡がっているが、シート面内から漏れ出すことは無い。 << Seventh Embodiment >>
FIG. 10 shows another example of the semiconductor device according to the present embodiment. In FIG. 10, the Cu base electrode member 126 and the lead electrode member 128 are subjected to Ag plating with a thickness of about 3 μm on the entire surface. The base 127 of the base electrode member 128 is processed into an inverted trapezoid, and the joining head 129 at the tip of the lead electrode member 128 is processed to a size that fits within the opening of the organic insulating sheet 125. The back electrode 122 formed on the lower surface of the diode chip 121 is metal-bonded to the base of the base electrode member 126 through the lower porous Ag 130. The porous sintered Ag 130 scoops up the side surface of the diode pellet 124 and reaches the organic insulating sheet 125, but the organic insulating sheet 125 suppresses the wrapping of the sintered Ag to the upper electrode of the diode pellet 124. . For this reason, it is possible to reliably prevent a short circuit between the upper and lower electrodes when the semiconductor device is formed. The pattern electrode 123 on the upper surface of the diode pellet 124 is metal-bonded to the lead electrode member 128 by the upper porous sintered Ag 132. The sintered Ag 132 protrudes from the opening of the organic insulating sheet 125 and spreads on the organic insulating sheet 125, but does not leak from the sheet surface.

ベース電極部材１２６及びリード電極部材１２８の一部と、ダイオードペレット１２４を含む接合部には金属と接着性に優れるポリイミド樹脂を塗布・硬化処理して有機皮膜１３４を形成している。また、有機皮膜を形成した領域を覆うようにシリカフィラーを混錬した低熱膨張のエポキシ樹脂１３５がモールドされ硬化処理されている。   A part of the base electrode member 126 and the lead electrode member 128 and the joint portion including the diode pellet 124 are coated with a metal and a polyimide resin having excellent adhesiveness to form an organic film 134. Further, a low thermal expansion epoxy resin 135 kneaded with silica filler is molded and cured so as to cover the region where the organic film is formed.

本実施形態が第一の実施形態と異なる点は、上下の焼結Ａｇ１３０、１３２中には、Ｃｕ粒子に約３μｍ厚のＡｇめっきを施した大径サイズの導電性粒子１３１、１３３を１０〜５０ｗｔ％ほど混在させている点である。当該構成によって、接合信頼性を確保しつつ、高価なＡｇペーストの使用量を抑えることが可能となる。   This embodiment is different from the first embodiment in that in the upper and lower sintered Ags 130 and 132, the conductive particles 131 and 133 having large diameters obtained by applying Ag plating of about 3 μm thickness to the Cu particles are 10 to 10. The point is that about 50 wt% is mixed. With this configuration, it is possible to suppress the amount of expensive Ag paste used while ensuring bonding reliability.

本実施形態によれば、焼結Ａｇの中に貴金属でない導電性粒子を混入した構造としたため、高価なＡｇの使用量を少なくして厚い接合層で実装することが可能となり、接合信頼性を確保しつつも、半導体装置の実装コストを低減できる効果がある。   According to the present embodiment, since the sintered Ag has a structure in which conductive particles that are not precious metal are mixed, it is possible to reduce the amount of expensive Ag used for mounting with a thick bonding layer, and to improve the bonding reliability. While securing, there is an effect that the mounting cost of the semiconductor device can be reduced.

《第八の実施形態》
図１１は、本発明による半導体装置の他の実施例を示す。なお、本実施形態の説明において、第七の実施形態と同じ構成については同様の図面番号を用いている。 << Eighth Embodiment >>
FIG. 11 shows another embodiment of the semiconductor device according to the present invention. In the description of the present embodiment, the same drawing numbers are used for the same configurations as those of the seventh embodiment.

図１０において、Ｃｕのベース電極部材１２６とリード電極部材１２８には、全面に約５μｍ厚のＡｇめっきを施している。   In FIG. 10, a Cu base electrode member 126 and a lead electrode member 128 are subjected to Ag plating with a thickness of about 5 μm on the entire surface.

第七の実施形態と異なる点は、半導体ペレット１２４とベース電極部材１２６の台座１２７との間には、熱膨張率が５〜１１ppmの範囲の材料で中央付近に開口部を有する貴金属めっきされた応力緩衝板１４９が配置されている点である。また、応力緩衝板１４９の中央開口部には、接合材のポーラスな焼結Ａｇ１３０が充填されている。   The difference from the seventh embodiment is that the semiconductor pellet 124 and the base 127 of the base electrode member 126 are plated with a noble metal having a thermal expansion coefficient in the range of 5 to 11 ppm and having an opening near the center. The stress buffer plate 149 is disposed. The central opening of the stress buffer plate 149 is filled with porous sintered Ag 130 of the bonding material.

以上、本実施形態によれば、半導体ペレットとベース電極部材の間に低熱膨張部材を挿入して焼結Ａｇの接合厚さを薄くし、低熱膨張部材の内部は電気及び熱伝導性に優れる焼結Ａｇで埋めているので、焼結Ａｇ接合部に発生する熱応力を低減できしかも電気・熱伝導性を高く維持できるので、接合信頼性を確保しつつも電力損失の少ないダイオードパッケージを提供できる。同時に、接合材の融点が高いことから高温信頼性も高くできる。   As described above, according to the present embodiment, the low thermal expansion member is inserted between the semiconductor pellet and the base electrode member to reduce the bonding thickness of the sintered Ag, and the inside of the low thermal expansion member is a ceramic having excellent electrical and thermal conductivity. Since it is filled with the sintered Ag, the thermal stress generated in the sintered Ag junction can be reduced and the electrical and thermal conductivity can be maintained high, so that a diode package with low power loss can be provided while ensuring the junction reliability. . At the same time, since the melting point of the bonding material is high, the high temperature reliability can be improved.

１ 半導体ペレット
７ 有機絶縁シート
１３ ベース電極部材
１４ 台座
１５ リード電極部材
１６ 接合用ヘッド
１７、１８ 焼結Ａｇ
１９ 有機皮膜
２０ エポキシ樹脂
３００ ダイオードパッケージ DESCRIPTION OF SYMBOLS 1 Semiconductor pellet 7 Organic insulating sheet 13 Base electrode member 14 Base 15 Lead electrode member 16 Joining heads 17 and 18 Sintered Ag
19 Organic film 20 Epoxy resin 300 Diode package

Claims (10)

半導体ペレットと、
前記半導体ペレットの一方の面に接着される絶縁シートと、
前記半導体ペレットの他方の面と接合される金属板と、を備える半導体装置であって、
前記絶縁シートは、前記半導体ペレットにおける外周部よりも突出しており、かつ、前記半導体ペレットにおける電極面が露出するように形成され、
前記半導体ペレットの他方の面と、前記金属板とは焼結銀層を介して接続され、
当該焼結銀層は、前記半導体ペレットの他方の面及び側面部を覆っていることを特徴とする半導体装置。 Semiconductor pellets,
An insulating sheet bonded to one surface of the semiconductor pellet;
A metal plate joined to the other surface of the semiconductor pellet,
The insulating sheet protrudes from the outer peripheral portion of the semiconductor pellet, and is formed so that the electrode surface of the semiconductor pellet is exposed,
The other surface of the semiconductor pellet and the metal plate are connected via a sintered silver layer,
The sintered silver layer covers the other surface and side surface portion of the semiconductor pellet . 請求項１に記載の半導体装置において、
前記半導体ペレット、前記絶縁シート、及び前記焼結銀層は、有機皮膜に覆われていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor pellet, the insulating sheet, and the sintered silver layer are covered with an organic film. 請求項１または２に記載の半導体装置において、
前記金属板は、前記半導体ペレットを搭載する台座部を有し、
前記台座部は、前記半導体ペレットを搭載する上面部を有し、
前記上面部の面積は、前記台座部を前記上面部と平行に切断した面の面積よりも大きくなるように構成され、
前記半導体ペレット、前記絶縁シート、前記焼結銀層、及び前記台座部は樹脂で覆われていることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2,
The metal plate has a pedestal portion on which the semiconductor pellet is mounted,
The pedestal portion has an upper surface portion on which the semiconductor pellet is mounted,
An area of the upper surface portion is configured to be larger than an area of a surface obtained by cutting the pedestal portion in parallel with the upper surface portion,
The semiconductor device, wherein the semiconductor pellet, the insulating sheet, the sintered silver layer, and the pedestal portion are covered with a resin. 請求項２に記載の半導体装置において、
前記電極面は、焼結銀を介してリード電極と接続され、
当該リード電極の一部は、前記有機皮膜で覆われた有機皮膜被覆部を有し、かつ当該有機皮膜被覆部を介して前記樹脂に覆われていることを特徴とする半導体装置。 The semiconductor device according to claim 2 ,
The electrode surface is connected to the lead electrode through sintered silver,
A part of the lead electrode has an organic film covering portion covered with the organic film, and is covered with the resin through the organic film covering portion. 請求項１乃至４のいずれかに記載の半導体装置において、
前記焼結銀層は、導電性粒子を含有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
The sintered silver layer contains conductive particles, and is a semiconductor device. 請求項１乃至４のいずれかに記載の半導体装置において、
前記焼結銀層は、応力緩衝板を含有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
The sintered silver layer contains a stress buffer plate. 半導体ペレットと、
前記半導体ペレットにおける外周部よりも突出した絶縁シートと、
前記半導体ペレットを搭載する金属板と、を有する半導体装置の製造方法において、
前記半導体ペレットと前記絶縁シートとを接着する第一の工程と、
前記金属板に焼結銀ペーストを塗布する第二の工程と、
前記第一及び第二の工程の後に、加圧して、前記半導体ペレットを前記金属板に搭載する第三の工程を有することを特徴とする半導体装置の製造方法。 Semiconductor pellets,
An insulating sheet protruding from the outer periphery of the semiconductor pellet;
In a method for manufacturing a semiconductor device having a metal plate on which the semiconductor pellet is mounted,
A first step of bonding the semiconductor pellet and the insulating sheet;
A second step of applying a sintered silver paste to the metal plate;
A method of manufacturing a semiconductor device, comprising a third step of mounting the semiconductor pellet on the metal plate by applying pressure after the first and second steps. 請求項７に記載の半導体装置の製造方法において、
前記金属板は、前記半導体ペレットを搭載する台座部を有し、
前記台座部は、前記半導体ペレットを搭載する上面部を有し、
前記上面部の面積は、前記台座部を前記上面部と平行に切断した面の面積よりも大きくなるように構成されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7,
The metal plate has a pedestal portion on which the semiconductor pellet is mounted,
The pedestal portion has an upper surface portion on which the semiconductor pellet is mounted,
The method of manufacturing a semiconductor device, wherein an area of the upper surface portion is configured to be larger than an area of a surface obtained by cutting the pedestal portion in parallel with the upper surface portion. 請求項７または８に記載の半導体装置の製造方法において、
前記第三の工程の後に、液状樹脂を塗布し、当該液状樹脂を５０〜９０％の硬化状態として有機皮膜を作製する第四の工程を有することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7 or 8,
A method for manufacturing a semiconductor device, comprising: a fourth step of applying an organic resin film after applying the liquid resin and setting the liquid resin in a cured state of 50 to 90% after the third step. 請求項９に記載の半導体装置の製造方法において、
前記第四の工程の後に、前記有機皮膜を覆う封止樹脂でトランスファーモールドする第五の工程を有することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 9,
A method for manufacturing a semiconductor device, comprising a fifth step of performing transfer molding with a sealing resin covering the organic film after the fourth step.
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