JPS5840848A - Insulating type semiconductor device - Google Patents

Insulating type semiconductor device

Info

Publication number
JPS5840848A
JPS5840848A JP56138504A JP13850481A JPS5840848A JP S5840848 A JPS5840848 A JP S5840848A JP 56138504 A JP56138504 A JP 56138504A JP 13850481 A JP13850481 A JP 13850481A JP S5840848 A JPS5840848 A JP S5840848A
Authority
JP
Japan
Prior art keywords
projection
groove
metal substrate
semiconductor device
metallic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56138504A
Other languages
Japanese (ja)
Inventor
Tatsuo Yamazaki
山崎 龍雄
Yoichi Nakajima
中島 羊一
Noritoshi Kotsuji
小辻 宣俊
Ryuichiro Sakai
酒井 隆一郎
Tetsuo Ushiwatari
牛渡 徹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP56138504A priority Critical patent/JPS5840848A/en
Publication of JPS5840848A publication Critical patent/JPS5840848A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the reliability of an insulating type semiconductor device, providing projections approximately parallel with the main surface of a substrate in a groove of a case adhesion part provided on a metallic substrate. CONSTITUTION:A projection 17 is provided in a groove 16 of a metallic substrate 2. In such a constitution, cracks do not generate on the end part of an insulating plate 4 resulting in the prevention of the thermal fatigue of a solder 3. Therefore, the reliability of insulating withstand voltage and thermal fatigue withstand strength increases. Further, since a resin 13 on injection flows in the lower side of the projection 17, and the creepage distance to a chip 10 is long, out air interruption improves resulting in the imcrease of resisting force against tensile force from the outside. The metallic substrate 2 is pressed by a male mold 17a, a projection 18b is formed simultaneously with a mount hole 19 and the groove 16, and further the projection 18b is deformed by pressing by a male mold 17b, and thus the projection can be easily formed.

Description

【発明の詳細な説明】 不発1jllは、絶縁型半導体装置における金属基板の
構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Misfire 1jll relates to the structure of a metal substrate in an insulated semiconductor device.

一般に、絶縁型半導体装置は、半導体チップ、該半導体
チップに通電するためのq!r種端子、通電時に半導体
チップで発生する熱損失を外部放熱フィンへ伝えるとと
もに、半纏体チップを支持するための金属基板、及び該
金属基板と、前記半導体チップ、各柚xiω子とを電気
的に絶縁するための熱伝導率の大きなAt t Os 
等の絶縁板とを、ろう付は等により一体化し、さらに一
体にろう付された半導体チップ等を内部に収納するよう
なケースを金属基板の周囲に接着し、外部雰囲気等から
゛電気的機械的に保護するため、前記ケース内部に、エ
ポキシレジン等の樹脂を充填するプロセスを経て製作さ
れる。以下、図面を用いて説明する。
Generally, an insulated semiconductor device includes a semiconductor chip and q! for energizing the semiconductor chip. R type terminal, a metal substrate for transmitting the heat loss generated in the semiconductor chip when energized to the external heat dissipation fin, and supporting the semi-integrated chip, and electrically connecting the metal substrate, the semiconductor chip, and each yuzu xiω. At t Os with high thermal conductivity to insulate
The insulating plates such as the above are integrated by brazing, etc., and a case that houses the integrally brazed semiconductor chips etc. is glued around the metal substrate, and electrical and mechanical parts are protected from the external atmosphere. The case is manufactured through a process in which the inside of the case is filled with resin such as epoxy resin for protection. This will be explained below using the drawings.

第1図に従来の絶縁型半導体装置の一例を示す。FIG. 1 shows an example of a conventional insulated semiconductor device.

第1図において、半導体チップ10の」二面には、ろう
材ita、iibによって内リード8.9がろう付けさ
れ、内リード8,9はさらにろう拐7C97bを介して
、カソード′電極6c、ゲーI・電極6bに接続されて
いる。半纏体チップ10の下面はろう材7aを介して、
アノード電極6aに接着されている。更にカソード電極
6c、アノード電極5a、ゲート電極61)は、ろう材
5c。
In FIG. 1, inner leads 8.9 are brazed to two surfaces of the semiconductor chip 10 using brazing materials ita and iib, and the inner leads 8 and 9 are further connected to the cathode electrode 6c and It is connected to the gate I electrode 6b. The lower surface of the semi-integrated chip 10 is connected via the brazing material 7a,
It is bonded to the anode electrode 6a. Further, the cathode electrode 6c, anode electrode 5a, and gate electrode 61) are made of a brazing material 5c.

5a、5bを介してセラミック等の絶縁板4に接着保持
されており、絶縁板4はろう材3を介して、金属基板2
に接着されている。なお、絶縁板4のろう付は部にはメ
タライズ処理が施されている。
The insulating plate 4 is bonded to the metal substrate 2 via the brazing material 3 via the insulating plate 4 made of ceramic or the like.
is glued to. Note that the brazing portion of the insulating plate 4 is metallized.

ケース12は、金属基板2上の溝16に接着剤により接
着され、ケース内部はレジン13で充満されている。
The case 12 is bonded to the groove 16 on the metal substrate 2 with an adhesive, and the inside of the case is filled with resin 13.

このような従来1イク造では、レジン13と、金属基板
2との線膨張係数の差が大きい為、外部よりヒートサイ
クル等を刀1えると、レジン13の金属基板2界而での
剥離が生じ湿気等が外部より浸入しやすくなり、遮断性
が劣化する。それゆえ、絶縁板4にオーバーハング部1
5を設け、そこにレジン13をくい込ませることにより
遮断性を確保することが考えられる。オーバーハング部
15は、ろう拐3よりも周囲に突き出ておシ、そのため
沿面長が大きくなるので上述の効果が期待される。
In such a conventional one-layer structure, there is a large difference in linear expansion coefficient between the resin 13 and the metal substrate 2, so if heat cycles or the like are applied from the outside, the resin 13 may peel off between the metal substrate 2. This makes it easier for moisture, etc. to enter from the outside, and the barrier properties deteriorate. Therefore, there is an overhang 1 on the insulating plate 4.
5 and inserting the resin 13 therein may be considered to ensure the barrier property. The overhang portion 15 protrudes further to the periphery than the soldering hole 3, and therefore has a larger creepage length, so that the above-mentioned effect can be expected.

しかしこうすると、レジ/13と絶縁板4との線膨張係
数の差は、金属基板とのそれよりも更に大きい為、外部
からのヒートサイクルによる熱応力により絶縁板端面に
クラックが生じやすく、絶縁耐圧を劣化させる恐れがあ
る。また、絶縁板4と金属基板2との間のろう材3が、
オーバー・・ノブ部I5の直下のレジンの熱膨張によっ
て絶縁板4が上向きのカケ受けることによりクラック及
び剥離が生じる恐れがあった。以上のように、従来例は
、絶縁耐圧、熱疲労耐量及び外気との遮断性に対し著し
く信頼性が低いという欠点があった。
However, if this is done, the difference in linear expansion coefficient between the register 13 and the insulating plate 4 is even larger than that with the metal substrate, so cracks are likely to occur on the end face of the insulating plate due to thermal stress due to external heat cycles. There is a risk of deteriorating the withstand voltage. Furthermore, the brazing material 3 between the insulating plate 4 and the metal substrate 2 is
There was a risk that cracks and peeling would occur due to the insulating plate 4 being chipped upward due to thermal expansion of the resin directly under the over-knob portion I5. As described above, the conventional example has the disadvantage of extremely low reliability in terms of dielectric strength, thermal fatigue resistance, and isolation from the outside air.

本発明の目的は、従来例の欠点を改善し、絶縁耐圧、′
熱疲労耐量及び外気の遮断性に配れた絶縁型半導体装置
を提供することにある。
The purpose of the present invention is to improve the drawbacks of the conventional example, and to improve the dielectric strength and
An object of the present invention is to provide an insulated semiconductor device with good thermal fatigue resistance and external air insulation.

本発明の特徴は絶縁型半導体装置において、金属基板に
施したケース接着部である11fの内部に、金属基板の
主面とほぼ平行となるような突起を設けたことにある。
A feature of the present invention is that, in an insulated semiconductor device, a protrusion that is substantially parallel to the main surface of the metal substrate is provided inside the case bonding portion 11f formed on the metal substrate.

以下本発明の実施例を図面を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.

第2図は、本発明の一実施例の要部断面である。FIG. 2 is a sectional view of a main part of an embodiment of the present invention.

第2図に示した以外の部分は第1図と同等であるので、
図示を略しである。絶縁板4のオーバーハング部を除去
し、かわりに金属基板2の溝16の内部に突起部17を
設けている点に!時機がある。
The parts other than those shown in Figure 2 are the same as in Figure 1, so
Illustrations are omitted. The overhang portion of the insulating plate 4 has been removed and a protrusion 17 is provided inside the groove 16 of the metal substrate 2 instead! There is a time.

このことにより、絶縁板4端部にクラック音生じること
がなくなり、またろう材3の熱疲労をも防止できる。そ
の結果、絶縁耐圧、熱疲労耐量の信頼性も向」二できる
。さらにレジン13が、注入時に溝の突起部17の下1
116にまわり込み、外気から半導体チップ10までの
沿面距離を長くできるため、外気の遮断性も向上できる
。なお、外気がレジンと他部材のすきまを浸透するに要
する時間は、沿面距離の4乗に比例すると言われている
。また電極等に加わる外部からの引張力に対しても、突
起部17によって抵抗力が増大する。
This eliminates the occurrence of cracking sounds at the ends of the insulating plate 4, and also prevents thermal fatigue of the brazing filler metal 3. As a result, the reliability of dielectric strength and thermal fatigue resistance can be improved. Furthermore, the resin 13 is applied to the bottom 1 of the protrusion 17 of the groove during injection.
116, and the creepage distance from the outside air to the semiconductor chip 10 can be increased, so that the insulation against outside air can also be improved. It is said that the time required for outside air to penetrate the gap between the resin and other members is proportional to the fourth power of the creepage distance. Furthermore, the protrusion 17 increases the resistance against external tensile force applied to the electrodes and the like.

」二連の実施例の金属基板は、プレス加工により容易に
製作できる。第3図、第4図に突起部金有する金属基板
2の製作フ頴セスの一実施例を示す。
The metal substrates of the two series of embodiments can be easily manufactured by press working. FIGS. 3 and 4 show an embodiment of the manufacturing process for the metal substrate 2 having protrusions.

第3図は、金鳩基板2に第1のプレス雄417aを打ち
終えたものを示す。プレス加工によシ、金属基板2を外
部支持材へ固定するためのネジ穴19及び金属基板の4
16が形成されると同時に、プレス雄型17aに設けた
型のにげ部18aに沿って突起部18I)ができる。更
に第5図に示すように、第2のプレス雄型17bを金属
基板2にプレスすると、突起部18bが変形して屑の突
起部17が形成される。
FIG. 3 shows the first male press 417a having been pressed onto the metal dove board 2. Through press working, screw holes 19 for fixing the metal substrate 2 to an external support material and 4 of the metal substrate are formed.
At the same time as the mold 16 is formed, a protrusion 18I) is formed along the stub 18a of the male press mold 17a. Furthermore, as shown in FIG. 5, when the second press male die 17b is pressed against the metal substrate 2, the protrusion 18b is deformed and a scrap protrusion 17 is formed.

第5図、第6図、第7図に本発明の他の実施例の要部を
示す。第5図の実施例の特徴は溝16の断面が台形状と
なっている点である。このように金属基板の箭の断面形
状が台形であっても一向にさしつかえない。
FIG. 5, FIG. 6, and FIG. 7 show main parts of other embodiments of the present invention. A feature of the embodiment shown in FIG. 5 is that the groove 16 has a trapezoidal cross section. In this way, even if the cross-sectional shape of the metal substrate is trapezoidal, there is no problem at all.

第゛6図に示すように、ケースを用いずに、レジン13
をインジェクションあるいはトランスファモールド法に
より形成することにより装置を製作しても、特性上なん
ら変化はない。
As shown in Figure 6, the resin 13 is
Even if the device is manufactured by injection or transfer molding, there will be no change in characteristics.

第7図は、第6図の応用例を示す。第7図では、突起部
17が、蒋16の外周」りに位置している。
FIG. 7 shows an example of application of FIG. In FIG. 7, the protrusion 17 is located near the outer periphery of the chimney 16.

このように、溝の突起部の位置は、荷の内部ならどこで
もかまわない。また% iFjの突起部は、清音体にβ
つても、屑の一部だけにあっても一向にさしつかえない
In this way, the protrusion of the groove can be located anywhere inside the load. In addition, the protrusion of % iFj is β
However, even if it is only part of the debris, there is no problem at all.

上述の実施例では個別半導体装置につ、いて説明したが
、本発明はモジュール等混成ICにも適用できる。
Although the above embodiments have been described with reference to individual semiconductor devices, the present invention can also be applied to hybrid ICs such as modules.

以上詳述したように、本発明によれば、絶縁耐圧、熱疲
労耐量、及び外気との遮断性にすぐれた絶縁型半導体装
置が容易に提供できるという効果がある。
As detailed above, according to the present invention, an insulated semiconductor device having excellent dielectric strength, thermal fatigue resistance, and isolation from outside air can be easily provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の絶縁型半導体装置の一例の断面図、第
2図は、本発明の一実施plの絶縁型半導体装置の断面
図、第3図、第4図は、本発明の実施例で用いた金属基
板の製作工程におけるブレス雄型と金属基板の断面図、
第5図、第6図、及び第7図は、本発明の他の実施例の
絶縁型半導体装1斤の1新面図である。 2・・・金属基板、3・・・ろう材、4・・・絶縁板、
12・・・第1 図 半2図
FIG. 1 is a sectional view of an example of a conventional insulated semiconductor device, FIG. 2 is a sectional view of an insulated semiconductor device according to an embodiment of the present invention, and FIGS. 3 and 4 are sectional views of an example of a conventional insulated semiconductor device. A cross-sectional view of the male bracelet and the metal substrate in the manufacturing process of the metal substrate used in the example,
FIG. 5, FIG. 6, and FIG. 7 are new views of one loaf of an insulated semiconductor device according to another embodiment of the present invention. 2... Metal substrate, 3... Brazing material, 4... Insulating plate,
12...1st figure half 2 figures

Claims (1)

【特許請求の範囲】[Claims] ■、謔属基板の一生面の一部に、前記金属基板と電気的
に絶縁された少なくとも1つの半導体チップ、及び該半
導体チップに′電気的に接説された電極リードをイテし
、前6C半導体チップと゛電極リードの少なくとも一部
をレジンにより被覆した構造をイイするものにおいて、
前記金属基板の周縁部に溝を側し、かつ溝の内部に溝に
対し突出する突起を設けたことを性徴とする絶縁型半導
体装置。
(2) At least one semiconductor chip electrically insulated from the metal substrate and an electrode lead electrically connected to the semiconductor chip are placed on a part of the surface of the metal substrate; In a structure in which the semiconductor chip and at least part of the electrode leads are coated with resin,
An insulated semiconductor device characterized by having a groove on the peripheral edge of the metal substrate and a protrusion inside the groove that protrudes from the groove.
JP56138504A 1981-09-04 1981-09-04 Insulating type semiconductor device Pending JPS5840848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56138504A JPS5840848A (en) 1981-09-04 1981-09-04 Insulating type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56138504A JPS5840848A (en) 1981-09-04 1981-09-04 Insulating type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5840848A true JPS5840848A (en) 1983-03-09

Family

ID=15223668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56138504A Pending JPS5840848A (en) 1981-09-04 1981-09-04 Insulating type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5840848A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065553A (en) * 1984-04-10 1985-04-15 Sanyo Electric Co Ltd Hybrid integrated circuit
US5923231A (en) * 1994-08-05 1999-07-13 Kinseki Limited Surface acoustic wave device with an electrode insulating film and method for fabricating the same
US6767767B2 (en) * 2001-08-31 2004-07-27 Renesas Technology Corp. Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate
JP2006310381A (en) * 2005-04-26 2006-11-09 Toyota Industries Corp Electronic apparatus
JP2013098266A (en) * 2011-10-31 2013-05-20 Hitachi Ltd Semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065553A (en) * 1984-04-10 1985-04-15 Sanyo Electric Co Ltd Hybrid integrated circuit
JPH0410742B2 (en) * 1984-04-10 1992-02-26
US5923231A (en) * 1994-08-05 1999-07-13 Kinseki Limited Surface acoustic wave device with an electrode insulating film and method for fabricating the same
US6767767B2 (en) * 2001-08-31 2004-07-27 Renesas Technology Corp. Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate
JP2006310381A (en) * 2005-04-26 2006-11-09 Toyota Industries Corp Electronic apparatus
JP2013098266A (en) * 2011-10-31 2013-05-20 Hitachi Ltd Semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US6881071B2 (en) Power semiconductor module with pressure contact means
US7944045B2 (en) Semiconductor module molded by resin with heat radiation plate opened outside from mold
KR960016239B1 (en) Semiconductor device
US4670771A (en) Rectifier module
KR100324333B1 (en) Stacked package and fabricating method thereof
US6867484B2 (en) Semiconductor device
JP3316714B2 (en) Semiconductor device
EP1104025B1 (en) Semiconductor device
US5767576A (en) Semiconductor module with snap line
WO1995028740A1 (en) Electronic package having improved wire bonding capability
US12041755B2 (en) Power semiconductor module arrangement and method for producing a power semiconductor module arrangement
US5698898A (en) Semiconductor apparatus with a multiple element electrode structure
JPH0476212B2 (en)
KR960012647B1 (en) Semiconductor device and manufacture method
US4712127A (en) High reliability metal and resin container for a semiconductor device
EP0645812B1 (en) Resin-sealed semiconductor device
JP2913247B2 (en) Power semiconductor module and inverter device for vehicle
JPS5840848A (en) Insulating type semiconductor device
EP0788152B1 (en) Internal compression bonded semiconductor device with a chip frame enabling a longer creepage distance
JPS6050354B2 (en) Resin-encapsulated semiconductor device
JPH1187575A (en) Semiconductor device
JPS5861637A (en) Insulated mold type semiconductor device
JP2022144711A (en) Manufacturing method for semiconductor device
JPS60165745A (en) Resin-sealed semiconductor device
JPH08139234A (en) Semiconductor device