JPS5861637A - Insulated mold type semiconductor device - Google Patents

Insulated mold type semiconductor device

Info

Publication number
JPS5861637A
JPS5861637A JP56160209A JP16020981A JPS5861637A JP S5861637 A JPS5861637 A JP S5861637A JP 56160209 A JP56160209 A JP 56160209A JP 16020981 A JP16020981 A JP 16020981A JP S5861637 A JPS5861637 A JP S5861637A
Authority
JP
Japan
Prior art keywords
metal substrate
insulating plate
sub
alpha3
alpha1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56160209A
Other languages
Japanese (ja)
Other versions
JPS6326543B2 (en
Inventor
Tatsuo Yamazaki
山崎　龍雄
Noritoshi Kotsuji
小辻　宣俊
Toshiki Kurosu
黒須　俊樹
Yoichi Nakajima
中島　羊一
Isao Kojima
小島　勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP56160209A priority Critical patent/JPS5861637A/en
Publication of JPS5861637A publication Critical patent/JPS5861637A/en
Publication of JPS6326543B2 publication Critical patent/JPS6326543B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact

Abstract

PURPOSE:To obtain the titled device having large thermal fatigue resistance on solder material by a method wherein, when a metal substrate, an auxiliary metal substrate and an insulated board are laminated by performing soldering, a semiconductor chip is mounted on the above insulated plate, an insulation molding is performed, and the linear expansion coefficient and the thickness is lamination direction of the above are set at alpha1-alpha3 and t1-t3, and they are prescribed at alpha3<alpha1<alpha2 and t2<t3<t1. CONSTITUTION:A metal substrate 2, which will be used as a bottom face base, an auxiliary metal substrate 3 and an insulated board 4 are laminated using solder materials 5 and 6 respectively. At this time, when the linear expansion coefficient and the thickness in lamination direction of the metal substrate 2, an auxiliary metal substrate 3 and the insulated board 4 are set at alpha1, alpha2, alpha3 and t1, t2, t3 respectively, and the relations thereof are prescribed as alpha3<alpha1<alpha2 and t2<t3<t1. Subsequently, the semiconductor chip 14 such as triac and the like is adhered with a solder material 13 on the insulated board 4 using the ordinary method, L-type electrodes 7-9 are led out to outside, the chip 14 is surrounded by an epoxy case 22 and hardened after an epoxy resin has been filled in the interior.

Description

【発明の詳細な説明】 本発明はろう材の熱疲労耐量を向上さ・せた絶縁モール
ド型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated molded semiconductor device in which the thermal fatigue resistance of a brazing material is improved.

従来の絶縁モールド型半導体装置は放熱フィンとしての
金属基板の一生表面上に副金属板、絶縁板を順次ろう材
によ多積層接着し、絶縁板上に所定の半導体チップとそ
の電極をろう付して一生表面側をレジンでモールドして
いた。副金属基板は金属基板と絶縁板間の接着強度を高
めるために設けられているもので、金属基板、副金属基
板、絶縁板の各々の線膨張係数、厚さをα１．α２．α
８゜ｔｌ　ｙ　’２　ｓ　”ａ　とすると、α３〈α２
＝αｓ　＃　”２　＜”ｓ　＜ｔｌの関係に置かれてい
た。このため、副金属基板の線膨張は絶縁板の線膨張の
影響を多大に受け、実質的には線膨張量が小さくなり、
α２＝αｌが成立しなくなって、金属基板と副金属基板
間のろう材に熱応力が加わり、このろう材の熱疲労耐量
が乏しく、信頼性に欠けていた。Conventional insulating mold type semiconductor devices are made by laminating multiple sub-metal plates and insulating plates in sequence using brazing material on the surface of a metal substrate that serves as a heat dissipation fin, and then brazing predetermined semiconductor chips and their electrodes onto the insulating plates. For the rest of my life, I molded the front side with resin. The sub-metal substrate is provided to increase the adhesive strength between the metal substrate and the insulating plate, and the linear expansion coefficient and thickness of the metal substrate, sub-metal substrate, and insulating plate are set to α1. α2. α
8゜tl y '2 s ''a, then α3〈α2
= αs # “2 <”s <tl. For this reason, the linear expansion of the sub-metal substrate is greatly affected by the linear expansion of the insulating plate, and the amount of linear expansion actually becomes smaller.
Since α2=αl no longer holds true, thermal stress is applied to the brazing filler metal between the metal substrate and the sub-metal substrate, and this brazing filler metal has poor thermal fatigue resistance and lacks reliability.

それ故１本発明の目的は熱疲労耐量が大きく、信頼性の
高い絶縁モールド型半導体装置を提供することにある。Therefore, one object of the present invention is to provide an insulated molded semiconductor device that has a large thermal fatigue resistance and is highly reliable.

上記目的を達成する本発明の特徴とするところは金属基
板、副金属基板および絶縁板の各々の線　　゛膨張係数
α１．α２．α３そして厚さ’Ｉ　＋　ｔ２　＋　ｔａ
　　がα３〈α１〈α２．ｔ２〈ｔａ〈ｔｌの関係を持
っていることにある。The present invention that achieves the above object is characterized by a linear expansion coefficient α1 of each of the metal substrate, sub-metal substrate, and insulating plate. α2. α3 and thickness 'I + t2 + ta
is α3〈α1〈α2. The reason is that they have the relationship t2<ta<tl.

以下、本発明を図面に示す実施例と共に説明する。Hereinafter, the present invention will be explained along with embodiments shown in the drawings.

第１図において、１は全体として本発明になる絶縁モー
ルド型半導体装置を示している。２は金属基板でその上
側主表面に副金属基板３、絶縁板４が順次ろう材５，６
により積層接着されている。In FIG. 1, reference numeral 1 indicates an insulated molded semiconductor device according to the present invention as a whole. 2 is a metal substrate, and on its upper main surface, a sub-metal substrate 3 and an insulating plate 4 are sequentially filled with brazing materials 5 and 6.
Laminated and bonded by.

絶縁板４上にはＬ字状のリード電極７〜９がろう材、１
０〜１２によって接着され、リード電極８上にはろう材
１３を介して半導体チップ１４が接着されている。半導
体チップ１４とリード電極７゜９の間はポンディングリ
ード１５，１６、ろう材１７〜２０によって接続されて
いる。半導体チップ１４におけるｐｎ接合露出端部は図
示していないパツペーション材によシ被覆されており、
金属基板２の上側主表面の副金属基板３の周囲に溝２１
が設けられて、ここにエポキシ製ケース２２が当接され
、ケース２２内にはエポキシレジン２３が注型硬化され
、半導体チップ１４等をモールドしてい一〇 半導体チップ１４は例えばトライアック機能を持つもの
であり、リード電極７，８が主端子、リード電極９がゲ
ート端子である。On the insulating plate 4, L-shaped lead electrodes 7 to 9 are connected to the brazing material, 1
0 to 12, and a semiconductor chip 14 is bonded onto the lead electrode 8 via a brazing material 13. The semiconductor chip 14 and the lead electrodes 7.9 are connected by bonding leads 15, 16 and brazing materials 17-20. The exposed end of the pn junction in the semiconductor chip 14 is covered with a passpation material (not shown).
A groove 21 is formed around the secondary metal substrate 3 on the upper main surface of the metal substrate 2.
is provided, an epoxy case 22 is brought into contact with the epoxy case 22, and an epoxy resin 23 is cast and hardened inside the case 22, and a semiconductor chip 14 etc. is molded therein. The lead electrodes 7 and 8 are main terminals, and the lead electrode 9 is a gate terminal.

本発明においては、金属基板２．副金属基板３および絶
縁板４の線膨張係数α１．α２．α、はα。In the present invention, metal substrate 2. Linear expansion coefficient α1 of the sub-metal substrate 3 and the insulating plate 4. α2. α, is α.

くα、〈α２の関係にある。−例として金属基板２は冷
間圧延により作った鉄、副金属基板３は銅、絶縁板４は
アルミナを用いる。また、これらの厚さ’１　ｅ　ｔ２
　＋　ｔａは１２（１，（１，の関係にあり、−例とし
て金属基板２は２ｍ＋＋、副金属基板３は０．１■、絶
縁板４は０．５　ｔｔａｎである。尚、厚さｔ、〜ｔ３
は第２図に示すように、積層方向での厚さである。There is a relationship between α and 〈α2. - For example, the metal substrate 2 is made of iron made by cold rolling, the sub-metal substrate 3 is made of copper, and the insulating plate 4 is made of alumina. Also, these thicknesses '1 e t2
+ ta is in the relationship of 12 (1, (1), - for example, the metal substrate 2 is 2 m++, the sub-metal substrate 3 is 0.1 cm, and the insulating plate 4 is 0.5 ttan. ,~t3
is the thickness in the stacking direction, as shown in FIG.

以上の関係により、金属基板２と副金属基板３の間のろ
う材５の熱疲労耐量は大幅に向上する。Due to the above relationship, the thermal fatigue resistance of the brazing material 5 between the metal substrate 2 and the sub-metal substrate 3 is significantly improved.

即ち、α、くα２　ｅ　ｔ２　＜’ｓの関係から、α２
の実効的な値α２．はα３の影響を受けてα２．〈α２
　となる。一方、α１はｔｌが大きいので、他の影響を
余り受けない。従って、α１〈α２からα１ユα２１と
なり、ろう材５に加わる熱応力は小さな値となり、大き
な熱疲労耐量が得られる。α、はα１．となって実効値
が小さくなり、それだけ、α３にも近付くので、副金属
基板３と絶縁板４間のろう材６の熱疲労耐量も向上する
。That is, from the relationship α, α2 e t2 <'s, α2
The effective value α2. is influenced by α3 and becomes α2. <α2
becomes. On the other hand, since α1 has a large tl, it is not affected much by other factors. Therefore, α1 < α2 becomes α1 y α21, the thermal stress applied to the brazing filler metal 5 becomes a small value, and a large thermal fatigue resistance is obtained. α, is α1. As a result, the effective value becomes smaller and approaches α3 accordingly, so that the thermal fatigue resistance of the brazing material 6 between the sub-metal substrate 3 and the insulating plate 4 is also improved.

第１図、第２図に示すように、金属基板２、副金属基板
３、絶縁板４の長さｔｌ、　ｔ２　、　ｔｓをｔ。As shown in FIGS. 1 and 2, the lengths tl, t2, and ts of the metal substrate 2, sub-metal substrate 3, and insulating plate 4 are t.

＞ｔ２＞ｔｓの関係におき、所謂、オーバーハング部を
なくすことによって、モールドレジン２３の熱膨張によ
る絶縁板４の引きはがし現象、即ち、オーバーハング部
函のモールドレジンが熱膨張して副金属基板３と絶縁板
４間のろう材６による接着部を引きはがすようなことは
なく、熱疲労耐量は更に向上する。In the relationship of >t2>ts, by eliminating the so-called overhang part, the peeling phenomenon of the insulating plate 4 due to the thermal expansion of the mold resin 23 can be prevented, that is, the mold resin of the overhang part of the box thermally expands and the secondary metal is removed. The bond between the substrate 3 and the insulating plate 4 by the brazing material 6 is not peeled off, and the thermal fatigue resistance is further improved.

厚さｔ、〜ｔ３は絶縁板４の厚さｔ、を基準として決め
られる。即ち、絶縁板４は熱抵抗が大きいので、絶縁板
４における熱抵抗ができるだけ小さくなるような厚さｔ
ａが先ず決められ、次に金属基板２や副金属基板３の厚
さｔ、’、ｔ、が決められる。従って、”２　＜”ｓ　
＜もの関係であっても半導体チップ１４から金属基板２
に至る熱抵抗は増大しない。むしろ、副金属基板３の厚
さｔ２が薄くされることによシ、熱抵抗が小さくなって
いる。The thicknesses t and t3 are determined based on the thickness t of the insulating plate 4. That is, since the insulating plate 4 has a large thermal resistance, the thickness t is such that the thermal resistance of the insulating plate 4 is as small as possible.
First, a is determined, and then the thicknesses t,',t, of the metal substrate 2 and the sub-metal substrate 3 are determined. Therefore, “2 <”s
< Even if the relationship is between the semiconductor chip 14 and the metal substrate 2
Thermal resistance does not increase. Rather, by reducing the thickness t2 of the sub-metal substrate 3, the thermal resistance is reduced.

このため、放熱性は良好で、金属基板２と半導体チップ
１４間の温度差は小さくなり、この点からも、ろう材５
，６に加わる熱応力は低減され、熱疲労耐量は向上する
。Therefore, heat dissipation is good, and the temperature difference between the metal substrate 2 and the semiconductor chip 14 is small.
, 6 is reduced, and thermal fatigue resistance is improved.

本発明によればろう材５，６の熱疲労耐量が向上する結
果、金属基板〜絶縁板間の接着は確実となり、信頼性が
向上した絶縁モフルド型半導体装置が得られる。According to the present invention, as a result of improving the thermal fatigue resistance of the brazing materials 5 and 6, the adhesion between the metal substrate and the insulating plate becomes reliable, and an insulating modular semiconductor device with improved reliability can be obtained.

以上の実施例では絶縁板４上に１個の半導体チップを積
載した例で説明したが、本発明では、複数個の半導体チ
ップが積載されたものにも適用できる。また、半導体チ
ップ以外の素子、例えば抵抗、コンデンサ等が積載され
、所定の電気回路を構成しているモジュール等にも適用
できる。そして、半導体チップ周辺を一旦バツファコー
トレジンで被覆してからモールドレジンを注型硬化した
ものや、モールドレジンの注型硬化後にケースを除去し
たものにも適用できる。In the above embodiment, an example in which one semiconductor chip is stacked on the insulating plate 4 has been described, but the present invention can also be applied to an arrangement in which a plurality of semiconductor chips are stacked. Furthermore, the present invention can also be applied to modules that are loaded with elements other than semiconductor chips, such as resistors, capacitors, etc., and constitute a predetermined electric circuit. It can also be applied to those in which the periphery of the semiconductor chip is once coated with buffer coat resin and then the mold resin is cast and cured, or in which the case is removed after the mold resin is cast and cured.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す絶縁モールド型半導体
装置の断面図、第２図は第１図の要部を示した断面図で
ある。 ２・・・金属基板、３・・・副金属基板、４・・・絶縁
板、５゜６．１１．１３・・・ろう材、１４・・・半導
体チップ、１建１５　　　ノ　　　　図 第　　２　　　図FIG. 1 is a cross-sectional view of an insulated molded semiconductor device showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the main part of FIG. 1. 2... Metal substrate, 3... Sub-metal substrate, 4... Insulating plate, 5゜6.11.13... Brazing metal, 14... Semiconductor chip, 1 building 15 Figure 2

Claims (1)

【特許請求の範囲】 １、金属基板の一生表面上に副金属基板、絶縁板が順次
ろう材たより積層接着され、上記絶縁板上に少なくとも
１個の半導体チップおよび該半導体チップに通電するた
めの電極がろう材によシ接着され、上記−主表面側をレ
ジンでモｉルドした絶縁モールド型半導体装置において
、金属基板、副金属基板および絶縁板の線膨張係数、積
層方向における厚さの各々をαｌｔα２・α３　＊　ｔ
ｌ　廖ｔ２　＊　ｔａとしたとき、α、〈α１〈α２．
　ｔ２＜ｔａ　＜’ｔとなっていることを特徴とする絶
縁モールド型半導体装置。 ２、特許請求の範囲第１項において、金属基板。 副金属基板および絶縁板の各々の長さを４，４゜ｔａ　
としたとき、４　＞　ｚｔ＞　Ａｓであることを特徴と
する絶縁モールド型半導体装置。[Scope of Claims] 1. A sub-metal substrate and an insulating plate are successively laminated and bonded with brazing material on the surface of the metal substrate, and on the insulating plate at least one semiconductor chip and a device for supplying electricity to the semiconductor chip are provided. In the insulated molded semiconductor device in which the electrode is bonded with a brazing material and the main surface side is molded with resin, each of the linear expansion coefficient and the thickness in the stacking direction of the metal substrate, sub-metal substrate, and insulating plate αltα2・α3 * t
When l Liaot2 * ta, α, 〈α1〈α2.
An insulating mold type semiconductor device characterized in that t2<ta<'t. 2. A metal substrate according to claim 1. The length of each of the sub-metal substrate and insulating plate is 4.4゜ta.
An insulating mold type semiconductor device characterized in that, when 4>zt>As.
JP56160209A 1981-10-09 1981-10-09 Insulated mold type semiconductor device Granted JPS5861637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56160209A JPS5861637A (en) 1981-10-09 1981-10-09 Insulated mold type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56160209A JPS5861637A (en) 1981-10-09 1981-10-09 Insulated mold type semiconductor device

Publications (2)

Publication Number Publication Date
JPS5861637A true JPS5861637A (en) 1983-04-12
JPS6326543B2 JPS6326543B2 (en) 1988-05-30

Family

ID=15710109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56160209A Granted JPS5861637A (en) 1981-10-09 1981-10-09 Insulated mold type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5861637A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1107310A2 (en) * 1999-12-08 2001-06-13 DaimlerChrysler Rail Systems GmbH Isolation improvement of high power semiconductor modules
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429945U (en) * 1990-07-04 1992-03-10

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same
EP1107310A2 (en) * 1999-12-08 2001-06-13 DaimlerChrysler Rail Systems GmbH Isolation improvement of high power semiconductor modules
EP1107310A3 (en) * 1999-12-08 2005-04-27 DaimlerChrysler Rail Systems GmbH Isolation improvement of high power semiconductor modules

Also Published As

Publication number Publication date
JPS6326543B2 (en) 1988-05-30

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