JPS6326543B2 - - Google Patents

Info

Publication number
JPS6326543B2
JPS6326543B2 JP56160209A JP16020981A JPS6326543B2 JP S6326543 B2 JPS6326543 B2 JP S6326543B2 JP 56160209 A JP56160209 A JP 56160209A JP 16020981 A JP16020981 A JP 16020981A JP S6326543 B2 JPS6326543 B2 JP S6326543B2
Authority
JP
Japan
Prior art keywords
metal substrate
insulating plate
sub
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56160209A
Other languages
Japanese (ja)
Other versions
JPS5861637A (en
Inventor
Tatsuo Yamazaki
Noritoshi Kotsuji
Toshiki Kurosu
Yoichi Nakajima
Isao Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP56160209A priority Critical patent/JPS5861637A/en
Publication of JPS5861637A publication Critical patent/JPS5861637A/en
Publication of JPS6326543B2 publication Critical patent/JPS6326543B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明はろう材の熱疲労耐量を向上させた絶縁
モールド型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated molded semiconductor device in which the thermal fatigue resistance of a brazing material is improved.

従来の絶縁モールド型半導体装置は放熱フイン
としての金属基板の一主表面上に副金属基板、絶
縁板を順次ろう材により積層接着し、絶縁板上に
所定の半導体チツプとその電極をろう付して一主
表面側をレジンでモールドしていた。副金属基板
は金属基板と絶縁板間の接着強度を高めるために
設けられているもので、金属基板、副金属基板、
絶縁板の各々の線膨張係数、厚さをα1、α2、α3、
t1、t2、t3とすると、α3＜α2＝α1、t2＜t3＜t1の関
係に置かれていた。このため、副金属基板の線膨
張は絶縁板の線膨張の影響を多大に受け、実質的
には線膨張量が小さくなり、α2＝α1が成立しなく
なつて、金属基板と副金属基板間のろう材に熱応
力が加わり、このろう材の熱疲労耐量が乏しく、
信頼性に欠けていた。 In a conventional insulated mold type semiconductor device, an auxiliary metal substrate and an insulating plate are successively laminated and bonded using a brazing material on one main surface of a metal substrate serving as a heat dissipation fin, and predetermined semiconductor chips and their electrodes are brazed onto the insulating plate. The main surface side was molded with resin. The sub-metal board is provided to increase the adhesive strength between the metal board and the insulating board.
The linear expansion coefficient and thickness of each insulating plate are α 1 , α 2 , α 3 ,
Assuming t 1 , t 2 , and t 3 , the relationships were α 3 <α 2 =α 1 and t 2 <t 3 <t 1 . For this reason, the linear expansion of the secondary metal substrate is greatly affected by the linear expansion of the insulating plate, and the amount of linear expansion actually becomes small, and α 2 = α 1 no longer holds, and the relationship between the metal substrate and the secondary metal increases. Thermal stress is applied to the brazing material between the boards, and this brazing material has poor thermal fatigue resistance.
It lacked reliability.

それ故、本発明の目的は熱疲労耐量が大きく、
信頼性の高い絶縁モールド型半導体装置を提供す
ることにある。 Therefore, the purpose of the present invention is to have high thermal fatigue resistance,
An object of the present invention is to provide a highly reliable insulated molded semiconductor device.

上記目的を達成する本発明の特徴とするところ
は金属基板、副金属基板および絶縁板の各々の線
膨張係数α1、α2、α3そして厚さt1、t2、t3がα3＜
α1＜α2、t2＜t3＜t1の関係を持つていることにあ
る。 The present invention is characterized in that the metal substrate, sub-metal substrate, and insulating plate each have linear expansion coefficients α 1 , α 2 , α 3 and thicknesses t 1 , t 2 , and t 3 of α 3 . <
The reason is that they have the relationships α 1 < α 2 and t 2 < t 3 < t 1 .

以下、本発明を図面に示す実施例と共に説明す
る。 Hereinafter, the present invention will be explained along with embodiments shown in the drawings.

第１図において、１は全体として本発明になる
絶縁モールド型半導体装置を示している。２は金
属基板でその上側主表面に副金属基板３、絶縁板
４が順次ろう材５，６により積層接着されてい
る。絶縁板４上にはＬ字状のリード電極７〜９が
ろう材１０〜１２によつて接着され、リード電極
８上にはろう材１３を介して半導体チツプ１４が
接着されている。半導体チツプ１４とリード電極
７，９の間はボンデイングリード１５，１６、ろ
う材１７〜２０によつて接続されている。半導体
チツプ１４におけるpn接合露出端部は図示して
いないパツベーシヨン材により被覆されており、
金属基板２の上側主表面の副金属基板３の周囲に
溝２１が設けられて、ここにエポキシ製ケース２
２が当接され、ケース２２内にはエポキシレジン
２３が注型硬化され、半導体チツプ１４等をモー
ルドしている。 In FIG. 1, reference numeral 1 indicates an insulated molded semiconductor device according to the present invention as a whole. Reference numeral 2 denotes a metal substrate, on the upper main surface of which a sub-metal substrate 3 and an insulating plate 4 are successively laminated and bonded using brazing materials 5 and 6. L-shaped lead electrodes 7 to 9 are bonded onto the insulating plate 4 with brazing fillers 10 to 12, and a semiconductor chip 14 is bonded onto the lead electrode 8 via a brazing filler metal 13. The semiconductor chip 14 and lead electrodes 7, 9 are connected by bonding leads 15, 16 and brazing fillers 17-20. The exposed end of the pn junction in the semiconductor chip 14 is covered with a packaging material (not shown).
A groove 21 is provided around the secondary metal substrate 3 on the upper main surface of the metal substrate 2, and the epoxy case 2 is inserted into the groove 21.
2 are brought into contact with each other, and an epoxy resin 23 is cast and hardened inside the case 22 to mold the semiconductor chip 14 and the like.

半導体チツプ１４は例えばトライアツク機能を
持つものであり、リード電極７，８が主端子、リ
ード電極９がゲート端子である。 The semiconductor chip 14 has, for example, a triax function, and the lead electrodes 7 and 8 are main terminals, and the lead electrode 9 is a gate terminal.

本発明においては、金属基板２、副金属基板３
および絶縁板４の線膨張係数α1、α2、α3はα3＜α1
＜α2の関係にある。一例として金属基板２は冷間
圧延により作つた鉄、副金属基板３は銅、絶縁板
４はアルミナを用いる。また、これらの厚さt1、
t2、t3はt2＜t3＜t1の関係にあり、一例として金属
基板２は２mm、副金属基板３は0.1mm、絶縁板４
は0.5mmである。尚、厚さt1〜t3は第２図に示すよ
うに、積層方向での厚さである。 In the present invention, the metal substrate 2, the sub-metal substrate 3
And the linear expansion coefficients α 1 , α 2 , α 3 of the insulating plate 4 are α 3 <α 1
The relationship is <α 2 . As an example, the metal substrate 2 is made of iron made by cold rolling, the sub-metal substrate 3 is made of copper, and the insulating plate 4 is made of alumina. Also, these thicknesses t 1 ,
t 2 and t 3 have a relationship of t 2 < t 3 < t 1. For example, the metal substrate 2 is 2 mm, the sub metal substrate 3 is 0.1 mm, and the insulating plate 4 is 2 mm.
is 0.5mm. Note that the thicknesses t1 to t3 are the thicknesses in the lamination direction, as shown in FIG.

以上の関係により、金属基板２と副金属基板３
の間のろう材５の熱疲労耐量は大幅に向上する。 Due to the above relationship, the metal substrate 2 and the sub metal substrate 3
During this period, the thermal fatigue resistance of the brazing filler metal 5 is significantly improved.

即ち、α3＜α2、t2＜t3の関係から、α2の実効的
な値α2aはα3の影響を受けてα2a＜α2となる。一
方、α1はt1が大きいので、他の影響を余り受けな
い。従つて、α1＜α2からα1α2aとなり、ろう材
５に加わる熱応力は小さな値となり、大きな熱疲
労耐量が得られる。α2はα2aとなつて実効値が小
さくなり、それだけ、α3にも近付くので、副金属
基板３と絶縁板４間のろう材６の熱疲労耐量も向
上する。 That is, from the relationships α 3 <α 2 and t 2 <t 3 , the effective value α 2a of α 2 is influenced by α 3 and becomes α 2a <α 2 . On the other hand, since t 1 is large, α 1 is not affected much by other factors. Therefore, since α 1 <α 2 , α 1 α 2a holds true, the thermal stress applied to the brazing filler metal 5 becomes a small value, and a large thermal fatigue resistance is obtained. Since α 2 becomes α 2a and its effective value becomes smaller and approaches α 3 accordingly, the thermal fatigue resistance of the brazing filler metal 6 between the sub-metal substrate 3 and the insulating plate 4 is also improved.

第１図、第２図に示すように、金属基板２、副
金属基板３、絶縁板４の長さl1、l2、l3をl1＞l2＞
l3の関係におき、所謂、オーバーハング部をなく
すことによつて、モールドレジン２３の熱膨張に
よる絶縁板４の引きはがし現象、即ち、オーバー
ハング部内のモールドレジンが熱膨張して副金属
基板３と絶縁板４間のろう材６による接着部を引
きはがすようなことはなく、熱疲労耐量は更に向
上する。 As shown in FIGS. 1 and 2, the lengths l 1 , l 2 , and l 3 of the metal substrate 2, sub-metal substrate 3 , and insulating plate 4 are determined by l 1 > l 2 >
l In relation to 3 , by eliminating the so-called overhang part, the peeling phenomenon of the insulating plate 4 due to thermal expansion of the mold resin 23 can be prevented, that is, the mold resin in the overhang part thermally expands and the secondary metal substrate There is no possibility that the bond between the soldering material 6 and the insulating plate 3 is torn off, and the thermal fatigue resistance is further improved.

厚さt1〜t3は絶縁板４の厚さt3を基準として決
められる。即ち、絶縁板４は熱抵抗が大きいの
で、絶縁板４における熱抵抗ができるだけ小さく
なるような厚さt3が先ず決められ、次に金属基板
２や副金属基板３の厚さt1、t2が決められる。従
つて、t2＜t3＜t1の関係であつても半導体チツプ
１４から金属基板２に至る熱抵抗は増大しない。
むしろ、副金属基板３の厚さt2が薄くされること
により、熱抵抗が小さくなつている。このため、
放熱性は良好で、金属基板２と半導体チツプ１４
間の温度差は小さくなり、この点からも、ろう材
５，６に加わる熱応力は低減され、熱疲労耐量は
向上する。 The thicknesses t 1 to t 3 are determined based on the thickness t 3 of the insulating plate 4. That is, since the insulating plate 4 has a large thermal resistance, the thickness t 3 that makes the thermal resistance of the insulating plate 4 as small as possible is first determined, and then the thicknesses t 1 and t of the metal substrate 2 and the sub-metal substrate 3 are determined. 2 can be determined. Therefore, even if the relationship t 2 <t 3 <t 1 holds, the thermal resistance from the semiconductor chip 14 to the metal substrate 2 does not increase.
Rather, by reducing the thickness t2 of the sub-metal substrate 3, the thermal resistance is reduced. For this reason,
The heat dissipation is good, and the metal substrate 2 and semiconductor chip 14
The temperature difference between them becomes smaller, and from this point of view as well, the thermal stress applied to the brazing materials 5 and 6 is reduced, and the thermal fatigue resistance is improved.

本発明によればろう材５，６の熱疲労耐量が向
上する結果、金属基板〜絶縁板間の接着は確実と
なり、信頼性が向上した絶縁モールド型半導体装
置が得られる。 According to the present invention, the thermal fatigue resistance of the brazing materials 5 and 6 is improved, and as a result, the adhesion between the metal substrate and the insulating plate becomes reliable, and an insulated molded semiconductor device with improved reliability can be obtained.

以上の実施例では絶縁板４上に１個の半導体チ
ツプを積載した例で説明したが、本発明では、複
数個の半導体チツプが積載されたものにも適用で
きる。また、半導体チツプ以外の素子、例えば抵
抗、コンデンサ等が積載され、所定の電気回路を
構成しているモジユール等にも適用できる。そし
て、半導体チツプ周辺を一旦バツフアコートレジ
ンで被覆してからモールドレジンを注型硬化した
ものや、モールドレジンの注型硬化後にケースを
除去したものにも適用できる。 In the above embodiment, an example in which one semiconductor chip is stacked on the insulating plate 4 has been described, but the present invention can also be applied to an arrangement in which a plurality of semiconductor chips are stacked. The present invention can also be applied to modules that are loaded with elements other than semiconductor chips, such as resistors, capacitors, etc., and constitute a predetermined electric circuit. It can also be applied to those in which the periphery of the semiconductor chip is once coated with buffer coat resin and then the mold resin is cast and cured, or in which the case is removed after the mold resin is cast and cured.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す絶縁モールド
型半導体装置の断面図、第２図は第１図の要部を
示した断面図である。 ２……金属基板、３……副金属基板、４……絶
縁板、５，６，１１，１３……ろう材、１４……
半導体チツプ、２３……レジン。 FIG. 1 is a cross-sectional view of an insulated molded semiconductor device showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the main part of FIG. 1. 2... Metal substrate, 3... Sub-metal substrate, 4... Insulating plate, 5, 6, 11, 13... Brazing metal, 14...
Semiconductor chip, 23...resin.

Claims (1)

【特許請求の範囲】 １ 金属基板の一主表面上に副金属基板、絶縁板
が順次ろう材により積層接着され、上記絶縁板上
に少なくとも１個の半導体チツプおよび該半導体
チツプに通電するための電極がろう材により接着
され、上記一主表面側をレジンでモールドした絶
縁モールド型半導体装置において、金属基板、副
金属基板および絶縁板の線膨張係数、積層方向に
おける厚さの各々をα1、α2、α3、t1、t2、t3とし
たとき、α3＜α1＜α2、t2＜t3＜t1となつているこ
とを特徴とする絶縁モールド型半導体装置。 ２ 特許請求の範囲第１項において、金属基板、
副金属基板および絶縁板の各々の長さをl1、l2、
l3としたとき、l1＞l2＞l3であることを特徴とする
絶縁モールド型半導体装置。[Scope of Claims] 1. A sub-metal substrate and an insulating plate are successively laminated and bonded on one main surface of a metal substrate using a brazing material, and on the insulating plate at least one semiconductor chip and a device for energizing the semiconductor chip are attached. In an insulated molded semiconductor device in which electrodes are bonded with a brazing material and the first main surface side is molded with resin, the coefficient of linear expansion and the thickness in the stacking direction of the metal substrate, sub-metal substrate, and insulating plate are each α 1 , An insulating mold type semiconductor device characterized in that, when α 2 , α 3 , t 1 , t 2 , and t 3 , α 3 <α 1 <α 2 and t 2 <t 3 <t 1 . 2 In claim 1, a metal substrate,
Let the lengths of the sub metal substrate and the insulating plate be l 1 , l 2 ,
An insulating mold type semiconductor device characterized in that when l 3 , l 1 > l 2 > l 3 .
JP56160209A 1981-10-09 1981-10-09 Insulated mold type semiconductor device Granted JPS5861637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56160209A JPS5861637A (en) 1981-10-09 1981-10-09 Insulated mold type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56160209A JPS5861637A (en) 1981-10-09 1981-10-09 Insulated mold type semiconductor device

Publications (2)

Publication Number Publication Date
JPS5861637A JPS5861637A (en) 1983-04-12
JPS6326543B2 true JPS6326543B2 (en) 1988-05-30

Family

ID=15710109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56160209A Granted JPS5861637A (en) 1981-10-09 1981-10-09 Insulated mold type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5861637A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429945U (en) * 1990-07-04 1992-03-10

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2255441C (en) * 1997-12-08 2003-08-05 Hiroki Sekiya Package for semiconductor power device and method for assembling the same
DE19959248A1 (en) * 1999-12-08 2001-06-28 Daimler Chrysler Ag Insulation improvement for high-performance semiconductor modules

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429945U (en) * 1990-07-04 1992-03-10

Also Published As

Publication number Publication date
JPS5861637A (en) 1983-04-12

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