JP4856821B2 - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the conventional semiconductor device of a BGA type wherein a semiconductor element is mounted by using a printed board, a ceramic board, a flexible sheet, etc., as a retaining substrate, however, the retaining substrate is not a member which is essential but an extra member, the thickness of the retaining substrate makes the semiconductor device large, heat generated from the semiconductor element built in the device is hardly dissipated, furthermore a solder electrode becomes a structure having a constriction, and to solve the problem of concentrated stress in the constriction part, which generates cracks. SOLUTION: Conducting patterns 11A-11D are buried in insulating resin 10 and formed, and a conducting foil 20 is subjected to half etching and formed, so that thickness of a semiconductor device can be reduced. An electrode 11D for heat dissipation is disposed, and a heat dissipating means RD is arranged at the back side of a semiconductor element 12, so that the semiconductor device and a module which are excellent in heat dissipating property can be provided. Furthermore, by making a structure wherein an external connection electrode does not have a constriction, generation of solder cracks can be prevented.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a semiconductor module that can release heat from a semiconductor element satisfactorily and buffer stress acting on a solder electrode.
[0002]
[Prior art]
In recent years, IC packages are increasingly used in portable devices and small / high-density mounting devices, and conventional IC packages and their mounting concepts are about to change drastically. Details are described, for example, in the special issue “CSP technology and mounting materials and devices supporting it” in the electronic materials (September 1998, page 22).
[0003]
FIG. 17 employs a flexible sheet 50 as an interposer substrate. A copper foil pattern 51 is bonded to the flexible sheet 50 via an adhesive, and an IC chip 52 is fixed. As the conductive pattern 51, there is a bonding pad 53 formed around the IC chip 52. A solder ball connection pad 54 is formed through a wiring 51B formed integrally with the bonding pad 53.
[0004]
The back side of the solder ball connection pad 54 is provided with an opening 56 in which a flexible sheet is opened, and a solder ball 55 is formed through the opening 56. The flexible sheet 50 is used as a substrate and the whole is sealed with an insulating resin 58. Reference numeral 57 is a thin metal wire.
[0005]
On the other hand, FIG. 18 shows a semiconductor device in which the IC chip 52 is mounted face down. This employs solder balls 60 instead of the fine metal wires 57 to reduce the thickness of the entire semiconductor device.
[0006]
[Problems to be solved by the invention]
However, the flexible sheet 50 provided under the IC chip 52 is very expensive, and there are problems such as an increase in cost, a problem that the thickness of the package is increased, and an increase in weight.
[0007]
Further, since the support substrate is made of a material other than metal, there is a problem that the thermal resistance from the IC chip to the outside of the package is large. The support substrate is a flexible sheet, a ceramic substrate, or a printed substrate. Further, the heat conduction path made of a material having good heat conduction is a path that reaches the solder ball 55 through the copper foil pattern 51 as shown by a thick arrow, and has a structure that cannot sufficiently release the heat of the IC chip. Therefore, there is a problem that the temperature of the IC chip rises at the time of driving, and the driving current cannot sufficiently flow.
[0008]
  The semiconductor device of the present invention includes a pad provided opposite to a bonding electrode of a semiconductor element, an external connection electrode provided on a wiring electrically connected to the pad, and an electrical connection means with the pad. The semiconductor elements connected face-down, an insulating resin that seals the semiconductor element so that the back surface of the external connection electrode is exposed and integrated, and heat dissipation provided on the back surface side of the semiconductor element And a conductive film made of a different material is provided on the upper surface of the pad, and an eaves made of the conductive film is provided.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment for explaining a semiconductor device
First, a semiconductor device of the present invention will be described with reference to FIGS. 1 shows a semiconductor module provided with a heat dissipation means RD, FIG. 2A is a plan view of the semiconductor device 15 used in FIG. 1, and FIG. 1B is a cross-sectional view taken along line AA. .
[0033]
First, the semiconductor device 15 to which the heat radiation means RD is attached will be described with reference to FIG. The following components are embedded in the insulating resin 10 shown in the figure. In other words, the pad 11A, the wiring 11B integrated with the pad 11A, and the wiring 11B are integrated with the external connection electrode 11C provided at the other end of the wiring 11B. Further, in a region surrounded by the conductive patterns 11A to 11C, a heat radiating electrode 11D is provided, and the heat radiating electrode 11D and the semiconductor element 12 provided thereon are embedded. The semiconductor element 12 is fixed through an insulating adhesive means, here, an underfill material AF. The semiconductor element 12 is indicated by a dotted line in FIG. 2A.
[0034]
Further, the bonding electrode 13 and the pad 11A of the semiconductor element 12 are electrically connected via an electrical connection means SD such as a brazing material such as solder, a conductive paste, or an anisotropic conductive resin.
[0035]
In order to prevent the flow of the electrical connection means SD, the conductive pattern is provided with a flow prevention film DM. For example, taking solder as an example of the electrical connection means SD, as shown in FIG. 2B, a flow prevention film DM is formed on at least a part of the conductive patterns 11A to 11C to prevent the flow of solder. The flow preventing film is a film having poor wettability with solder, such as a polymer film (solder resist) or Ni.
[0036]
The planar shape of this flow prevention film is shown in FIG. FIG. 8 shows another embodiment in which the electrode 11D for heat dissipation is omitted, but the formation method on the conductive pattern is the same, and will be described with reference to this drawing.
[0037]
In FIG. 8, five patterns A to E are formed for the convenience of drawing, but one of these is actually selected and formed in all the conductive patterns. In the pattern shown in A, a flow prevention film DM is provided at the boundary between the pad 11A and the wiring 11B, and an electrical connection means is formed over substantially the entire area of the pad 11A. Further, the flow prevention film DM may be formed including the entire area of the wiring 11B or the external connection electrode 11C. In B, the flow prevention film DM is formed on the pad, and the pad corresponding to the portion where the electrical connection means is provided is exposed. C shows a flow prevention film DM formed on the wiring 11B and the external connection electrode 11C in addition to the type B formation region. D is a type C opening from a rectangle to a circle. Further, E is a flow prevention film DM formed in a ring shape on the pad. The pad 11A is shown as a rectangle, but may be a circle. This flow prevention film DM prevents the flow of brazing material such as solder, conductive paste such as Ag paste, and conductive resin, and has poor wettability with respect to these electrical connection means. For example, when the solder is provided in the type D, when the solder is melted, the solder is blocked by the flow preventing film DM, and a clean hemispherical solder is formed by the surface tension. Further, since a passivation film is formed around the bonding electrode 13 of the semiconductor element to which the solder is attached, the solder gets wet only to the bonding electrode. Therefore, when the semiconductor element and the pad are connected via the solder, the solder is maintained at a certain height in a shell shape. Also, this height can be adjusted by the amount of solder, so that a certain gap can be provided between the semiconductor element and the conductive pattern, and a cleaning liquid can be infiltrated between them, and a low-viscosity adhesive (here underfill material) Can also be infiltrated. Furthermore, it is possible to improve the adhesiveness with the insulating adhesive means AF by covering all the areas other than the connection region with the flow preventing film DM. Further, when an insulating material is employed as the flow prevention film DM, the flow prevention film DM may be formed over the entire area of the conductive foil 21 except for the connection portion of FIG.
[0038]
As shown in FIG. 2, the side surfaces of the conductive patterns 11 </ b> A to 11 </ b> D are etched non-anisotropically, here formed by wet etching, have a curved structure, and this curved structure generates an anchor effect. .
[0039]
This structure is composed of four materials: a semiconductor element 12, a plurality of conductive patterns 11 </ b> A to 11 </ b> C, a heat radiation electrode 11 </ b> D, an insulating adhesive means AF, and an insulating resin 10 for embedding them. Further, as described above, in the arrangement region of the semiconductor element 12, the insulating adhesive means AF is filled on and between the conductive patterns 11A to 11D, and the separation groove 14 formed by etching is formed in the separation groove 14 in particular. The insulating adhesive means AF is filled, and everything including them is sealed with the insulating resin 10. The conductive patterns 11A to 11D and the semiconductor element 12 are supported by the insulating resin 10 and the insulating adhesive means AF.
[0040]
As the insulating adhesive means AF, an adhesive made of an insulating material and an underfill material are preferable. The underfill material is preferably a material that can penetrate into the gap between the semiconductor element and the conductive pattern, and further, a filler that functions as a spacer may be mixed therein.
[0041]
Further, as the insulating resin 10, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. The insulating resin 10 may be any resin as long as it is a resin that can be hardened using a mold, a resin that can be coated by dipping or coating. In addition, as the conductive patterns 11A to 11D, a conductive foil mainly made of Cu, a conductive foil mainly made of Al, or a Fe—Ni alloy, an Al—Cu laminate, an Al—Cu—Al laminate, etc. Can be used. Of course, other conductive materials are possible, and a conductive material that can be etched and a conductive material that evaporates with a laser are particularly preferable. In consideration of half-etching property, plating formability, and thermal stress, a conductive material mainly composed of Cu formed by rolling is preferable. This is because the crystal structure grows larger in the X and Y axis directions than in the Z axis direction, and thus is excellent in mechanical strength, flexibility, and intrusion of contaminants from the outside. Moreover, although the wiring 11B is extended, the rolled Cu foil has the strength against the stress applied here, and also has the merit of reducing the wiring resistance.
[0042]
In the present invention, since the insulating resin 10 and the insulating adhesive means AF are also filled in the separation groove 14, the conductive pattern can be prevented from coming off due to the anchor effect. Further, by adopting non-anisotropic etching by employing dry etching or wet etching as etching, the side surface of the pad 11A can be curved. As a result, a structure in which the conductive patterns 11A to 11D cannot be removed from the package can be realized.
[0043]
Moreover, the back surfaces of the conductive patterns 11 </ b> A to 11 </ b> D are exposed from the insulating resin 10. In particular, the back surface of the heat radiation electrode 11D can be fixed to the second circuit pattern 12B on the mounting substrate. With this structure, the heat generated from the semiconductor element 12 can be dissipated to the second circuit pattern 12B on the mounting substrate, the temperature rise of the semiconductor element 12 can be prevented, and the drive current of the semiconductor element 12 can be increased accordingly. . When heat dissipation is not considered, the heat dissipation electrode 11C may be omitted and the pattern as shown in FIG. 8 may be used. At this time, the second circuit pattern on the mounting board is omitted.
[0044]
In this semiconductor device, since the conductive patterns 11A to 11D are supported by the insulating resin 10 as the sealing resin and the insulating adhesive means AF, a support substrate is not necessary. This configuration is a feature of the present invention. As explained in the section of the prior art, the copper foil pattern of the conventional semiconductor device is supported by a support substrate (flexible sheet, printed circuit board or ceramic substrate) or supported by a lead frame, so it is essentially unnecessary. However, a good configuration is added. However, this circuit device is configured with the minimum necessary components and does not require a support substrate. Therefore, the circuit device is thin and lightweight, and has a feature of being inexpensive because it does not require material costs.
[0045]
Further, when the conductive patterns 11A to 11D exposed from the insulating resin 10 are covered with a brazing material such as solder, the area of the heat radiation electrode 11D is larger, and thus the brazing material may get wet. Therefore, when fixing on the mounting substrate 18, it is assumed that the brazing material 23 on the back surface of the external connection electrode 11C does not get wet with the first circuit pattern 19A on the mounting substrate 18, resulting in poor connection.
[0046]
In order to solve this, an insulating film 16 is formed on the back surface of the semiconductor device 15. The dotted circles shown in the external connection electrodes and the heat radiation electrodes in FIG. 2A indicate the external connection electrodes 11C ... exposed from the insulating coating 16, and the heat radiation electrode 11D. In other words, the portions other than the circle are covered with the insulating coating 16, and the size of the circles is made substantially the same, and the thickness of the brazing material formed here is made substantially the same.
[0047]
Further, the exposed portion 17 of the heat radiation electrode 11D may be formed larger than the exposed size of the external connection electrode 11C in consideration of heat dissipation of the semiconductor element.
[0048]
Further, by providing the insulating coating 16, the wiring provided on the mounting substrate can be extended to the back surface of the semiconductor device. In general, the wiring provided on the mounting substrate side is arranged to bypass the fixing region of the semiconductor device, but can be arranged without bypassing by forming the insulating film 16. The semiconductor device 15 has been described above.
[0049]
Conventionally, as shown in FIGS. 17 and 18, a path through the solder ball 55 contributes to heat dissipation. However, as shown in FIG. 1, the semiconductor device 15 includes a first heat dissipation path via the external connection electrode 11C, a second heat dissipation path via the heat dissipation means RD, and / or a third heat dissipation electrode 11D. The heat radiation path is provided, and the driving capability of the semiconductor element can be further improved by these. The first heat radiation path is indicated by a two-dot chain line arrow, the second heat radiation path is indicated by a one-dot chain line arrow, and the third heat radiation path is indicated by a solid line arrow.
[0050]
In FIG. 1, the external connection electrode 11 </ b> C is electrically connected to a first circuit pattern 19 </ b> A formed on the mounting substrate 18, and the heat dissipation electrode 11 </ b> D is a second circuit formed on the mounting substrate 18. It is connected to the pattern 19B. Here, since the brazing material is used as the external connection means 23, the heat radiation electrode 11D and the second circuit pattern 19B are thermally coupled through the brazing material. Further, a general heat radiating fin is adopted as the heat radiating means RD. In particular, the thickness of the insulating resin 10 can be controlled between the semiconductor element and the heat radiating means RD, and further, a filler can be mixed into the insulating resin 10 to efficiently release the heat of the semiconductor element. . Also, the back surface of the semiconductor element can be exposed. In this case, insulation between the heat radiation means RD and the semiconductor element is taken into consideration, and an insulating material having excellent heat conduction is provided therebetween.
[0051]
Further, like the conductive pattern PTN shown in FIG. 8, the heat radiation electrode 11D may be omitted.
Second Embodiment Explaining Method for Manufacturing Semiconductor Device
This manufacturing method shows the manufacturing method of the semiconductor device 15 of FIG. 2, and FIGS. 3 to 7 are cross-sectional views corresponding to the line AA of FIG. 2A.
[0052]
First, a conductive foil 20 is prepared as shown in FIG. The thickness is preferably about 10 μm to 300 μm, and here, a rolled copper foil of 70 μm is employed. Subsequently, a conductive film 21 or a photoresist is formed on the surface of the conductive foil 20 as an etching resistant mask. This pattern is the same as the pads 11A, wirings 11B, external connection electrodes 11C, and heat radiation electrodes 11D in FIG. 2A. When a photoresist is employed instead of the conductive coating 21, a conductive coating such as Au, Ag, Pd, or Ni may be formed at least in a portion corresponding to the pad in the lower layer of the photoresist. This is because the surface of Cu is likely to be oxidized and may cause a solder failure. These films enable solder connection without considering Cu oxidation. (See Figure 3 above)
Subsequently, a flow prevention film DM is formed on the patterned conductive film 21 and half-etched. In this case, the etching is performed through the patterned photoresist, and the etching depth may be shallower than the thickness of the conductive foil 20. Note that the shallower the etching depth, the finer the pattern can be formed. Alternatively, half etching may be performed using the conductive film 21 as a mask, and then the flow preventing film DM may be formed.
[0053]
And by half-etching, the conductive patterns 11 </ b> A to 11 </ b> D appear in a convex shape on the surface of the conductive foil 20. As described above, the conductive foil 20 is a Cu foil whose main material is Cu formed by rolling. However, a conductive foil made of Al, a conductive foil made of Fe—Ni alloy, a Cu—Al laminate, or an Al—Cu—Al laminate may be used. In particular, an Al—Cu—Al laminate can prevent warping caused by a difference in thermal expansion coefficient. (See FIG. 4 above)
Subsequently, the semiconductor element 12 is fixed face-down, the bonding electrode 13 of the semiconductor element 12 and the pad 11A are electrically connected, and then an underfill material AF is provided. Here, since the flow prevention film DM is formed, the flow of the brazing material SD can be prevented. In particular, when a brazing material is employed, if a flow preventing film DM having poor wettability is employed, the brazing material does not flow toward the wiring 11B, and the thickness of the solder can be maintained even after fixing.
[0054]
Next, a solder fixing method will be described. In general, a semiconductor element 12 with a solder ball attached to the bonding electrode 13 side is prepared, a solder paste is provided on the pad 11A side, and the semiconductor element 12 is temporarily bonded by the adhesive force of the solder paste. And it puts in a furnace and melts solder. Since the flow preventing film DM is formed, the solder does not flow and is maintained at a desired thickness.
[0055]
Further, since the flow preventing film DM is formed, the semiconductor element 12 on which the solder ball is not formed may be mounted and fixed after the hemispherical brazing material is fixedly formed on the pad 11A side.
[0056]
The reverse is also possible. That is, the semiconductor element 15 in which solder balls are formed is prepared and placed in a furnace for soldering.
[0057]
After the solder is fixed in this manner, the space between the semiconductor element 12 and the conductive foil 20 is washed, the underfill material AF is applied, and the semiconductor element 12 and the conductive patterns 11A to 11D are infiltrated. Since the solder SD is formed to have a desired thickness, the permeability of the cleaning liquid is improved, and the permeability of the underfill material is reduced. Thereby, the semiconductor element 12 can be fixed and passivated.
[0058]
The point of this process is that the semiconductor element can be mounted without adopting a support substrate, and can be mounted face-down, and the thickness of the insulating resin can be reduced by the amount of no lifting of the fine metal wire. (See Figure 5 above)
And insulating resin 10 is formed so that the whole may be covered. The insulating resin 10 may be either thermoplastic or thermosetting.
[0059]
Further, it can be realized by transfer molding, injection molding, dipping or coating. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as a liquid crystal polymer and polyphenylene sulfide can be realized by injection molding.
[0060]
In particular, the thickness of the solder can be adjusted, and the molten resin can be easily formed between the semiconductor element and the conductive pattern due to the feature that the thickness of the solder can be adjusted, so that sealing without voids is possible.
[0061]
In the present embodiment, the thickness of the insulating resin is adjusted so that about 100 μm is covered from the back surface of the semiconductor element. This thickness can be increased or decreased in consideration of the strength and heat dissipation of the semiconductor device.
[0062]
Further, if the back surface of the semiconductor element is brought into contact with the mold, the back surface of the semiconductor element can be exposed from the package. In particular, the structure in which the heat of the semiconductor element can be further released by thinning the insulating resin 10 formed on the back surface of the semiconductor element or by exposing the back surface of the semiconductor element and disposing the heat sink RD in this portion. I can take it.
[0063]
FIG. 6B shows a method for exposing the back surface of the semiconductor element 15. D1 is an upper mold, D2 is a lower mold, and SH is a buffer sheet. Generally, when the conductive foil 20 on which the semiconductor element 15 is mounted is disposed in a mold and the back surface of the semiconductor element 15 is brought into contact with the upper mold, the back surface of the semiconductor element 15 is exposed from the insulating resin 10. However, in order to prevent the resin from entering the back surface, a considerable pressure is applied, and an external force may be applied to the chip or the solder. Therefore, here, the buffer sheet SH is disposed on the back surface of the semiconductor element 15 to reduce the external force.
[0064]
In the resin injection, the conductive patterns 11A to 11D are integrated with the sheet-like conductive foil 20, and therefore, the conductive patterns 11A to 11D are not displaced at all unless the conductive foil 20 is displaced.
[0065]
As described above, the conductive resin 11 </ b> A to 11 </ b> D and the semiconductor element 12 formed as convex portions are embedded in the insulating resin 10, and the conductive foil 20 below the convex portions is exposed on the back surface. (See Figure 6 above)
Subsequently, the conductive foil 20 exposed on the back surface of the insulating resin 10 is removed, and the conductive patterns 11A to 11D are individually separated.
[0066]
Various methods are conceivable for the separation step here, and the back surface may be removed by etching, or may be separated by polishing or grinding. Moreover, you may employ | adopt both. For example, if the insulating resin 10 is etched until it is exposed, the shaving residue of the conductive foil 20 and the burr-like metal that is thinly spread on the outside bite into the insulating resin 10 and the insulating adhesive means AF. There's a problem. Therefore, if the cutting is stopped before the insulating resin 10 or the insulating adhesive means AF is exposed, and then the pads 11 are separated by etching, the surface of the insulating resin 10 or the insulating adhesive means AF is electrically conductive. The metal of the foil 20 can be formed without biting in. Thereby, the short circuit between the conductive patterns 11A to 11D with fine intervals can be prevented. Further, if etching is performed so that the back surface of the conductive pattern is on the inner side of the bottom of the separation groove 14, the resin filled in the separation groove 14 jumps out, and the extended surface distance can be increased accordingly, and the breakdown voltage can be improved.
[0067]
In addition, when a plurality of one unit to be the semiconductor device 15 are formed, a dicing process is added after the separation process.
[0068]
Here, a dicing apparatus is employed to separate the components individually, but chocolate breaks, presses and cuts are also possible.
[0069]
In addition, here, the insulating film 16 is formed on the conductive patterns 11A to 11D that are separated and exposed on the back surface, and is patterned so as to expose the portion indicated by the dotted circle in FIG. 2A, and thereafter the portion indicated by the arrow. The semiconductor device is diced.
[0070]
The solder 23 may be formed either before dicing or after dicing. In particular, if a brazing material is formed by screen printing and then melted before dicing, solder can be formed on a plurality of semiconductor devices at once. In addition, when the external connection means 23 is connected with the brazing material SD, it is better to increase the melting point of the electrical connection means SD.
[0071]
FIG. 7B shows an integrated object PK in which the semiconductor elements 12 are sealed in a matrix. As shown in the figure, even when the conductive patterns 11A to 11D are separated, the plurality of semiconductor elements 12 are integrated with an insulating resin. Therefore, the formation of the insulating coating 16 and the formation of the external connection means 23 can be formed together, and the semiconductor device 15 can be individually separated by dicing thereafter. Although it takes time, the insulating coating 16 and the external connection means 23 may be formed after dicing.
[0072]
With the above manufacturing method, a light, thin and small package in which a conductive pattern and a semiconductor element are embedded in an insulating resin can be realized.
Next, effects produced by the above manufacturing method will be described.
[0073]
First, since the conductive pattern is half-etched and supported integrally with the conductive foil, the support substrate used for conventional support can be eliminated.
[0074]
Second, since the conductive foil is formed with a pad that is half-etched to form a convex portion, the pad can be miniaturized. Accordingly, the width and interval can be reduced, and a package with a smaller planar size can be formed.
[0075]
Third, since it is composed of a conductive pattern, a semiconductor element, a connecting means, and a sealing material, a thin semiconductor device that can be configured with the minimum necessary, can eliminate wasteful materials as much as possible, and can greatly reduce costs. realizable.
[0076]
Fourth, the pad is formed as a convex portion by half-etching, and the individual separation is performed after sealing, so that tie bars and suspension leads are not necessary. Therefore, the formation of tie bars (suspending leads) and the cutting of tie bars (suspending leads) are completely unnecessary in the present invention.
[0077]
Fifth, after the conductive pattern that became the convex portion is embedded in the insulating resin, the conductive foil is removed from the back surface of the insulating resin, and the conductive pattern is separated. Resin burrs generated between the leads can be eliminated.
[0078]
Sixth, the back surface of the semiconductor element 12 can be exposed, or a thin insulating resin 10 can be formed on the back surface. Therefore, heat radiation means RD such as heat radiation fins can be disposed on the back surface side of the semiconductor element 12, and the heat of the semiconductor element 12 can be efficiently released.
[0079]
Seventh, the semiconductor element is fixed to the heat radiation electrode via the insulating adhesive means, and the heat radiation electrode is exposed from the back surface. Therefore, as shown in FIG. 1, the second circuit pattern 19B of the mounting substrate 18 and the heat radiation electrode 11D can be thermally fixed, and heat can be released through the second circuit pattern 19B. Furthermore, heat dissipation is further improved by mixing fillers such as Si oxide film and aluminum oxide into the insulating adhesive means. Moreover, if a filler is mixed and the size is substantially unified, it can have a function as a spacer.
Third embodiment for explaining a semiconductor module
FIG. 9 shows a semiconductor module. FIG. 10A is a plan view of the semiconductor device 40 mounted on this module, and FIG. 10B is a cross-sectional view taken along the line AA.
[0080]
In FIG. 2, the wiring 11 </ b> B and the external connection electrode 11 </ b> C are integrally formed on the pad 11 </ b> A, but here, the back surface of the pad 11 </ b> A is an external connection electrode.
[0081]
Further, since the back surface of the pad 11A is rectangular, the pattern exposed from the insulating coating 16 is also formed in the same pattern as the rectangle. In consideration of the adhesiveness of the insulating adhesive means AF, the groove 43 is formed so that the heat radiation electrode 11D is divided into a plurality of parts.
[0082]
The heat radiation electrode 11D may be omitted, or the back surface of the semiconductor element 12 may be exposed. Moreover, since the manufacturing method is substantially the same as the manufacturing method described above, the description thereof is omitted.
[0083]
As described above, since the heat radiation means RD and / or the heat radiation electrode 11D are employed, the heat generated from the semiconductor element can be released to the outside. Therefore, by applying to a semiconductor element that dislikes heat generation such as a memory, a microcomputer, or a CPU, the capability can be sufficiently exhibited.
Fourth embodiment for explaining a semiconductor device
A semiconductor device according to the present embodiment is shown in FIG. FIG. 11A is a plan view thereof, and FIG. 11B is a cross-sectional view taken along line AA when the semiconductor device 50 is mounted on the mounting substrate 42.
[0084]
In the above description, the electrode provided on the back surface of the region of the semiconductor element 12 is provided in order to enhance the heat dissipation action. However, these electrodes have a heat dissipation function and also have a function of buffering stress acting on the external connection electrode 11C provided in the peripheral portion of the semiconductor device.
[0085]
As shown in FIG. 11, the semiconductor device 50 is characterized in that a stress buffering electrode 11E is provided on the back surface of the electrode 11D surrounded by the external connection electrode 11C so as to cover the entire back surface. That is, the solder electrode 11E having a size larger than that of the external connection electrode 11C is provided. This size may be equal to or larger than that of a semiconductor element. It may be slightly smaller. The effect | action by this is demonstrated below. The 11C may be solder, solder bumps, or conductive adhesive.
[0086]
The semiconductor device 50 according to the present invention is supported by the insulating resin 10 as a whole. Since the thermal expansion coefficients of the mounting substrate 43 and the insulating resin 10 are often different, the difference is made as small as possible. However, since it is very difficult to make them identical, the thermal expansion coefficients of the two are inevitably different. Therefore, when the temperature of both the semiconductor device 50 and the mounting substrate 43 rises, stress acts on the solder electrode 11C that connects the two. For example, in the case of FIG. 18 where the semiconductor device is soldered only with the external connection electrodes, the magnitude of this stress increases as the package size increases. Specifically, it is proportional to the distance from the center of the semiconductor element to the periphery of the semiconductor device.
[0087]
In the present application, the stress can be relieved by making the stress buffering electrode 11E substantially the same size as the semiconductor element 12. The region is firmly fixed to the mounting substrate by the stress buffering electrode 11E. Accordingly, the stress acting on the external connection electrode 11C is proportional to the distance from the stress buffering electrode 11E to the center of the external connection electrode 11C. As a result of the stress simulation, the maximum stress applied to the external connection electrode 11C by about 25 to 30% is reduced. Therefore, it is possible to prevent cracks from occurring in the external connection electrode 11C. The stress buffering electrode may be slightly larger or slightly smaller than the semiconductor element 12.
[0088]
FIG. 16 is a graph showing the relationship between the number of cycles (horizontal axis) and the crack generation rate (vertical axis) in the heat cycle test. Here, the method of the heat cycle test will be described. First, a semiconductor device mounted on a mounting substrate via a solder electrode is exposed to the gas phase. Next, the temperature of the gas phase is changed, and the number of semiconductor devices in which cracks have occurred in the solder electrodes due to the temperature change is measured. By performing the above operation, it is possible to evaluate the lifetime of the solder electrode with respect to temperature change. In addition, the range of the temperature change of a gaseous phase is -40 degreeC-125 degreeC, and the time of 1 cycle is about 1 hour.
[0089]
The structure of case 1 and case 2 in FIG. 16 will be described below.
[0090]
Case 1: The solder structure provided on the back surface of the semiconductor device of FIG. 10 has the same size of the heat radiation electrode as the back surface of the bonding pad exposed through the insulating film. Therefore, a large number of solder is provided on the exposed portion of the heat radiation electrode, and the solder electrode is mounted on the mounting substrate.
[0091]
Case 2: In Case 1, the back surface of the heat radiation electrode is exposed over substantially the entire area, and the heat radiation electrode and the electrode of the mounting substrate are fixed all over. That is, the mounting structure shown in FIG.
[0092]
In case 1, the crack generation rate increased from the time when the number of cycles exceeded 250, and the crack generation rate reached 100% when the number of cycles reached 400. In other words, when the number of cycles reaches 400, cracks have occurred in the solder electrodes of all the semiconductor devices.
[0093]
In Case 2, the crack generation rate increased from the time when the number of cycles exceeded 450, and the crack generation rate reached 100% when the number of cycles reached 600.
[0094]
From this, it can be said that the semiconductor device of case 2 has a structure in which solder cracks are less likely to occur than the semiconductor device of case 1. Therefore, it is more effective to use a large solder electrode having substantially the same size as the chip as the stress buffering electrode. This is because the distance between the solder electrodes is shortened as described above.
[0095]
Here, the solder electrode is made of a solder material, but the material here may be a generally-known brazing material, a conductive paste such as Ag or gold, or a conductive adhesive. The material for fixing the heat radiation electrode and the mounting substrate may be an insulating adhesive as long as the heat radiation electrode 11D is not electrically connected to the chip back surface.
Fifth embodiment for explaining a semiconductor device
A semiconductor device according to the present embodiment is shown in FIG. FIG. 12A is a plan view thereof, and FIG. 12B is a cross-sectional view taken along line AA when the semiconductor device 51 is mounted on the mounting substrate 43.
[0096]
As shown in FIGS. 12A and 12B, the semiconductor device 51 is characterized in that a stress releasing electrode 11 </ b> F is provided on the heat radiating electrode 11 </ b> D divided by the groove 44. That is, the back surface of the semiconductor device 51 and the mounting substrate 43 are firmly coupled to each other via the stress buffering electrode 11F. Therefore, the stress acting on the external connection solder electrode 11C is proportional to the distance from the periphery of the stress buffering electrode 11D to the central portion of the external connection electrode 11C. Therefore, when the semiconductor device 51 is thermally expanded, the stress acting on the external connection electrode 11C can be buffered, and cracks can be prevented from occurring in the external connection electrode 11C.
[0097]
Furthermore, by providing the groove 44, the adhesive force between the insulating adhesive means AD and the heat radiation electrode 11D can be improved.
[0098]
In addition, although the cycle test of this structure was not implemented, it seems that the effect equivalent to the structure of FIG. 11 generate | occur | produces. The number of divisions of the stress buffer electrode 11F is about 2 to 8 at most. By performing this division, the amount (thickness) of the applied solder is reduced and the mountability is improved as compared with a structure in which the entire surface is solidly fixed.
Sixth embodiment for explaining a semiconductor device
A semiconductor device according to the present embodiment is shown in FIG. FIG. 13A is a plan view thereof, and FIG. 13B is a cross-sectional view taken along line AA when the semiconductor device 52 is mounted on the mounting substrate 43.
[0099]
As shown in FIG. 13A, the feature of this semiconductor device is that the external connection electrode 13C has an elongated shape. Again, there are two causes of stress buffering.
The first is that the adhesion area of the external connection electrode 11C has increased.
Secondly, since the crack generation point CK is generated on the outer peripheral portion of the solder and on the semiconductor element side, the separation distance of the generation point CK is shortened.
[0100]
Considering prevention of solder bridges between the electrodes, the distance between the heat radiation electrode 11D and the bonding pad 11A needs to be about 0.3 m. In the drawing, since the number of bonding pads 11A is small, a square shape is possible. However, when a bonding pad having more than 200 pins is required, the width of the bonding pad needs to be narrowed. Therefore, the shape of the bonding pad 11A inevitably becomes an elongated shape.
[0101]
As a result, the adhesion area increases, and at the same time, the occurrence of cracks is on the inside, and the occurrence of cracks is suppressed.
Seventh embodiment for explaining a semiconductor device
A semiconductor device according to the present embodiment is shown in FIGS. FIG. 14A is a plan view thereof, and FIG. 14B is a cross-sectional view taken along line AA when the semiconductor device 53 is mounted on the mounting substrate 43. 15A to 15C show the structure of the external connection electrode 11C.
[0102]
As shown in FIGS. 15A and 15B, the semiconductor device 53 is characterized by the structure of the external connection electrode 11C. The problem is that, as shown in FIG. 15C, the insulating coating 16 hits the surface of the solder and does not form a constriction NK. As long as the external connection electrode 11C does not have a constriction NK, the structure shown in FIGS. 15A and 15B may be used.
[0103]
It has been found that this constricted NK tends to concentrate stress, and therefore easily generates cracks. In addition, in a thin package having a thickness of 0.5 mm or less, the composition ratio of the insulating resin is small with respect to the constituent material of the semiconductor device because it is thin, and in an extreme case, the semiconductor element 12 is directly attached. . Since the thermal expansion coefficient of silicon, which is the material of the semiconductor element 12, and the mounting substrate are greatly different, the stress acting on the solder electrode 11C connecting the two becomes large. Therefore, in all the embodiments of the present invention, it is important that the solder surface has a smooth curved surface without constriction.
[0104]
Next, the results of the heat cycle test will be described with reference to FIG. First, the structure of the semiconductor device used for the tests of case 3 and case 4 will be described.
[0105]
The external connection electrodes of the semiconductor devices of both the case 3 and the case 4 also have a structure having no constriction. The difference between the two lies in the structure of the stress buffer electrode. The stress buffer electrodes of the semiconductor device of case 3 are provided with a plurality of electrodes having the same size as the external connection electrodes. The stress buffering electrode of the semiconductor device of the case 4 has the same size as the semiconductor element.
[0106]
Case 3 is currently under test, but no solder cracks have occurred even if the number of cycles exceeds 750 times.
[0107]
In case 4, the crack occurrence rate is 0% even when the number of cycles reaches 1400. That is, no cracks are generated in the solder electrode even when the number of cycles is 1400.
[0108]
Next, the difference in structure between Case 1 to Case 4 will be described.
[0109]
The difference in structure between case 1 and case 2 is the shape of the electrode for stress buffering. The stress buffering electrode of the case 1 is the same size as the external connection electrode 11C. On the other hand, the stress buffer electrode of the case 2 has almost the same size as the semiconductor element. That is, the stress buffering electrode of the case 2 is larger than the case 1.
[0110]
The difference in structure between case 1 and case 3 is the shape of the external connection electrode. The external connection electrode of the case 1 has a circular structure with a constriction. On the other hand, the external connection electrode of the case 2 has a long and narrow structure.
[0111]
The difference between the structures of the case 2 and the case 4 is that both have stress buffering electrodes having a size almost equal to that of the semiconductor element, but are in the shape of external connection electrodes. The external connection electrode of the case 2 has a circular structure with a constriction. On the other hand, the external connection electrode of the case 4 has a long and narrow structure.
[0112]
From this, it can be seen that solder cracks can be prevented by combining the two characteristics of the shape of the stress buffer electrode and the shape of the external connection electrode. In other words, the size of the stress buffering electrode is set to the same size as that of the semiconductor element, the shape of the external connection electrode is elongated, and the shape is not constricted.
[0113]
As described above, the feature of the present invention is that the heat radiation electrode 11D, which was originally effective as a heat radiation electrode, is firmly fixed to the mounting substrate through solder, so that the external connection electrode It was found to be effective in preventing cracks.
[0114]
Further, it has been found that the strength of the external connection electrode can be improved by making the external connection electrode without a constriction.
[0115]
This realizes a significant improvement in mountability of thin packages and greatly contributes to the practical use of light, thin and small packages.
[0116]
In all the above-described embodiments, the insulating adhesive means AD is used as the adhesive means between the semiconductor element 12 and the heat radiation electrode 11D. However, this bonding means is not limited to insulating. If the back electrode of the semiconductor device is not short-circuited, conductive adhesive means may be used.
[0117]
【The invention's effect】
As is clear from the above description, in the present invention, the semiconductor element can be improved in performance by mounting the semiconductor element face-down and employing a heat radiation means or a heat radiation electrode.
[0118]
In particular, if the electrode for heat dissipation is connected to the second circuit pattern of the mounting substrate, it can be emitted through this second circuit pattern. Therefore, the heat of the entire semiconductor module can be reduced, and the ability of other elements separately attached to the module can be improved.
[0119]
Further, by forming the flow preventing film on the conductive pattern, the electrical connection means does not flow along the conductive pattern, and the shape and thickness of the electrical connection means can be controlled. Therefore, after the semiconductor element and the conductive pattern are connected via the electrical connection means, cleaning between them can be performed. In addition, since the gap is not narrowed, it is possible to enter an insulating resin having fluidity.
[0120]
In addition, the circuit device is configured with a minimum of conductive patterns, semiconductor elements, and insulating resin, so that resources are not wasted. Therefore, there can be realized a semiconductor device and a module that do not have extra components until completion and can greatly reduce the cost.
[0121]
Furthermore, in the semiconductor device of the present invention, the stress acting on the external connection electrode can be reduced by providing a stress buffering electrode having the same size as the semiconductor element on the back surface of the pad at the center. This can prevent the occurrence of solder cracks.
[0122]
Furthermore, the semiconductor device of the present invention can reduce the stress acting on the solder electrode and improve the strength of the solder electrode itself by making the external connection electrode into a slender shape and not having a constriction. be able to. Therefore, solder cracks can be prevented.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a semiconductor module of the present invention.
FIG. 2 is a diagram illustrating the semiconductor device used in FIG.
FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 8 is a diagram illustrating a conductive pattern employed in the semiconductor device of the present invention.
FIG. 9 is a diagram illustrating a semiconductor module of the present invention.
10 is a diagram illustrating the semiconductor device used in FIG. 9;
FIG. 11 is a diagram illustrating a mounting structure of a semiconductor device of the present invention.
FIG. 12 is a diagram illustrating a mounting structure of a semiconductor device of the present invention.
FIG. 13 is a diagram illustrating a mounting structure of a semiconductor device of the present invention.
FIG. 14 is a diagram illustrating a mounting structure of a semiconductor device of the present invention.
FIG. 15 is a diagram illustrating a shape of an external connection electrode of a semiconductor device of the present invention.
FIG. 16 is a diagram for explaining a test result of a heat cycle using the semiconductor device of the present invention.
FIG. 17 illustrates a conventional semiconductor device.
FIG. 18 is a diagram illustrating a conventional semiconductor device.
[Explanation of symbols]
10 Insulating resin
11A pad
11B wiring
11C External connection electrode
11D Heat dissipation electrode
12 Semiconductor elements
13 Bonding electrodes
15 Semiconductor device
16 Insulation coating
17 Exposed area
18 Mounting board
19 Circuit pattern
AF insulating adhesive means
DM flow prevention membrane
SD external connection means
RD heat dissipation means

Claims (5)

A pad provided opposite to the bonding electrode of the semiconductor element, an external connection electrode provided on a wiring electrically connected to the pad, and the pad and the pad connected to each other face-down via an electrical connection means The semiconductor element, an insulating resin that seals the semiconductor element so that the back surface of the external connection electrode is exposed and integrated, and heat dissipation means provided on the back surface side of the semiconductor element,
A semiconductor device, wherein a conductive film made of a different material is provided on an upper surface of the pad, and an eaves made of the conductive film is provided. The semiconductor device according to claim 1 , wherein a heat radiation electrode is disposed under the semiconductor element in a region surrounded by the pad. 3. The semiconductor device according to claim 1, wherein a back surface of the semiconductor element is exposed from an insulating resin, and the heat dissipating means is attached directly or insulated from the back surface of the semiconductor element.   The semiconductor device according to claim 1, wherein the electrical connection means is made of a brazing material.   The semiconductor device according to claim 1, wherein the conductive film is made of nickel, silver, gold, or palladium.

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