CN105161432A - Chip packaging method - Google Patents
Chip packaging method Download PDFInfo
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- CN105161432A CN105161432A CN201510596161.6A CN201510596161A CN105161432A CN 105161432 A CN105161432 A CN 105161432A CN 201510596161 A CN201510596161 A CN 201510596161A CN 105161432 A CN105161432 A CN 105161432A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 140
- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000010410 layer Substances 0.000 claims abstract description 217
- 239000004033 plastic Substances 0.000 claims abstract description 103
- 229920003023 plastic Polymers 0.000 claims abstract description 103
- 239000002184 metal Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000012790 adhesive layer Substances 0.000 claims abstract description 30
- 238000007639 printing Methods 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 40
- 239000000843 powder Substances 0.000 claims description 33
- 238000000354 decomposition reaction Methods 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 230000004927 fusion Effects 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 238000007493 shaping process Methods 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 7
- 239000007921 spray Substances 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920001971 elastomer Polymers 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000005060 rubber Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 13
- 238000001259 photo etching Methods 0.000 abstract description 9
- 230000008021 deposition Effects 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 6
- 238000010146 3D printing Methods 0.000 abstract 2
- 238000002161 passivation Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000003292 glue Substances 0.000 description 5
- 238000000227 grinding Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000010992 reflux Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000110 selective laser sintering Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000013536 elastomeric material Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004372 laser cladding Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000013178 mathematical model Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Laser Beam Processing (AREA)
Abstract
The invention provides a chip packaging method which comprises the following steps: providing a carrier, and forming an adhesive layer on the surface of the carrier; pasting at least one chip on the adhesive layer, wherein the front surface of the chip faces up; and printing a plastic package layer covering the chip and a redistribution lead layer electrically connected with the chip on the surface of the carrier through a 3D printing method, wherein the redistribution lead layer comprises conductive columns running through the plastic package layer and corresponding to electrical lead of the chip, and metal circuits distributed on the surface of the plastic package layer and connected with the conductive columns. The chip packaging method adopts the 3D printing method to replace the photoetching and etching steps of a through hole, and replace the process steps of photoetching and etching and electroplate deposition and the like of the metal circuits, thereby greatly reducing process complexity. According to the chip packaging method, after removing the carrier and the plastic package layer, the back surface of the chip has no unnecessary plastic package layer, so that the final packaged body is allowed to be lighter and thinner, and requirement for device miniaturization can be met better.
Description
Technical field
The invention belongs to field of semiconductor package, relate to a kind of chip packaging method.
Background technology
Fan-out-type wafer-level packaging (Fan-outwaferlevelpackaging, FOWLP) is a kind of embedded encapsulation of wafer level processing, is also one of main Advanced Packaging that more, the integrated flexibility of I/O number is good.Fan-out-type Wafer level packaging adopts wafer scale thin film technique, and by distributing, trace layer (RedistributionLayers, RDL) connects chip and outside terminal again, eliminates conventional package substrates.
In fan-out-type wafer-level packaging, chip by suitable material around, encapsulation area occupied expands to beyond chip by these materials.Test passes chip wafer scale molding technology embeds in synthetic plastic wafer (restructuring wafer).Then with the insulation of front road and metallization process, with wafer scale photoetching and drafting method, interconnection is fanned out to peripheral region.Again on wafer, apply soldered ball and carry out concurrent testing.Then restructuring wafer is cut into separate unit, packaging and shipping.During by fan-in method, interconnecting number and their pitch must adapt to chip size.On the contrary, fan-out WLP supports adaptable fan-out area, and butt welding ball-joint is apart from not having anything to limit.
The general process of fan-out-type wafer-level packaging comprises following several step: first cut single microchip from wafer, and adopts standard to pick up the equipment of putting chip front side to be pasted down on the adhesive-layer of carrier; Then form plastic packaging layer, chip is embedded in plastic packaging layer; After the solidification of plastic packaging layer, remove carrier and adhesive-layer, the trace layer technique that then distributes again and plant ball reflux technique, finally carry out cutting and testing.
Traditional fan-out-type Wafer level packaging complex process, it is before the trace layer technique that distributes again, peels off adhesive-layer with exposed chip front, and forms passivation layer in chip front side, then make based on passivation layer the trace layer that distributes again.Passivation layer adds thickness of detector, simultaneously, the effect of plastic packaging layer is only used to fixed chip, after carrier is removed, in the trace layer technique and plant in the process of ball reflux technique of distributing again afterwards, often there is the problems such as bending in capsulation material, thus greatly affects the performance of encapsulating products.
Existing a solution is, semiconductor chip is assemblied in capsulation material with facing up, due to described capsulation material by rigid carrier as support, this method can reduce the follow-up trace layer technique and plant the deformation probability of the capsulation material that ball technique causes of distributing again greatly.But, this method needs to increase if the processing steps such as grinding, thinning plastic packaging layer are with exposed chip front, thus the raising of product cost can be caused, and environmental protection not, and this method needs deposit passivation layer equally and makes based on passivation layer the trace layer that distributes again.
Therefore, how to provide a kind of chip packaging method, to reduce process complexity, enhance productivity and reduce thickness of detector, become the important technological problems that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of chip packaging method, for solving the problem that prior art chips packaging technology is complicated, production efficiency is not high, thickness of detector is thicker.
For achieving the above object and other relevant objects, the invention provides a kind of chip packaging method, comprise the following steps:
One carrier is provided, forms adhesive-layer at described carrier surface;
Described adhesive-layer is pasted at least one chip, and wherein, chip front side upward;
3D impact system is adopted to print the plastic packaging layer covering described chip and the trace layer that distributes again be electrically connected with described chip at described carrier surface; The described trace layer that distributes again comprises and runs through described plastic packaging layer and electrically draw corresponding conductive pole with described chip, and is distributed in described plastic packaging layer surface and the metallic circuit be connected with described conductive pole.
Alternatively, first print described plastic packaging layer, distribute described in then printing trace layer again; Wherein, after described plastic packaging layer prints, wherein there is the through hole holding described conductive pole.
Alternatively, distribute described in the printing of employing Engineered Net Shaping Aftertreatment trace layer again.
Alternatively, described conductive pole and described metallic circuit print respectively, comprise the steps:
Adopt shower nozzle metal injection powder in described through hole, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Described conductive pole is formed after molten metal powder forming;
Adopt shower nozzle according to predetermined paths at described plastic packaging layer surface metal injection powder, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Described metallic circuit is formed after molten metal powder forming.
Alternatively, described conductive pole and described metallic circuit isochronous printing, comprise the steps:
Adopt shower nozzle according to predetermined paths metal injection powder in described plastic packaging layer surface and described through hole, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Wherein, after being positioned at described through hole molten metal powder forming, form described conductive pole, after being positioned at the shaping of metal powders of described plastic packaging layer surface melting, form described metallic circuit.
Alternatively, isochronous printing goes out described plastic packaging layer and the described trace layer that distributes again.
Alternatively, the composite bed be made up of described plastic packaging layer and the described trace layer that distributes again is decomposed at least two-layer and successively prints from bottom to top; Wherein, for the decomposition layer only comprising plastic packaging layer material, adopt the first shower nozzle to spray plastic packaging layer material according to predetermined paths and obtain; For the decomposition layer comprising plastic packaging layer material and metal material simultaneously, replace employing first shower nozzle according to predetermined paths and spray plastic packaging layer material and the second shower nozzle metal injection material and obtain.
Alternatively, described plastic packaging layer surface is formed with the groove corresponding with described metallic circuit, and described metallic circuit is embedded in described groove.
Alternatively, form ubm layer on the described trace layer surface that distributes again further, and form solder bumps on described ubm layer surface.
Alternatively, described carrier and described adhesive-layer is removed further.
Alternatively, the material of described plastic packaging layer comprises epoxy resin, rubber or polyimides.
Alternatively, described carrier comprises metal, wafer, glass or organic material.
As mentioned above, chip packaging method of the present invention, there is following beneficial effect: 1) the present invention is by being pasted on chip front side on the adhesive-layer of carrier, and adopts 3D impact system to print the plastic packaging layer covering described chip and the trace layer that distributes again be electrically connected with described chip at described carrier surface upward.Because the trace layer that distributes again is formed when carrier is unstripped, effectively reduce and distribute trace layer technique again and plant the deformation probability of the capsulation material that ball technique causes.2) in chip packaging method of the present invention, the trace layer that distributes again is directly printed in plastic packaging layer, thus eliminate grinding, the reduction steps of the deposition step of passivation layer and plastic packaging layer, not only reduce the risk that chip front side is damaged in planarization process, also reduce production cost.3) chip packaging method of the present invention adopts 3D impact system to instead of photoetching, the etch step of through hole, and instead of the processing steps such as the photoetching of metallic circuit, etching and electroplating deposition, greatly reduces process complexity.4) chip packaging method of the present invention is after removal carrier and plastic packaging layer, and chip back does not have unnecessary plastic packaging layer, makes final packaging body more frivolous, better meets the requirement of device miniaturization.5) metallic circuit of the trace layer that distributes again of the present invention's making both can protrude from plastic packaging layer surface, and also can be embedded in the groove on plastic packaging layer surface, reliability is higher.
Accompanying drawing explanation
Fig. 1 is shown as the process chart of chip packaging method of the present invention.
Fig. 2 ~ Figure 13 is shown as the structural representation that each step of chip packaging method of the present invention presents.
Element numbers explanation
S1 ~ S3 step
1 carrier
2 adhesive-layers
3 chips
4 plastic packaging layers
5 distribute trace layer again
51 conductive poles
52 metallic circuits
6 through holes
7 ubm layers
8 solder bumps
I, II, III decomposition layer
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Figure 13.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
The invention provides a kind of chip packaging method, refer to Fig. 1, be shown as the process chart of the method, comprise the following steps:
S1: provide a carrier, forms adhesive-layer in described carrier disk surfaces;
S2: paste at least one chip on described adhesive-layer, wherein, chip front side is upward;
S3: adopt 3D impact system to print the plastic packaging layer covering described chip and the trace layer that distributes again be electrically connected with described chip at described carrier surface; The described trace layer that distributes again comprises and runs through described plastic packaging layer and electrically draw corresponding conductive pole with described chip, and is distributed in described plastic packaging layer surface and the metallic circuit be connected with described conductive pole.
First refer to Fig. 2, perform step S1: provide a carrier 1, form adhesive-layer 2 on described carrier 1 surface.
Concrete, the effect of described carrier 1 is for described adhesive-layer 2 and follow-up plastic packaging layer 4 provide structure or the matrix of rigidity.Described carrier 1 can be selected but be not limited to metal, wafer, glass or organic material etc.Exemplarily, described carrier 1 selects glass.Described carrier 1 can be disk or other shape.
The effect of described adhesive-layer 2 is fixed chips, and to ensure that chip can not produce the situations such as mobile in subsequent technique, and described adhesive-layer 2 and described carrier 1 also have stronger adhesion.In general, described adhesive-layer 2 needs to be greater than the adhesion with chip with the adhesion of carrier 1, described adhesive-layer 2 in follow-up technique for the separating layer between chip and carrier 1.Exemplarily, described adhesive-layer 3 selects UV adhesive glue, is formed at described carrier 1 surface by spin coating proceeding.In other embodiments, described adhesive-layer 3 also can select other suitable jointing material, should too not limit the scope of the invention herein.
Then refer to Fig. 3, perform step S2: on described adhesive-layer, paste at least one chip, wherein, chip front side upward.
Chip front side refers to that chip 3 is formed with the one side of device and electrode extraction herein.Discrete arrangement between each chip 3 and keeping at a certain distance away, thinks that the follow-up making distributing trace layer again provides fan-out space and cutting room.
Refer to Fig. 4 again, perform step S3: adopt the plastic packaging layer 4 that 3D impact system goes out to cover described chip 3 at described carrier 1 printout surface and the trace layer 5 that distributes again be electrically connected with described chip 3; The described trace layer 5 that distributes again comprises and runs through described plastic packaging layer 4 and electrically draw corresponding conductive pole 51 with described chip 3, and is distributed in described plastic packaging layer 4 surface and the metallic circuit 52 be connected with described conductive pole 51.
3D impact system is the one of rapid shaping technique, and it is a kind of based on mathematical model file, uses powdery metal or plastics etc. can jointing material, is carried out the technology of constructed object by the mode successively printed.3D prints substantially identical with common print operation principle, and printer, built with liquid or powder etc. " printed material ", after being connected, is stacked up " printed material " by conputer controlled from level to level with computer, finally the blueprint on computer is become in kind.
Exemplarily, first print described plastic packaging layer 4, and then the trace layer 5 that distributes again described in printing.As shown in Figure 5, after described plastic packaging layer 4 prints, wherein there is the through hole 6 holding described conductive pole 51.
Concrete, the material of described plastic packaging layer 4 includes but not limited to epoxy resin, rubber or polyimides etc.Exemplarily, described plastic packaging layer 4 select elastomeric material.Adopt shower nozzle, according to predetermined paths, the plastic packaging layer material of molten state is ejected the described plastic packaging layer 4 of formation.In another embodiment, powdered form also can be adopted to be sprayed by plastic packaging layer material, and adopt glue (such as acrylic UV is without shadow glue) to be bonded by the plastic packaging layer material of powdered form, wherein, glue also adopts shower nozzle to spray.
Concrete, distribute described in employing Engineered Net Shaping Aftertreatment prints trace layer 5 again.Engineered Net Shaping Aftertreatment (LaserEngineeredNetShaping, LENS) be a kind of new RP technique, selective laser sintering (SLS) technology and laser melting coating (LaserCladding) technology combine by it, obtain fast density and all higher metal parts of intensity.Laser energizing system is generally made up of four parts: computer, superpower laser, metal dust shower nozzle and X-Y workbench.Wherein, computer sets up the CAD physical model of metallic circuit for the preproduction phase that is shaped at metallic circuit, and convert this CAD physical model to stl file, slicing treatment is carried out to the stl file of part, generates a series of track while scan with certain thickness thin layer and every skim; Computer also for the formed machining stage to system in each parts (comprise laser optical gate, correct optical switch, protection gas air valve, showerhead electrode and X-Y table motor etc.) carry out under same instruction orderly control, complete the course of processing of metallic circuit.In laser energizing system, laser direct deposite metal powder, realizes cladding effect, therefore requires to adopt superpower laser.Exemplarily, described laser can adopt Nd:YAG high power solid pulse laser or carbon dioxide laser.Metal dust shower nozzle is used for metal dust pointwise by-line metal injection powder, member metal circuit.X-Y workbench is used for realizing flat scanning motion, and specific practice is fixed on the cantilever of X-Y workbench by laser head, makes laser head do plane motion with workbench, realizes pointwise by-line laser melting coating until obtain a cladding cross section.
The described material distributing trace layer 5 again includes but not limited to Au, Ag, Cu or Cu alloy.
Exemplarily, described conductive pole 51 prints respectively with described metallic circuit 52, comprises the steps:
1) as shown in Figure 6, adopt shower nozzle metal injection powder in described through hole 6, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Described conductive pole 51 is formed after molten metal powder forming;
2) as shown in Figure 7, adopt shower nozzle according to predetermined paths at described plastic packaging layer surface metal injection powder, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Described metallic circuit 52 is formed after molten metal powder forming.
It is pointed out that described step 1) with step 2) order interchangeable.
In the present embodiment, first adopt and print described plastic packaging layer 4, and then the trace layer 5 that distributes again described in printing.And the trace layer 5 that distributes again described in printing also is divided into two steps, namely described conductive pole 51 prints respectively with described metallic circuit 52.
In chip packaging method of the present invention, the trace layer that distributes again is directly printed in plastic packaging layer, thus eliminate grinding, the reduction steps of the deposition step of passivation layer and plastic packaging layer, not only reduce the risk that chip front side is damaged in planarization process, also reduce production cost.Chip packaging method of the present invention adopts 3D impact system to instead of photoetching, the etch step of through hole, and instead of the processing steps such as the photoetching of metallic circuit, etching and electroplating deposition, greatly reduces process complexity.
Embodiment two
The present embodiment adopts substantially identical technical scheme with embodiment one, difference is, in embodiment one, conductive pole 51 and the metallic circuit 52 of the described trace layer 5 that distributes again print respectively, and in the present embodiment, described conductive pole 51 is isochronous printings with described metallic circuit 52.
Exemplarily, described in isochronous printing, conductive pole 51 and described metallic circuit 52 comprise the steps:
Adopt shower nozzle according to predetermined paths metal injection powder in described plastic packaging layer 4 surface and described through hole 6, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Wherein, form described conductive pole 51 after being positioned at described through hole 6 molten metal powder forming, after being positioned at the shaping of metal powders of described plastic packaging layer surface melting, form described metallic circuit 52.
Embodiment three
The present embodiment adopts substantially identical technical scheme with embodiment one or two, difference is, in embodiment one, described plastic packaging layer 4 prints respectively with the described trace layer 5 that distributes again, and in the present embodiment, described plastic packaging layer 4 and described trace layer 5 isochronous printing that distributes again.
Concrete, the composite bed be made up of described plastic packaging layer 4 and the described trace layer 5 that distributes again is decomposed at least two-layer and successively prints from bottom to top; Wherein, for the decomposition layer only comprising plastic packaging layer material, adopt the first shower nozzle to spray plastic packaging layer material according to predetermined paths and obtain; For the decomposition layer comprising plastic packaging layer material and metal material simultaneously, replace employing first shower nozzle according to predetermined paths and spray plastic packaging layer material and the second shower nozzle metal injection material and obtain.
Exemplarily, as shown in Figure 8, the composite bed be made up of described plastic packaging layer 4 and the described trace layer 5 that distributes again is decomposed into three layers, be respectively decomposition layer I, decomposition layer II and decomposition layer III from bottom to top, wherein, decomposition layer I only comprises plastic packaging layer material, and decomposition layer II comprises plastic packaging layer material and metal material simultaneously, and decomposition layer III only comprises metal material.By controlling the parameters such as the motion path of shower nozzle and laser head and emitted dose, completing the printing of each layer, obtaining the composite bed be made up of described plastic packaging layer 4 and the described trace layer 5 that distributes again.Certainly, each decomposition layer is also decomposed into the thinner thin layer of multiple thickness further, is obtained by repeatedly duplicate printing thin layer.
Embodiment four
The present embodiment adopts substantially identical technical scheme with embodiment one, two or three, difference is, in embodiment one, two and three, the metallic circuit of the trace layer that distributes again protrudes from plastic packaging layer surface, and in the present embodiment, the metallic circuit of the trace layer that distributes again is embedded in the groove on plastic packaging layer surface, and reliability is higher.
As shown in Figure 9, described plastic packaging layer 4 surface is formed with the groove corresponding with described metallic circuit 52, and described metallic circuit 52 is embedded in described groove.
In the present embodiment, described plastic packaging layer 4 can print respectively with the described trace layer 5 that distributes again, and concrete steps see embodiment one or embodiment two, can repeat no more herein.
In the present embodiment, described plastic packaging layer 4 also can isochronous printing with the described trace layer 5 that distributes again, the composite bed be made up of described plastic packaging layer 4 and the described trace layer 5 that distributes again can be decomposed into three layers as shown in Figure 10, be respectively decomposition layer I, decomposition layer II and decomposition layer III from bottom to top, wherein, decomposition layer I only comprises plastic packaging layer material, and decomposition layer II and decomposition layer III comprises plastic packaging layer material and metal material all simultaneously.By controlling the parameters such as the motion path of shower nozzle and laser head and emitted dose, completing the printing of each layer, obtaining the composite bed be made up of described plastic packaging layer 4 and the described trace layer 5 that distributes again.
Embodiment five
As shown in figure 11, the present embodiment, on the basis of embodiment one, two, three or four, forms ubm layer 7 on described trace layer 5 surface that distributes again further, and forms solder bumps 9 on described ubm layer 7 surface.
Concrete, a dielectric layer (not shown) can be formed on described trace layer 5 surface that distributes again in advance, and obtain ubm layer 7 by the method such as optical mask, etching in the dielectric layer; Ubm layer 7 embeds in dielectric layer, is connected with wiring lead layer 5 again; The end face of ubm layer can with the either flush of dielectric layer, also can protrude from the surface of dielectric layer.Described solder bumps 8 can adopt plant ball reflux technique obtain.
Because the trace layer that distributes again is formed when carrier is unstripped, therefore, the present invention effectively can reduce and distributes trace layer technique again and plant the deformation probability of the capsulation material that ball technique causes, and improves chip package performance.
As shown in FIG. 12 and 13, in the present invention, described carrier 1 and described adhesive-layer 2 can be removed further.
Concrete, adopt exposure method to make described adhesive-layer 2 (UV adhesive glue) reduce stickiness, to realize it with described plastic packaging layer 4 and being separated, finally to remove described carrier 1 and adhesive-layer 2 of chip 3.Certainly, when described adhesive-layer 2 adopts other material, other corresponding method can be adopted to peel off described carrier and adhesive-layer 2, should too not limit the scope of the invention herein.
The present invention is after removal carrier and plastic packaging layer, and chip back does not have unnecessary plastic packaging layer, makes final packaging body more frivolous, better meets the requirement of device miniaturization.
In sum, chip packaging method of the present invention, there is following beneficial effect: 1) the present invention is by being pasted on chip front side on the adhesive-layer of carrier, and adopts 3D impact system to print the plastic packaging layer covering described chip and the trace layer that distributes again be electrically connected with described chip at described carrier surface upward.Because the trace layer that distributes again is formed when carrier is unstripped, effectively reduce and distribute trace layer technique again and plant the deformation probability of the capsulation material that ball technique causes.2) in chip packaging method of the present invention, the trace layer that distributes again is directly printed in plastic packaging layer, thus eliminate grinding, the reduction steps of the deposition step of passivation layer and plastic packaging layer, not only reduce the risk that chip front side is damaged in planarization process, also reduce production cost.3) chip packaging method of the present invention adopts 3D impact system to instead of photoetching, the etch step of through hole, and instead of the processing steps such as the photoetching of metallic circuit, etching and electroplating deposition, greatly reduces process complexity.4) chip packaging method of the present invention is after removal carrier and plastic packaging layer, and chip back does not have unnecessary plastic packaging layer, makes final packaging body more frivolous, better meets the requirement of device miniaturization.5) metallic circuit of the trace layer that distributes again of the present invention's making both can protrude from plastic packaging layer surface, and also can be embedded in the groove on plastic packaging layer surface, reliability is higher.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (12)
1. a chip packaging method, is characterized in that, comprises the following steps:
One carrier is provided, forms adhesive-layer at described carrier surface;
Described adhesive-layer is pasted at least one chip, and wherein, chip front side upward;
3D impact system is adopted to print the plastic packaging layer covering described chip and the trace layer that distributes again be electrically connected with described chip at described carrier surface; The described trace layer that distributes again comprises and runs through described plastic packaging layer and electrically draw corresponding conductive pole with described chip, and is distributed in described plastic packaging layer surface and the metallic circuit be connected with described conductive pole.
2. chip packaging method according to claim 1, is characterized in that: first print described plastic packaging layer, and distribute described in then printing trace layer again; Wherein, after described plastic packaging layer prints, wherein there is the through hole holding described conductive pole.
3. chip packaging method according to claim 2, is characterized in that: distribute described in employing Engineered Net Shaping Aftertreatment prints trace layer again.
4. chip packaging method according to claim 3, is characterized in that: described conductive pole and described metallic circuit print respectively, comprise the steps:
Adopt shower nozzle metal injection powder in described through hole, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Described conductive pole is formed after molten metal powder forming;
Adopt shower nozzle according to predetermined paths at described plastic packaging layer surface metal injection powder, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Described metallic circuit is formed after molten metal powder forming.
5. chip packaging method according to claim 3, is characterized in that: described conductive pole and described metallic circuit isochronous printing, comprise the steps:
Adopt shower nozzle according to predetermined paths metal injection powder in described plastic packaging layer surface and described through hole, and the synchronous laser launched by laser emitting head is by fusion of metal powder; Wherein, after being positioned at described through hole molten metal powder forming, form described conductive pole, after being positioned at the shaping of metal powders of described plastic packaging layer surface melting, form described metallic circuit.
6. chip packaging method according to claim 1, is characterized in that: isochronous printing goes out described plastic packaging layer and the described trace layer that distributes again.
7. chip packaging method according to claim 6, is characterized in that: the composite bed be made up of described plastic packaging layer and the described trace layer that distributes again is decomposed at least two-layer and is successively printed from bottom to top; Wherein, for the decomposition layer only comprising plastic packaging layer material, adopt the first shower nozzle to spray plastic packaging layer material according to predetermined paths and obtain; For the decomposition layer comprising plastic packaging layer material and metal material simultaneously, replace employing first shower nozzle according to predetermined paths and spray plastic packaging layer material and the second shower nozzle metal injection material and obtain.
8. chip packaging method according to claim 1, is characterized in that: described plastic packaging layer surface is formed with the groove corresponding with described metallic circuit, and described metallic circuit is embedded in described groove.
9. chip packaging method according to claim 1, is characterized in that: form ubm layer on the described trace layer surface that distributes again further, and form solder bumps on described ubm layer surface.
10. chip packaging method according to claim 9, is characterized in that: remove described carrier and described adhesive-layer further.
11. chip packaging methods according to claim 1, is characterized in that: the material of described plastic packaging layer comprises epoxy resin, rubber or polyimides.
12. chip packaging methods according to claim 1, is characterized in that: described carrier comprises metal, wafer, glass or organic material.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510596161.6A CN105161432A (en) | 2015-09-17 | 2015-09-17 | Chip packaging method |
| PCT/CN2016/082778 WO2017045421A1 (en) | 2015-09-17 | 2016-05-20 | Chip packaging method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510596161.6A CN105161432A (en) | 2015-09-17 | 2015-09-17 | Chip packaging method |
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| CN105161432A true CN105161432A (en) | 2015-12-16 |
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| CN201510596161.6A Pending CN105161432A (en) | 2015-09-17 | 2015-09-17 | Chip packaging method |
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| CN (1) | CN105161432A (en) |
| WO (1) | WO2017045421A1 (en) |
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