CN113257692B - Manufacturing method of semiconductor packaging structure and semiconductor packaging structure - Google Patents

Manufacturing method of semiconductor packaging structure and semiconductor packaging structure Download PDF

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Publication number
CN113257692B
CN113257692B CN202110510989.0A CN202110510989A CN113257692B CN 113257692 B CN113257692 B CN 113257692B CN 202110510989 A CN202110510989 A CN 202110510989A CN 113257692 B CN113257692 B CN 113257692B
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chip
chips
wafer
array
film
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CN113257692A (en
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黄真瑞
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Chengdu Yicheng Technology Co ltd
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Chengdu Yicheng Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The application discloses a semiconductor packaging structure manufacturing method and a semiconductor packaging structure, comprising the following steps: the method comprises the steps of providing a wafer comprising a plurality of chips to be packaged, manufacturing a first rewiring layer for each chip on one side of the wafer, cutting the wafer to obtain a chip array formed by a plurality of chips distributed at preset intervals, arranging the chip array on a chip carrier, performing plastic packaging on the chip array, removing the chip carrier and cutting the chip array to obtain a plurality of manufactured semiconductor plastic packaging structures, and compared with the prior art that the arrangement of an electronic circuit layer is performed after the wafer is cut, the arrangement of the electronic circuit layer can cause the occurrence of high-low displacement difference between the electronic circuit layers of the chips, thereby causing the problem that the specifications of products obtained after the subsequent plastic packaging cutting are inconsistent.

Description

Manufacturing method of semiconductor packaging structure and semiconductor packaging structure
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure manufacturing method and a semiconductor packaging structure.
Background
At present, in the manufacturing process of a semiconductor packaging structure, dicing is generally performed after a wafer is provided, a plurality of chips obtained by dicing are arranged by using a chip mounting process after dicing is completed, and then a plastic packaging process is used for plastic packaging, and then a circuit layer is manufactured. Because of the multiple processes before the circuit layer is manufactured, it is difficult to avoid the deviation of high and low displacement between the circuit layers for manufacturing multiple chips, and thus the problem of inconsistent specifications of the produced products may be caused.
Disclosure of Invention
The application provides a semiconductor packaging structure manufacturing method and a semiconductor packaging structure, which can be used for performing processes such as plastic packaging, cutting and the like after manufacturing an electronic circuit layer and solving the problem that high-low displacement deviation can occur between circuit layers of a plurality of chips.
In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor package structure, including:
providing a wafer, wherein the wafer comprises a plurality of chips to be packaged;
manufacturing a first rewiring layer for each chip on one side of a wafer;
cutting the wafer to obtain a chip array consisting of a plurality of chips distributed according to preset intervals;
manufacturing a chip carrier on one side of the chip array where the first rewiring layer is located;
performing plastic packaging on the chip array based on the chip carrier to form a plastic packaging body for protecting each chip;
and removing the chip carrier, and cutting the chip array by taking each chip as a unit to obtain a plurality of manufactured semiconductor packaging structures.
In one possible implementation manner, dicing the wafer to obtain a chip array composed of a plurality of chips distributed according to a preset interval includes:
cutting the wafer to obtain a plurality of separated chips;
and (3) performing film expansion on the plurality of chips to obtain a chip array consisting of a plurality of chips distributed according to preset intervals.
In one possible embodiment, dicing the wafer to obtain a plurality of separate chips includes:
and adhering the wafer to the dicing film, and dicing based on the dicing film to obtain a plurality of separated chips.
In one possible implementation manner, the film expansion is performed on a plurality of chips to obtain a chip array composed of a plurality of chips distributed according to a preset interval, including:
placing a plurality of separated chips on a bearing film in a film expanding machine, and enabling a cutting film to be in contact with the bearing film;
and (5) performing film expansion on the plurality of chips according to preset intervals by using a film expander to obtain a chip array.
In one possible embodiment, the preset interval is 1um.
In one possible embodiment, the method further comprises:
and manufacturing conductive bumps on the first rewiring layer corresponding to each chip.
In one possible embodiment, the chip carrier is removed, and the chip array is diced for each chip unit to obtain a plurality of semiconductor package structures which are manufactured, including:
removing the chip carrier, and implanting balls into the conductive bumps;
and cutting the chip array by taking each chip as a unit to obtain a plurality of manufactured fan-in semiconductor packaging structures.
In one possible embodiment, the chip carrier is removed, and the chip array is diced for each chip unit to obtain a plurality of semiconductor package structures which are manufactured, including:
removing the chip carrier, manufacturing a conductive bump and a second redistribution layer on one side of the chip array where the first redistribution layer is located, wherein the first redistribution layer and the second redistribution layer are connected through the conductive bump;
ball planting is carried out on the second rewiring layer;
and cutting the chip array by taking each chip as a unit to obtain a plurality of manufactured fan-out type semiconductor packaging structures.
In one possible embodiment, removing the chip carrier includes:
the chip carrier is removed using a laser.
In a second aspect, an embodiment of the present application provides a semiconductor package, which is manufactured by a method for manufacturing a semiconductor package in at least one possible implementation manner of the first aspect.
Compared with the prior art, the application has the beneficial effects that: by providing the wafer comprising a plurality of chips to be packaged, manufacturing a first rewiring layer for each chip on one side of the wafer, cutting the wafer to obtain a chip array formed by a plurality of chips distributed at preset intervals, arranging the chip array on a chip carrier, performing plastic packaging on the chip array to obtain a plastic package body for protecting each chip, removing the chip carrier and cutting the chip array to obtain a plurality of manufactured semiconductor plastic package structures, compared with the conventional semiconductor plastic package structures, the problem that the electronic circuit layers of the chips are different in height displacement after the wafer is cut, and further the problem that the specifications of products obtained after the subsequent plastic package cutting are inconsistent is caused.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described. It is appreciated that the following drawings depict only certain embodiments of the application and are therefore not to be considered limiting of its scope. Other relevant drawings may be made by those of ordinary skill in the art without undue burden from these drawings.
Fig. 1 is a schematic flow chart of steps of a method for manufacturing a semiconductor package according to an embodiment of the present application;
fig. 2 is a schematic diagram of a semiconductor package structure change corresponding to each process of a semiconductor package structure manufacturing method according to an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a semiconductor package structure variation corresponding to each process of another semiconductor package structure manufacturing method according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, or the directions or positional relationships conventionally put in place when the product of the application is used, or the directions or positional relationships conventionally understood by those skilled in the art are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, terms such as "disposed," "connected," and the like are to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
The following describes specific embodiments of the present application in detail with reference to the drawings.
In order to solve the foregoing technical problems in the background art, fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor package according to an embodiment of the disclosure, and the method for manufacturing a semiconductor package is described in detail below.
In step S201, a wafer 1 is provided.
The wafer 1 may include a plurality of chips 10 to be packaged therein.
In step S202, a first redistribution layer 20 for each chip 10 is fabricated on one side of the wafer 1.
In step S203, the wafer 1 is diced to obtain a chip array composed of a plurality of chips 10 distributed at predetermined intervals.
In step S204, the chip carrier 40 is fabricated on the side of the chip array where the first redistribution layer 20 is located.
In step S205, the chip array is encapsulated based on the chip carrier 40, and the encapsulation body 50 for protecting each chip 10 is formed.
In step S206, the chip carrier 40 is removed, and the chip array is diced for each chip 10, so as to obtain a plurality of semiconductor package structures after being fabricated.
Compared to the related art in which the wafer 1 is cut first and then the subsequent electronic circuit layers are fabricated, the scheme provided in the embodiment of the present application can be used to fabricate the electronic circuit layers of each chip 10, such as the re-wiring layer, before the wafer 1 is cut. By the above method, the relative high-low displacement difference between the rewiring layers of each chip 10 can be avoided, and on the basis, the chip arrays formed by the chips 10 distributed according to the preset distance can be uniformly packaged.
Besides adopting a plastic packaging mode, the application can also adopt a film pressing packaging mode to form the plastic packaging body 50 for protecting the chip 10, and can synchronously protect the backboard for bearing the chip 10 no matter which mode is adopted, so that additional process flow is not needed, and equipment and cost are saved.
In one possible implementation, the aforementioned step S203 may be implemented by performing the following steps.
In step S203-1, the wafer 1 is diced to obtain a plurality of separated chips 10.
In the substep S203-2, the plurality of chips 10 are subjected to film expansion to obtain a chip array composed of a plurality of chips 10 distributed at predetermined intervals.
In this embodiment, in order to ensure that the arrangement positions of the chips 10 in the plastic packaging process are more accurate, compared with the chip 10 arrangement performed by using the chip mounting process in the related art, the embodiment of the application uses the film expansion process, and the film expansion process is adopted to further ensure that no high-low displacement difference exists between the chips 10, thereby ensuring the yield of the product manufactured later.
In one possible implementation, the aforementioned substep S203-1 may be implemented by the following example.
(1) The wafer 1 is stuck to a dicing film, and dicing is performed based on the dicing film to obtain a plurality of separated chips 10.
In one possible implementation, the aforementioned substep S203-2 may be implemented by performing the following detailed steps.
(1) A plurality of separated chips 10 are placed on a carrier film in a film expander, and the dicing film is brought into contact with the carrier film.
(2) And (5) performing film expansion on the plurality of chips 10 at preset intervals by using a film expander to obtain a chip array.
The cutting film is not dismantled after the cutting process is finished, but enters the film expander along with a plurality of separated chips 10 and is used as a contact surface with a bearing film in the film expander, the film expander is controlled by a set program to expand the films of the separated chips 10, so that the distance between each chip 10 reaches a preset distance, and compared with the arrangement of the chips 10 in a mode of adopting a patch in the related art, the scheme provided by the application has a shorter flow, and compared with the patch equipment, the use of the film expander is more cost-saving.
In one possible embodiment, the preset interval is 1um.
It should be understood that, the chip 10 is arranged by adopting the film expansion process, so that the distance between the chips 10 and 10 is smaller, the chip 10 is arranged by adopting the chip mounting process in the related art, the distance is generally 80um, and the film expansion process scheme provided by the application can obtain 1um, can cope with smaller cutting lines, so that the number of the chips 10 which can participate in the same batch production is increased. Meanwhile, the embodiment also provides a wider edge wrapping area, so that the structure of a product manufactured later is firmer.
In one possible implementation, the present embodiment provides more methods by which the conductive bumps 30 can also be fabricated on the corresponding first redistribution layer 20 of each chip 10.
In one possible implementation, the aforementioned step S206 may be performed by the following steps.
In step S206-1, the chip carrier 40 is removed and the conductive bump 30 is ball-mounted.
In the substep S206-2, the chip array is diced for each chip 10, so as to obtain a plurality of fan-in semiconductor packages.
On the basis of the above, the fan-in (fanin) semiconductor package structure can be manufactured by the method provided by the application, and when the first redistribution layer 20 is manufactured, the conductive bump 30 for the first redistribution layer 20 can be manufactured synchronously, and then the subsequent processes such as plastic packaging, cutting and the like can be performed. Before the dicing process, the ball mounting operation for the conductive bumps 30 may be uniformly performed, and then dicing may be performed to obtain a plurality of fan-in semiconductor package structures.
In order to clearly describe the solution provided in the embodiments of the present application for manufacturing a plurality of fan-in semiconductor packages, the method described above may be exemplarily described below with reference to fig. 2. First, a wafer 1 including a plurality of chips 10 may be provided. Then, the first rewiring layer 20 and the conductive bumps 30 for each chip 10 are fabricated on one side of the wafer 1. Next, the side of the first redistribution layer 20 and the conductive bumps 30 may be placed on the chip carrier 40. In this way, the chip carrier 40 is matched with a corresponding plastic packaging mold for plastic packaging, so as to form the plastic packaging body 50 for protecting the chip 10. The chip carrier 40 may be removed and solder balls 60 soldered to the conductive bumps 30. Finally, dicing may be performed to obtain a plurality of fan-in semiconductor packages.
In one possible implementation, the foregoing step S206 may include the following specific examples.
In step S206-3, the chip carrier 40 is removed, and the conductive bump 30 and the second redistribution layer are formed on the side of the chip array where the first redistribution layer 20 is located, and the first redistribution layer 20 and the second redistribution layer are connected by the conductive bump 30.
In the substep S206-4, ball placement is performed on the second redistribution layer.
In sub-step S206-5, the chip array is diced for each chip 10 to obtain a plurality of fan-out semiconductor packages.
In addition to the above-mentioned embodiments, the embodiment of the present application further provides a fan-out type semiconductor package structure, in which after the chip carrier 40 is removed, the conductive bump 30 is fabricated on the first redistribution layer 20, then the second redistribution layer is fabricated, the conductive bump 30 may be connected to the first redistribution layer 20 and the second redistribution layer, then the ball mounting process for the second redistribution layer is performed uniformly, and finally the dicing is performed, so that a plurality of fan-out type semiconductor packages structures can be obtained.
In order to clearly describe the solution provided in the embodiments of the present application for manufacturing a plurality of fan-in semiconductor packages, the following exemplary description may be made with reference to fig. 3. First, a wafer 1 including a plurality of chips 10 may be provided. Then, the first rewiring layer 20 is fabricated for each chip 10, and the side on which the first rewiring layer 20 is located is placed on the chip carrier 40. Then, the chip 10 may be molded using a corresponding mold to form a molded body 50 protecting the chip 10. Then, the chip carrier 40 may be removed, and the conductive bump 30 may be fabricated for the first redistribution layer 20, and then the second redistribution layer may be fabricated such that the first and second redistribution layers 20 and 30 are connected by the conductive bump 30. Finally, solder balls 60 may be soldered to the second redistribution layer and diced to obtain a plurality of fan-out semiconductor packages.
In one possible embodiment, the foregoing step S206 may further include the following embodiments.
Substep S206-6, the chip carrier 40 is removed using a laser.
The removal of the chip carrier 40 may be performed by laser removal to enable the chip carrier 40 to be peeled from the chip 10 quickly and efficiently.
It is worth to be noted that, through the above process flow, no additional back adhesive manufacturing process is involved in the manufacturing process, so that the cost is saved, meanwhile, as the surface mounting process in the related technology is not used, the limitation of the width of the cutting band of the incoming wafer 1 can be avoided, and the manufacturing of products with any cutting channel specification and any encapsulation width can be realized. Meanwhile, the problem of process instability caused by uneven height of the chip 10 generated by the Face down process in the chip mounting process is avoided.
In addition, in order to further improve the production efficiency of the chip 10, a plurality of wafers 1 may be provided, the plurality of wafers 1 may be temporarily bonded to a panel (for example, a metal substrate), and the method for manufacturing a semiconductor package structure may be performed for each wafer 1, so as to process the plurality of wafers 1 simultaneously, thereby improving the efficiency.
The embodiment of the application provides a semiconductor packaging structure, which is manufactured by the manufacturing method of the semiconductor packaging structure.
In summary, the embodiment of the application provides a semiconductor package structure manufacturing method and a semiconductor package structure, including a wafer of a plurality of chips to be packaged, a first redistribution layer for each chip is manufactured on one side of the wafer, the wafer is cut to obtain a chip array composed of a plurality of chips distributed at preset intervals, the chip array is arranged on a chip carrier, the chip array is subjected to plastic packaging to obtain a plastic package body for protecting each chip, the chip carrier is removed and the chip array is cut, and the manufactured plurality of semiconductor plastic package structures are obtained.
The foregoing description, for purpose of explanation, has been presented with reference to particular embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. The foregoing description, for purpose of explanation, has been presented with reference to particular embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.

Claims (9)

1. A method of fabricating a semiconductor package, comprising:
providing a wafer, wherein the wafer comprises a plurality of chips to be packaged;
fabricating a first rewiring layer for each chip on one side of the wafer;
cutting the wafer to obtain a chip array consisting of a plurality of chips distributed at preset intervals;
manufacturing a chip carrier on one side of the chip array where the first rewiring layer is located;
performing plastic packaging on the chip array based on the chip carrier to form a plastic packaging body for protecting each chip;
removing the chip carrier, and cutting the chip array by taking each chip as a unit to obtain a plurality of manufactured semiconductor packaging structures;
the wafer is cut to obtain a chip array composed of a plurality of chips distributed according to preset intervals, and the method comprises the following steps:
cutting the wafer to obtain a plurality of separated chips;
and (3) performing film expansion on the chips so as to enable the distance between the chips to be smaller, and obtaining a chip array consisting of the chips distributed at preset intervals.
2. The method of claim 1, wherein dicing the wafer to obtain a plurality of separated chips comprises:
and adhering the wafer to a dicing film, and dicing based on the dicing film to obtain a plurality of separated chips.
3. The method of claim 2, wherein the step of performing film expansion on the plurality of chips to obtain a chip array comprising a plurality of chips distributed at predetermined intervals comprises:
placing the plurality of separated chips on a carrier film in a film expander, wherein the cutting film is in contact with the carrier film;
and performing film expansion on the chips according to preset intervals by using the film expander to obtain the chip array.
4. The method of claim 1, wherein the predetermined interval is 1um.
5. The method according to claim 1, wherein the method further comprises:
and manufacturing conductive bumps on the first rewiring layers corresponding to the chips.
6. The method of claim 5, wherein said removing said chip carrier and dicing said array of chips per chip to obtain a plurality of finished semiconductor packages comprises:
removing the chip carrier, and implanting balls into the conductive bumps;
and cutting the chip array by taking each chip as a unit to obtain a plurality of manufactured fan-in semiconductor packaging structures.
7. The method of claim 1, wherein said removing said chip carrier and dicing said array of chips per chip to obtain a plurality of finished semiconductor packages comprises:
removing the chip carrier, and manufacturing a conductive bump and a second redistribution layer on one side of the chip array where the first redistribution layer is located, wherein the first redistribution layer and the second redistribution layer are connected through the conductive bump;
ball placement is carried out on the second redistribution layer;
and cutting the chip array by taking each chip as a unit to obtain a plurality of manufactured fan-out type semiconductor packaging structures.
8. The method of claim 1, wherein the removing the chip carrier comprises:
the chip carrier is removed using a laser.
9. A semiconductor package structure, characterized by being manufactured by the method for manufacturing a semiconductor package structure according to any one of claims 1 to 8.
CN202110510989.0A 2021-05-11 2021-05-11 Manufacturing method of semiconductor packaging structure and semiconductor packaging structure Active CN113257692B (en)

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