CN108091629A - A kind of photoelectric chip integrated morphology - Google Patents
A kind of photoelectric chip integrated morphology Download PDFInfo
- Publication number
- CN108091629A CN108091629A CN201711305080.1A CN201711305080A CN108091629A CN 108091629 A CN108091629 A CN 108091629A CN 201711305080 A CN201711305080 A CN 201711305080A CN 108091629 A CN108091629 A CN 108091629A
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- chip
- photoelectric chip
- pad
- photoelectric
- packaging body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
The invention discloses a kind of photoelectric chip integrated morphology, including：Photoelectric chip and electrical chip；One of the photoelectric chip and the electrical chip formal dress are set, and another one upside-down mounting is set；At least one second pad that at least one first pad of the photoelectric chip corresponds to the electrical chip is set.The pad of different modes photoelectric chip and electrical chip that the present invention passes through formal dress and upside-down mounting is staggered relatively and position corresponds to, and connects or connects so as to connect Direct Bonding between corresponding pad or pad by soldered ball.Connected compared to using bonding wire, the cross-sectional area of soldered ball or directly in conjunction with contact area it is larger, therefore inductance is smaller, according to formulaInductance is smaller, and frequency is higher, and therefore, higher by soldered ball connection or the attainable frequency of pad Direct Bonding institute, so as to widen the bandwidth of photoelectric chip and electrical chip signal transmission, relative bandwidth is up to 8 to 50 times of conventional package.
Description
Technical field
The present invention relates to integrated chip technical fields, and in particular to a kind of photoelectric chip integrated morphology.
Background technology
Optic communication (Optical Communication) is the communication mode using light wave as carrier wave.With the development of technology,
Amount of communication data is increasing, therefore higher and higher to the transmission rate request of optical communications module.At present, 56Gbps and
112Gbps is the standard of next-generation light network.Photoelectric chip integrated morphology is the core component of optical communications module.Photoelectricity core
Piece integrated morphology is by photoelectric chip (such as the active electro-optics such as laser, modulator, detector chip or the photoelectricity collection of multiple structures
Into chip) it is integrated with the electrical chip (such as driving chip of photoelectric chip) of its peripheral circuit, realize optical signal and electricity
The function that signal is converted.Amount of communication data itself is increasing, in addition photoelectric chip and electrical chip need optical signal and
Electric signal is frequently converted so that the electrical characteristics interconnected between both become the bottle of photoelectric chip integrated morphology bandwidth Design
Neck.
Photoelectric chip and electrical chip are often organized on medium substrate by existing way, and its pad is used this field skill
Art personnel mode of common bonding wire in integrated chip is connected on the wiring layer of medium substrate, so as in medium substrate
Upper unified wiring.
However, it is found by the inventors that used bonding wire causes light when existing way realizes photoelectric chip integrated morphology
The bandwidth of electrical chip interconnection, which is restricted, to be difficult to widen.
The content of the invention
In view of this, an embodiment of the present invention provides a kind of photoelectric chip integrated morphology, to solve photoelectric chip interconnection
Bandwidth is restricted the problem of being difficult to widen.
First aspect present invention provides a kind of photoelectric chip integrated morphology, including：Photoelectric chip and electrical chip；The light
One of electrical chip and the electrical chip formal dress are set, and another one upside-down mounting is set；At least one the first of the photoelectric chip
At least one second pad that pad corresponds to the electrical chip is set.
Optionally, the photoelectric chip integrated morphology further includes：Packaging body；The photoelectric chip formal dress insertion is arranged on institute
It states in packaging body, the first surface of the photoelectric chip is flushed with the first surface of the packaging body；The electrical chip upside-down mounting is set
Put the first surface in the packaging body.
Optionally, the light functional component of the photoelectric chip is located at the first surface of the photoelectric chip.
Optionally, at least one first via is provided in the packaging body, it is at least one with the electrical chip respectively
3rd pad connects, and the first surface of the first via from the packaging body extends to second surface.
Optionally, it is also embedded in the packaging body to be provided with hard block, the surface that the hard block reveals in vitro with it is described
The surface of packaging body flushes；At least one first via is provided in the hard block body, respectively with the electrical chip at least
One the 3rd pad connection；The first surface of first via from the hard block extends to second surface.
Optionally, first via is directly connected to the 3rd pad.
Optionally, the photoelectric chip integrated morphology further includes：First wiring layer is arranged at the first table of the packaging body
Face；One end of the conducting wire of first wiring layer is connected or described at least one 3rd pad of the electrical chip respectively
One end of the conducting wire of first wiring layer is connected respectively at least one 4th pad of the photoelectric chip；The other end and described the
One via connects.
Optionally, the photoelectric chip integrated morphology further includes：Second wiring layer is arranged at the second table of the packaging body
Face, conducting wire one end of second wiring layer are connected with first via, and the other end sets soldered ball.
Optionally, at least one 5th pad of the second surface exposing photoelectric chip of the packaging body, and
Position on the second surface of the packaging body corresponding to the 5th pad is provided with soldered ball.
Optionally, the photoelectric chip is internally provided with the second via, one end of second via and the photoelectricity core
The pad connection of piece, the other end extend to the second surface connection soldered ball of the photoelectric chip or the conducting wire of wiring layer.
The photoelectric chip integrated morphology that the embodiment of the present invention is provided passes through formal dress and the different modes photoelectricity of upside-down mounting
The pad of chip and electrical chip is staggered relatively and position corresponds to, so as to connect corresponding pad or pad by soldered ball
Between Direct Bonding connection or connect.Compared to using bonding wire connect, the cross-sectional area of soldered ball or directly in conjunction with
Contact area it is larger, therefore inductance is smaller, according to formulaInductance is smaller, and frequency is higher, therefore, passes through weldering
Ball connects or the attainable frequency of pad Direct Bonding institute is higher, so as to widen photoelectric chip and electrical chip signal transmission
Bandwidth, relative bandwidth is up to 8 to 50 times of conventional package.Above-mentioned photoelectric chip integrated morphology substantially reduces track lengths,
Signal delay and loss are reduced,
Description of the drawings
The features and advantages of the present invention can be more clearly understood by reference to attached drawing, attached drawing is schematically without that should manage
It solves to carry out any restrictions to the present invention, in the accompanying drawings：
Fig. 1 shows a kind of schematic diagram of photoelectric chip integrated morphology according to embodiments of the present invention；
Fig. 2 shows the schematic diagram of another photoelectric chip integrated morphology according to embodiments of the present invention；
Fig. 3 shows the schematic diagram of another photoelectric chip integrated morphology according to embodiments of the present invention；
Fig. 4 shows the schematic diagram of another photoelectric chip integrated morphology according to embodiments of the present invention；
Fig. 5 shows the schematic diagram of another photoelectric chip integrated morphology according to embodiments of the present invention.
Specific embodiment
In order to make the purpose of the present invention, advantage, preparation method clearer, below in conjunction with implementation of the attached drawing to the present invention
Example is described in detail, and the example of the embodiment is shown in the drawings, and part-structure has directly given excellent wherein in attached drawing
The structural material of choosing, it is clear that described embodiment is part of the embodiment of the present invention, instead of all the embodiments.It needs
Illustrate, the embodiment being described with reference to the drawings is exemplary, and the structural material shown in embodiment is also exemplary, only
It for explaining the present invention, and is not construed as limiting the claims, the attached drawing of each embodiment of the present invention is merely to signal
Purpose, therefore be not necessarily to scale.Based on the embodiments of the present invention, those skilled in the art are not making wound
All other embodiments obtained under the premise of the property made work, belong to the scope of protection of the invention.
Embodiment one
An embodiment of the present invention provides a kind of photoelectric chip integrated morphology, which includes photoelectric chip 10 and battery core
Piece 20.One of photoelectric chip 10 and electrical chip 20 formal dress are set, and another one upside-down mounting is set.Photoelectric chip 10 it is at least one
At least one second pad that first pad corresponds to electrical chip 20 is set.First pad can be connected with the second pad by soldered ball
It connects or the connection of pad Direct Bonding, the application does not limit connection mode herein.
Above-mentioned photoelectric chip integrated morphology passes through formal dress and the different modes photoelectric chip of upside-down mounting and the weldering of electrical chip
Disk is staggered relatively and position corresponds to, and is connected so as to connect Direct Bonding between corresponding pad or pad by soldered ball
Or it connects.Compared to using bonding wire connect, the cross-sectional area of soldered ball or directly in conjunction with contact area it is larger, because
This inductance is smaller, according to formulaInductance is smaller, and frequency is higher, therefore, passes through soldered ball connection or pad direct key
The attainable frequency of conjunction institute is higher, and so as to widen the bandwidth of photoelectric chip and electrical chip signal transmission, relative bandwidth can
Up to 8 to 50 times of conventional package.Above-mentioned photoelectric chip integrated morphology substantially reduces track lengths, reduces signal delay and damage
Consumption.
Photoelectric chip 10 in the application can be active electro-optics chip or multiple knots such as laser, modulator, detector
The photoelectricity integrated chip of structure, material can be the compound semiconductor materials such as silicon optical chip or indium, gallium, arsenic, phosphorus or
Person's carborundum, silicon nitride material.
As a kind of optional embodiment of the present embodiment, as shown in Figure 1, the photoelectric chip integrated morphology includes packaging body
30, such as plastic-sealed body.The block that " packaging body " described herein is formed after being cured by soft packing colloid.Photoelectricity core
The insertion of 10 formal dress of piece is arranged in packaging body 30, and the first surface of photoelectric chip 10 is flushed with the first surface of packaging body 30.Example
Soft packaging plastic such as can be first coated on substrate, then the insertion of photoelectric chip 10 is placed on packing colloid, packaging plastic cladding
First surface is polished after adhesive curing to be packaged or flattens first surface before adhesive curing is encapsulated by photoelectric chip 10.
Packaging body 30 can with 10 direct seamless binding of photoelectric chip, so as to accurately fix photoelectric chip 10 position and water
Pingdu can be based on photoelectric chip 10 convenient for other component and precisely mount.
A kind of mode of texturing that plastic-sealed body 30 fixes photoelectric chip 10 is taken as, can be opened up in the block of hard recessed
Slot, then in bottom portion of groove coating colloid, photoelectric chip 10 is pasted onto bottom portion of groove.However this embodiment is opened for groove
If depth and bottom water Pingdu it is more demanding, general technology is difficult to reach accurately to be required very much；In addition photoelectric chip 10
There is bottom to fix, be not sufficiently stable in subsequent process steps.
20 upside-down mounting of electrical chip is arranged on the first surface of packaging body 30." upside-down mounting " described herein refers to pad downward
Setting, " formal dress " be the setting of pad upward.
There is the light functional component 11 such as optical coupling structure on photoelectric chip 10, for example, can be grating, spot-size converter or
Person's waveguiding structure.Optionally, the light functional component 11 of photoelectric chip 10 is located at the first surface of photoelectric chip 10, consequently facilitating light
The connection of functional component 11 and other component (such as optical fiber 40).
Electrical chip 20 also has the 3rd pad, is located at the same surface of electrical chip 20 with the second pad, and the 3rd pad can be with
It is drawn by the conducting wire of 30 first surface wiring layer of packaging body, and soldered ball is set at conducting wire endpoint.Alternatively, as the present embodiment
A kind of optional embodiment, at least one first via 50 is provided in packaging body 30, respectively at least the one of electrical chip 20
A 3rd pad connection, the first surface of the first via 50 from packaging body 30 extend to second surface.First via 50 can be with
3rd pad is directly connected to by soldered ball.
" via " in the application is also referred to as plated through-hole, to connect the printed conductor of first surface and second surface, in table
Face needs the intersection of the conducting wire connected or a upper common aperture is bored in soldered ball position, then with change on the hole wall cylindrical surface of via
Learn the method plating last layer metal of deposition.
As a kind of optional embodiment arranged side by side of above-mentioned optional embodiment, as shown in Fig. 2, also embedded in packaging body 30
Hard block 60 is provided with, the exposed surface of hard block 60 is flushed with the surface of packaging body 30.It is provided in hard block 60
At least one first via 50 is connected respectively at least one 3rd pad of electrical chip 20.First via 50 is from hard block
60 first surface extends to second surface.First via 50 can in succession connect with the 3rd pad, can set weldering therebetween
Ball auxiliary connection.
Optionally, which further includes the first wiring layer 70, as shown in figure 4, being arranged at the of packaging body 30
One surface.One end of the conducting wire of first wiring layer 70 is connected respectively at least one 3rd pad of electrical chip 20 (not to be shown in figure
Go out the situation)；Alternatively, one end of the conducting wire of the first wiring layer 70 respectively at least one 4th pad of photoelectric chip 10 (such as
In Fig. 4 shown in 12) connection.The other end of the conducting wire of first wiring layer 70 is connected with the first via 50.Optionally, can also pass through
Layout block 120 as shown in Figure 5 replaces the first wiring layer 70 namely wire structures is arranged in layout block 120 in advance, is making
Directly layout block 120 is used to assemble when making photoelectric chip integrated morphology.By the first wiring layer or the layout block, by light
The pad of electrical chip or electrical chip is fanned out to design, can be connected up in order to photoelectricity integrated morphology.May be used also on the surface of first wiring layer 70
To set insulating layer 80.
Optionally, which further includes the second wiring layer 90, is arranged at the second surface of packaging body 30,
Conducting wire one end of second wiring layer 90 is connected with the first via 50, and the other end sets soldered ball.By the second wiring layer, can cause
Soldered ball is more uniformly distributed in the second surface of packaging body, with balanced all electrical properties.The surface of second wiring layer 90 can be with
Insulating layer 100 is set.
As a kind of optional embodiment of the present embodiment, as shown in figure 3, the second surface of packaging body 30 is by being thinned work
Skill exposes at least one 5th pad of photoelectric chip 10, and corresponding to the 5th pad on the second surface of packaging body 30
Position is provided with soldered ball, so as to which the signal of 10 second surface of photoelectric chip (such as low frequency signal) is directly led out, is convenient for
Photoelectric chip integrated morphology connects up.
Optionally, photoelectric chip 10 is internally provided with the second via 110, one end and the photoelectric chip 10 of the second via 110
Pad connection, the other end extend to photoelectric chip 10 second surface connection soldered ball or wiring layer conducting wire.By in photoelectricity
10 inside of chip sets the second via, can directly lead out the signal of 10 first surface of photoelectric chip, convenient for photoelectric chip collection
Into structural wiring.
Although being described in detail on example embodiment and its advantage, those skilled in the art can not depart from
Various change is carried out to these embodiments in the case of the spiritual and defined in the appended claims protection domain of the present invention, is replaced
And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability
The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention
Change.
In addition, the application range of the present invention is not limited to technique, mechanism, the system of the specific embodiment described in specification
It makes, material composition, means, method and step.It, will be easy as those of ordinary skill in the art from the disclosure
Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or
Step, the knot that the function or acquisition that the corresponding embodiment that wherein they are performed with the present invention describes is substantially the same are substantially the same
Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system
It makes, material composition, means, method or step are included in its protection domain.
Claims (10)
1. a kind of photoelectric chip integrated morphology, which is characterized in that including：Photoelectric chip and electrical chip；
One of the photoelectric chip and the electrical chip formal dress are set, and another one upside-down mounting is set；The photoelectric chip is extremely
At least one second pad that few first pad corresponds to the electrical chip is set.
2. photoelectric chip integrated morphology according to claim 1, which is characterized in that further include：Packaging body；
The photoelectric chip formal dress insertion is arranged in the packaging body, the first surface of the photoelectric chip and the packaging body
First surface flush；The electrical chip upside-down mounting is arranged on the first surface of the packaging body.
3. photoelectric chip integrated morphology according to claim 2, which is characterized in that the light functional component of the photoelectric chip
Positioned at the first surface of the photoelectric chip.
4. photoelectric chip integrated morphology according to claim 3, which is characterized in that at least one is provided in the packaging body
A first via is connected respectively at least one 3rd pad of the electrical chip, and first via is from the packaging body
First surface extends to second surface.
5. photoelectric chip integrated morphology according to claim 3, which is characterized in that also insertion is provided in the packaging body
Hard block, the surface that the hard block reveals in vitro are flushed with the surface of the packaging body；
At least one first via is provided in the hard block body, is connected respectively at least one 3rd pad of the electrical chip
It connects；The first surface of first via from the hard block extends to second surface.
6. photoelectric chip integrated morphology according to claim 4 or 5, which is characterized in that first via and described the
Three pads are directly connected to.
7. photoelectric chip integrated morphology according to claim 4 or 5, which is characterized in that further include：
First wiring layer is arranged at the first surface of the packaging body；One end of the conducting wire of first wiring layer respectively with institute
State electrical chip at least one 3rd pad connection or first wiring layer conducting wire one end respectively with the photoelectricity core
At least one 4th pad connection of piece；The other end is connected with first via.
8. according to claim 4 to 7 any one of them photoelectric chip integrated morphology, which is characterized in that further include：
Second wiring layer is arranged at the second surface of the packaging body, conducting wire one end of second wiring layer and described first
Via connects, and the other end sets soldered ball.
9. photoelectric chip integrated morphology according to claim 2, which is characterized in that the second surface of the packaging body exposes
At least one 5th pad of the photoelectric chip, and correspond to the 5th pad on the second surface of the packaging body
Position be provided with soldered ball.
10. photoelectric chip integrated morphology according to claim 2, which is characterized in that the photoelectric chip is internally provided with
Second via, one end of second via are connected with the pad of the photoelectric chip, and the other end extends to the photoelectric chip
Second surface connection soldered ball or wiring layer conducting wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711305080.1A CN108091629B (en) | 2017-12-08 | 2017-12-08 | Photoelectric chip integrated structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711305080.1A CN108091629B (en) | 2017-12-08 | 2017-12-08 | Photoelectric chip integrated structure |
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| CN108091629A true CN108091629A (en) | 2018-05-29 |
| CN108091629B CN108091629B (en) | 2020-01-10 |
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| CN109786368A (en) * | 2019-01-24 | 2019-05-21 | 中国科学院微电子研究所 | A kind of photoelectric chip collaboration encapsulating structure and method |
| CN113589449A (en) * | 2021-06-21 | 2021-11-02 | 北京协同创新研究院 | Hybrid integrated system applied to photoelectric interconnection |
| CN114325965A (en) * | 2021-12-28 | 2022-04-12 | 华进半导体封装先导技术研发中心有限公司 | Optical chip and electric chip packaging structure and preparation method thereof |
| CN114355520A (en) * | 2021-12-30 | 2022-04-15 | 华进半导体封装先导技术研发中心有限公司 | Optical chip and electric chip packaging structure and preparation method thereof |
| CN115149394A (en) * | 2022-09-05 | 2022-10-04 | 山东中清智能科技股份有限公司 | Photoelectric device integrated packaging structure and manufacturing method thereof |
| CN117096037A (en) * | 2023-10-20 | 2023-11-21 | 盛合晶微半导体(江阴)有限公司 | Semiconductor photoelectric packaging structure based on grating and preparation method thereof |
| WO2024066360A1 (en) * | 2022-09-30 | 2024-04-04 | 青岛海信宽带多媒体技术有限公司 | Optical module |
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| CN108091629B (en) | 2020-01-10 |
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