CN111554627A - Chip packaging method - Google Patents

Chip packaging method Download PDF

Info

Publication number
CN111554627A
CN111554627A CN202010367772.4A CN202010367772A CN111554627A CN 111554627 A CN111554627 A CN 111554627A CN 202010367772 A CN202010367772 A CN 202010367772A CN 111554627 A CN111554627 A CN 111554627A
Authority
CN
China
Prior art keywords
package
packaging
chip
substrate
packaging body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010367772.4A
Other languages
Chinese (zh)
Other versions
CN111554627B (en
Inventor
夏鑫
李红雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Fujitsu Microelectronics Co Ltd
Original Assignee
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to CN202010367772.4A priority Critical patent/CN111554627B/en
Publication of CN111554627A publication Critical patent/CN111554627A/en
Application granted granted Critical
Publication of CN111554627B publication Critical patent/CN111554627B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The application discloses a chip packaging method, which comprises the following steps: providing a first packaging body and a second packaging body, wherein the first packaging body and the second packaging body respectively comprise a plurality of first conductive columns and a first plastic packaging layer, and the first plastic packaging layer covers the side faces of the first conductive columns; arranging a first packaging body and a second packaging body on a packaging substrate at intervals, arranging a connecting chip in an interval area between the first packaging body and the second packaging body, and respectively arranging a first main chip and a second main chip on one sides of the first packaging body and the second packaging body, which are far away from the packaging substrate; the signal transmission areas of the first main chip and the second main chip are arranged adjacently, the bonding pads of the signal transmission areas of the first main chip and the second main chip are electrically connected with the connecting chip, and the bonding pads of the non-signal transmission areas of the first main chip and the second main chip are electrically connected with the first conductive columns. The chip packaging method provided by the application can reduce the packaging cost and improve the performance of the packaged device.

Description

Chip packaging method
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a chip packaging method.
Background
The existing polymer-based 2D packaging technology is the most basic and widely applied packaging form, is mature in technology and low in cost, but has no connection in the third direction and is large in line width. The recently developed packaging technology based on the silicon interposer is small in line width, and the formed packaged device is excellent in electrical performance and thermal conductivity, but high in cost, and the silicon material is high in brittleness, so that the stability of the packaged device is low. Therefore, there is a need to develop a new packaging technique that combines the advantages of the existing packaging techniques, can reduce the cost, and can form a packaged device with excellent performance.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a chip packaging method, which can reduce the packaging cost and improve the performance of a packaged device.
In order to solve the technical problem, the application adopts a technical scheme that:
a chip packaging method is provided, which comprises the following steps: providing a first packaging body and a second packaging body, wherein the first packaging body and the second packaging body respectively comprise a plurality of first conductive columns and a first plastic packaging layer, and the first plastic packaging layer covers the side faces of the first conductive columns; arranging the first packaging body and the second packaging body on a packaging substrate at intervals, arranging a connecting chip in an interval area between the first packaging body and the second packaging body, and respectively arranging a first main chip and a second main chip on one sides of the first packaging body and the second packaging body, which are far away from the packaging substrate; the signal transmission areas of the first main chip and the second main chip are arranged adjacently, the bonding pads of the signal transmission areas of the first main chip and the second main chip are electrically connected with the connecting chip, and the bonding pads of the non-signal transmission areas of the first main chip and the second main chip are electrically connected with the first conductive columns.
Wherein the providing a first package or the providing a second package comprises:
providing a removable carrier plate, wherein the carrier plate is defined with at least one area; forming a plurality of said first conductive pillars in each of said regions; forming a first plastic package layer on one side of the carrier plate, where the first conductive pillars are arranged, and exposing the surface of one side, away from the carrier plate, of the first conductive pillar from the first plastic package layer; and removing the carrier plate.
Wherein, said first encapsulation body and said second encapsulation body are arranged on the encapsulation substrate at intervals, before, including:
and forming a first solder on one side surface of the first conductive pillar facing the package substrate, or forming a first solder on one side surface of the package substrate.
Wherein, will first encapsulation body with the second encapsulation body interval sets up on packaging substrate, and the interval region between first encapsulation body with the second encapsulation body is provided with the connection chip, includes: arranging the first packaging body and the second packaging body on the packaging substrate with a flat surface at intervals; and the non-functional surface of the connecting chip faces the packaging substrate and is arranged in a spacing area between the first packaging body and the second packaging body.
Or, the first package body and the second package body are arranged on the package substrate at intervals, and a connection chip is arranged in an interval area between the first package body and the second package body, including: arranging the connecting chip on the packaging substrate with a flat surface, wherein the non-functional surface of the connecting chip faces the packaging substrate; and arranging the first packaging body and the second packaging body at two opposite sides of the connecting chip at intervals.
Or, the first package body and the second package body are arranged on the package substrate at intervals, and a connection chip is arranged in an interval area between the first package body and the second package body, including: arranging the first packaging body and the second packaging body on the packaging substrate with grooves on the surface at intervals, wherein the grooves are correspondingly arranged in the interval areas of the first packaging body and the second packaging body; and enabling the non-functional surface of the connecting chip to face the packaging substrate, and arranging the non-functional surface of the connecting chip to face the packaging substrate in a spacing area between the first packaging body and the second packaging body, wherein at least part of the connecting chip is positioned in the groove.
Or, the first package body and the second package body are arranged on the package substrate at intervals, and a connection chip is arranged in an interval area between the first package body and the second package body, including: arranging the connecting chip on the packaging substrate with a groove on the surface, wherein at least part of the connecting chip is positioned in the groove, and the non-functional surface of the connecting chip faces the packaging substrate; and arranging the first packaging body and the second packaging body at two opposite sides of the connecting chip at intervals.
Wherein, will first packaging body with the second packaging body interval sets up on packaging substrate, and the interval region between first packaging body and the second packaging body is provided with the connection chip, later, includes: and arranging the first main chip on one side surface of the first packaging body far away from the packaging substrate, and arranging the second main chip on one side surface of the second packaging body far away from the packaging substrate.
Wherein, after the disposing the first main chip on a side surface of the first package body away from the package substrate and the disposing the second main chip on a side surface of the second package body away from the package substrate, the method includes: and forming underfill between the first main chip and the second main chip and the first packaging body and the second packaging body.
The first packaging body and the second packaging body comprise a plurality of packaging units, each packaging unit comprises a plurality of first conductive columns, and the first plastic packaging layers of the adjacent packaging units are connected with each other; before the first package body and the second package body are arranged on the package substrate at intervals, the method includes: cutting off the area between the adjacent packaging units to obtain the first packaging body and the second packaging body containing the single packaging unit.
The beneficial effect of this application is: different from the prior art, the chip packaging method provided by the application adopts different connection modes for the signal transmission area and the non-signal transmission area of the main chip: for the signal transmission area, a connecting chip is adopted to connect the two main chips, so that the signal transmission rate between the main chips is improved, and the performance of a packaged device is improved; for the non-signal transmission area, the common conductive column is connected with the packaging substrate, so that the packaging cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 1;
FIG. 3 is a flowchart illustrating an embodiment corresponding to step S101 in FIG. 1;
FIG. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 3;
FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 3;
FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 3;
FIG. 5 is a schematic structural diagram of another embodiment corresponding to step S101 in FIG. 1;
FIG. 6 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;
FIG. 7 is a flowchart illustrating an embodiment corresponding to step S102 in FIG. 1;
FIG. 8a is a schematic structural diagram of an embodiment corresponding to step S301 in FIG. 7;
FIG. 8b is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 7;
FIG. 9 is a schematic flow chart illustrating another embodiment corresponding to step S102 in FIG. 1;
FIG. 10 is a schematic structural diagram of an embodiment corresponding to step S401 in FIG. 9;
FIG. 11 is a schematic flow chart illustrating another embodiment corresponding to step S102 in FIG. 1;
FIG. 12a is a schematic structural diagram of an embodiment corresponding to step S501 in FIG. 11;
FIG. 12b is a schematic structural diagram of an embodiment corresponding to step S502 in FIG. 11;
FIG. 13 is a schematic flowchart illustrating another embodiment corresponding to step S102 in FIG. 1;
FIG. 14 is a schematic structural diagram of an embodiment corresponding to step S601 in FIG. 13;
FIG. 15 is a schematic structural diagram of another embodiment corresponding to step S102 in FIG. 1;
FIG. 16 is a schematic structural diagram of an embodiment corresponding to the step included before the step S102 in FIG. 1;
fig. 17 is a schematic structural diagram of an embodiment corresponding to the step included after step S102 in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a chip packaging method according to the present application, the chip packaging method including the following steps:
s101, providing a first packaging body and a second packaging body, wherein the first packaging body and the second packaging body respectively comprise a plurality of first conductive columns and a first plastic packaging layer, and the first plastic packaging layer covers the side faces of the first conductive columns.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 1, in which a structure of a first package is schematically illustrated, and a structure of a second package is similar to the first package, but layouts, spacing manners, and heights of the first conductive pillars in the first package and the second package may be the same or different, and heights and sizes of the first package and the second package may be the same or different. As shown in fig. 2, the first package body 20 includes a plurality of first conductive pillars 21 and a first molding compound layer 22, and the first molding compound layer 22 covers side surfaces of the first conductive pillars 21.
In an embodiment, referring to fig. 3, fig. 3 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 1, where the step of providing the first package or the step of providing the second package specifically includes:
s201, providing a removable carrier plate, wherein the carrier plate is defined with at least one area.
Specifically, referring to fig. 4a, fig. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 3. The carrier 23 is schematically illustrated as defining an area, wherein the carrier 23 is made of a rigid material such as metal, plastic, etc.
S202, a plurality of first conductive pillars are formed in each region.
Specifically, please refer to fig. 4b, wherein fig. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 3. In the present embodiment, a plurality of first conductive pillars 21 are formed in a region of the carrier 23 where one region is defined, and the first conductive pillars 21 are made of copper-containing alloy, and may be formed by electroplating or the like. For example, a patterned mask layer may be formed on the surface of the carrier 23, a via hole is formed on the mask layer, the first conductive pillar 21 is formed in the via hole, and finally the mask layer is removed.
S203, a first plastic package layer is formed on one side of the carrier board where the first conductive pillars are disposed, and a surface of one side of the first conductive pillars, which is far away from the carrier board, is exposed from the first plastic package layer.
Specifically, please refer to fig. 4c, wherein fig. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 3. After the first conductive pillars 21 are formed, a first molding layer 22 is formed on the side of the carrier plate 23 where the first conductive pillars 21 are disposed, and a surface of the first conductive pillars 21 away from the carrier plate 23 is exposed from the first molding layer 22. The first molding compound layer 22 may be made of epoxy resin, and the first conductive pillar 21 can be protected.
In addition, in the step S203, a first molding compound layer 22 may be formed on one side of the carrier plate 23, and the first molding compound layer 22 covers a surface of the first conductive pillar 21 away from the carrier plate 23; then, a surface of the first molding compound layer 22 away from the carrier plate 23 is ground, so that a surface of the first conductive pillar 21 away from the carrier plate 23 is exposed from the first molding compound layer 22.
S204, removing the carrier plate.
Referring to fig. 2, after the carrier 23 is removed, the first package body 20 is obtained, which includes a plurality of first conductive pillars 21 and a first molding compound layer 22, wherein the first molding compound layer 22 covers side surfaces of the first conductive pillars 21.
Further, the present embodiment includes, after forming the first package and the second package, before step S102 (disposing the first package and the second package on the package substrate with a space therebetween), the steps of: the first solder 24 is formed on the surface of the first conductive post 21 facing the package substrate, or the first solder 24 is formed on the surface of the package substrate. The first solder 24 is made of an electrically and thermally conductive material, so that the main chip and the package substrate can be electrically connected.
In another embodiment, please refer to fig. 5, wherein fig. 5 is a schematic structural diagram of another embodiment corresponding to step S101 in fig. 1. The first package and the second package comprise a plurality of package units, and fig. 5 schematically illustrates a case where the first package comprises two package units 50, each package unit 50 comprises a plurality of first conductive pillars 51, and the first molding compounds 52 of adjacent package units 50 are connected to each other; before the first packaging body and the second packaging body are arranged on the packaging substrate at intervals, the packaging substrate comprises: the area between adjacent package units 50 is cut away, for example along the dashed line 100 in the figure, to obtain a first package or a second package containing a single package unit 50. In this embodiment, the time point of forming the first solder is not limited, and may be before dicing or after dicing.
S102, arranging a first packaging body and a second packaging body on a packaging substrate at intervals, arranging a connecting chip in an interval area between the first packaging body and the second packaging body, and arranging a first main chip and a second main chip on one sides of the first packaging body and the second packaging body, which are far away from the packaging substrate, respectively; the signal transmission areas of the first main chip and the second main chip are arranged adjacently, the bonding pads of the signal transmission areas of the first main chip and the second main chip are electrically connected with the connecting chip, and the bonding pads of the non-signal transmission areas of the first main chip and the second main chip are electrically connected with the first conductive columns.
Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1. Arranging the first package body 20 and the second package body 30 on the package substrate 500 at intervals, arranging the connection chip 40 in an interval area between the first package body 20 and the second package body 30, and arranging a first main chip 200 and a second main chip 300 on the sides of the first package body 20 and the second package body 30 far away from the package substrate 500 respectively; the signal transmission regions 600 of the first main chip 200 and the second main chip 300 are disposed adjacent to each other, the pads of the signal transmission regions 600 of the first main chip 200 and the second main chip 300 are electrically connected to the connection chip 40, and the pads of the non-signal transmission regions 700 of the first main chip 200 and the second main chip 300 are electrically connected to the first conductive pillars 21. The first conductive pillar 21 is electrically connected to the package substrate 500 through the first solder 24.
In addition, the first main chip 200 may be a CPU or the like, the second main chip 300 may be a GPU or the like, and one first main chip 200 may be electrically connected to at least one second main chip 300 through the connection chip 40. For example, the four corners of the first main chip 200 are provided with signal transmission area pads, and the number of the second main chips 300 corresponding to one first main chip 200 may be four, and the chip types of the four second main chips 300 may be the same or different.
Referring to fig. 7, fig. 7 is a flowchart illustrating an embodiment corresponding to step S102 in fig. 1, in step S102, the first package and the second package are disposed on the package substrate at an interval, and a connection chip is disposed in an interval area between the first package and the second package, which specifically includes the following steps:
s301, the first packaging body and the second packaging body are arranged on the packaging substrate with the flat surface at intervals.
Specifically, referring to fig. 8a, fig. 8a is a schematic structural diagram of an embodiment corresponding to step S301 in fig. 7. After the first package 20 and the second package 30 are provided, the first package 20 and the second package 30 are disposed on the package substrate 500 with a flat surface at intervals, and the first package 20 and the second package 30 are electrically connected to the package substrate 500 through the first solder 24.
S302, the non-functional surface of the connection chip faces the package substrate and is arranged in the interval area between the first package body and the second package body.
Specifically, please refer to fig. 8b, wherein fig. 8b is a schematic structural diagram of an embodiment corresponding to step S302 in fig. 7. The non-functional surface 410 of the connection chip 40 faces the package substrate 500 and is disposed in the gap region between the first package 20 and the second package 30. The non-functional surface 410 of the connection chip 40 may be in direct contact with the package substrate 500, or may be bonded to the package substrate 500 by an adhesive layer.
In another embodiment, referring to fig. 9, fig. 9 is a flowchart illustrating another embodiment corresponding to step S102 in fig. 1, in which step S102, the first package and the second package are disposed on the package substrate at an interval, and a connection chip is disposed in an interval region between the first package and the second package, and the method specifically includes the following steps:
s401, arranging the connecting chip on the packaging substrate with the flat surface, wherein the non-functional surface of the connecting chip faces the packaging substrate.
Specifically, referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment corresponding to step S401 in fig. 9. In the present embodiment, after the first package 20 and the second package 30 are provided, the connection chip 40 is disposed on the package substrate 500 having a flat surface without processing the first package 20 and the second package 30, and the non-functional surface 410 of the connection chip 40 faces the package substrate 500. The non-functional surface 410 of the connection chip 40 may be in direct contact with the package substrate 500, or may be bonded to the package substrate 500 by an adhesive layer.
S402, arranging the first packaging body and the second packaging body at two opposite sides of the connecting chip at intervals.
Specifically, referring to fig. 8b, in the present embodiment, after the connection chip 40 is disposed on the package substrate 500, the first package body 20 and the second package body 30 are disposed on two opposite sides of the connection chip 40 at an interval, and the first package body 20 and the second package body 30 are electrically connected to the package substrate 500 through the first solder 24.
Step S401 and step S402 in fig. 9 and step S301 and step S302 in fig. 7 are merely exchanged in sequence, and the sequence of electrically connecting the first package 20 and the second package 30 and the connection chip 40 with the package substrate 500 is exchanged, so that the same structure is finally obtained, as shown in fig. 8 b.
In the above embodiment, with reference to fig. 10, before the connecting chip 40 is disposed on the package substrate 500 with a flat surface, the second conductive pillars 25 may be respectively formed at the pad positions of the functional surface 411 of the connecting chip 40, so as to be electrically connected to the first main chip and the second main chip through the second conductive pillars 25.
In another embodiment, referring to fig. 11, fig. 11 is a flowchart illustrating another embodiment corresponding to step S102 in fig. 1, in which step S102, the first package and the second package are disposed on the package substrate at an interval, and a connection chip is disposed in an interval region between the first package and the second package, and the method specifically includes the following steps:
s501, arranging the first packaging body and the second packaging body on a packaging substrate with grooves on the surface at intervals, wherein the grooves are correspondingly arranged in the interval areas of the first packaging body and the second packaging body.
Specifically, referring to fig. 12a, fig. 12a is a schematic structural diagram of an embodiment corresponding to step S501 in fig. 11. After the first package body 20 and the second package body 30 are provided, the first package body 20 and the second package body 30 are disposed on the package substrate 800 with the surface provided with the grooves at intervals, and the grooves are correspondingly disposed in the interval areas of the first package body 20 and the second package body 30. The first package body 20 and the second package body 30 are electrically connected to the package substrate 800 through the first solder 24.
S502, the non-functional surface of the connection chip faces the package substrate and is arranged in the interval area between the first package body and the second package body, and at least part of the connection chip is located in the groove.
Specifically, referring to fig. 12b, fig. 12b is a schematic structural diagram of an embodiment corresponding to step S502 in fig. 11. After step S501, the non-functional surface 410 of the connecting chip 40 is disposed toward the package substrate 800 in the gap region between the first package 20 and the second package 30, and at least a portion of the connecting chip 40 is located in the recess, and fig. 12b schematically illustrates a situation where the connecting chip 40 is partially located in the recess.
In another embodiment, referring to fig. 13, fig. 13 is a flowchart illustrating another embodiment corresponding to step S102 in fig. 1, in which step S102, the first package and the second package are disposed on the package substrate at an interval, and a connection chip is disposed in an interval region between the first package and the second package, and the method specifically includes the following steps:
s601, arranging the connecting chip on the packaging substrate with the groove on the surface, wherein at least part of the connecting chip is positioned in the groove, and the non-functional surface of the connecting chip faces the packaging substrate.
Specifically, referring to fig. 14, fig. 14 is a schematic structural diagram of an embodiment corresponding to step S601 in fig. 13. After providing the first package 20 and the second package 30, the connection chip 40 is disposed on the package substrate 800 with the recess disposed on the surface thereof, and at least a portion of the connection chip 40 is disposed in the recess, the non-functional surface 410 of the connection chip 40 faces the package substrate 800, and fig. 14 schematically illustrates a situation where the connection chip 40 is partially disposed in the recess.
S602, the first packaging body and the second packaging body are arranged on two opposite sides of the connecting chip at intervals.
Specifically, referring to fig. 12b, in the present embodiment, after the connecting chip 40 is disposed on the package substrate 800 with the recess on the surface, the first package body 20 and the second package body 30 are disposed on two opposite sides of the connecting chip 40 at an interval, and the first package body 20 and the second package body 30 are electrically connected to the package substrate 800 through the first solder 24.
Step S601 and step S602 in fig. 13 and step S501 and step S502 in fig. 11 are merely exchanged in sequence, and the sequence of electrically connecting the first package 20 and the second package 30 and the connection chip 40 with the package substrate 800 is exchanged, so that the same structure is finally obtained, as shown in fig. 12 b.
In the above embodiment, with reference to fig. 14, before the connecting chip 40 is disposed on the package substrate 800 with the recess formed on the surface thereof, the second conductive pillars 25 may be respectively formed at the pad positions of the functional surface 411 of the connecting chip 400, so as to be electrically connected to the first main chip and the second main chip through the second conductive pillars 25.
Further, with reference to fig. 6, in step S102, the first package and the second package are disposed on the package substrate at an interval, and the connection chip is disposed in an interval region between the first package and the second package, and then the method includes the following steps: the first main chip 200 is disposed on a side surface of the first package body 20 away from the package substrate 500, and the second main chip 300 is disposed on a side surface of the second package body 30 away from the package substrate 500.
In another embodiment, referring to fig. 15, fig. 15 is a schematic structural diagram of another embodiment corresponding to step S102 in fig. 1, a surface of the package substrate may also be provided with a groove, after the structure shown in fig. 12b is formed, the first main chip 200 is disposed on a side surface of the first package body 20 away from the package substrate 800, and the second main chip 300 is disposed on a side surface of the second package body 30 away from the package substrate 800, so as to obtain a package device having a structure similar to that shown in fig. 6, so that the signal transmission regions 600 of the first main chip 200 and the second main chip 300 are electrically connected through the connection chip 40, and the non-signal transmission regions 700 of the first main chip 200 and the second main chip 300 are electrically connected to the package substrate 800 through the first conductive pillars 21.
In addition, referring to fig. 16, fig. 16 is a schematic structural diagram of an embodiment corresponding to the steps included before step S102 in fig. 1, in the above embodiment, before the first main chip 200 and the second main chip 300 are electrically connected to the package substrate, the third conductive pillars 26 may be respectively formed at the pad positions of the signal transmission regions 600 of the first main chip 200 and the second main chip 300, the fourth conductive pillars 27 may be respectively formed at the pad positions of the non-signal transmission regions 700 of the first main chip 20 and the second main chip 30, and further the second solders 28 are formed on the third conductive pillars 26 and the fourth conductive pillars 27, so as to facilitate the electrical connection between the first main chip 20 and the second main chip 30 and the package substrate or the connection chip, where fig. 15 schematically illustrates the second main chip 300.
When the package substrate is the package substrate 500 with a flat surface, as shown in fig. 6, in the package device formed after the step S102 is performed, a distance h is between the functional surface 211 of the first main chip 200 and the surface of the package substrate 500 close to the first conductive pillar 211Greater than or equal to the distance h between the functional side 211 of the first main chip 200 and the non-functional side 410 of the connection chip 402H is schematically shown in FIG. 61＝h2The case (1). When the package substrate is the package substrate 800 with the surface provided with the groove, as shown in fig. 15, a distance h from the functional surface 211 of the first main chip 200 to the surface of the package substrate 800 close to the first conductive pillar 21 is3Is smaller than the distance h between the functional side 211 of the first main chip 200 and the non-functional side 410 of the connection chip 404。
Further, in another embodiment, after step S102 is performed to form the packaged device shown in fig. 6 or fig. 15, the method further includes: an underfill 29 is formed between the first and second main chips 200 and 300 and the package substrate 500. The underfill 29 can make the connection between the first and second main chips 300 and 400 and the first and second packages 20 and 30 more stable. Specifically, referring to fig. 17, fig. 17 is a schematic structural diagram of an embodiment corresponding to the step included after step S102 in fig. 1, and schematically illustrates the structure of the package substrate with a flat surface shown in fig. 6.
In the packaging device formed by the embodiment, the signal transmission areas of the two main chips are connected by adopting the connecting chip, so that the signal transmission rate between the main chips can be improved, and the performance of the packaging device is improved; the non-signal transmission area of the main chip is connected with the packaging substrate by adopting a common conductive column, so that the packaging cost can be reduced.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A chip packaging method is characterized by comprising the following steps:
providing a first packaging body and a second packaging body, wherein the first packaging body and the second packaging body respectively comprise a plurality of first conductive columns and a first plastic packaging layer, and the first plastic packaging layer covers the side faces of the first conductive columns;
arranging the first packaging body and the second packaging body on a packaging substrate at intervals, arranging a connecting chip in an interval area between the first packaging body and the second packaging body, and respectively arranging a first main chip and a second main chip on one sides of the first packaging body and the second packaging body, which are far away from the packaging substrate; the signal transmission areas of the first main chip and the second main chip are arranged adjacently, the bonding pads of the signal transmission areas of the first main chip and the second main chip are electrically connected with the connecting chip, and the bonding pads of the non-signal transmission areas of the first main chip and the second main chip are electrically connected with the first conductive columns.
2. The chip packaging method according to claim 1, wherein the providing the first package or the providing the second package comprises:
providing a removable carrier plate, wherein the carrier plate is defined with at least one area;
forming a plurality of said first conductive pillars in each of said regions;
forming a first plastic package layer on one side of the carrier plate, where the first conductive pillars are arranged, and exposing the surface of one side, away from the carrier plate, of the first conductive pillar from the first plastic package layer;
and removing the carrier plate.
3. The chip packaging method according to claim 2, wherein the disposing the first package and the second package on the package substrate at intervals comprises:
and forming a first solder on one side surface of the first conductive pillar facing the package substrate, or forming a first solder on one side surface of the package substrate.
4. The chip packaging method according to claim 1, wherein the disposing the first package and the second package on a package substrate at an interval, and a connection chip is disposed in an interval area between the first package and the second package, comprising:
arranging the first packaging body and the second packaging body on the packaging substrate with a flat surface at intervals;
and the non-functional surface of the connecting chip faces the packaging substrate and is arranged in a spacing area between the first packaging body and the second packaging body.
5. The chip packaging method according to claim 1, wherein the disposing the first package and the second package on a package substrate at an interval, and a connection chip is disposed in an interval area between the first package and the second package, comprising:
arranging the connecting chip on the packaging substrate with a flat surface, wherein the non-functional surface of the connecting chip faces the packaging substrate;
and arranging the first packaging body and the second packaging body at two opposite sides of the connecting chip at intervals.
6. The chip packaging method according to claim 1, wherein the disposing the first package and the second package on a package substrate at an interval, and a connection chip is disposed in an interval area between the first package and the second package, comprising:
arranging the first packaging body and the second packaging body on the packaging substrate with grooves on the surface at intervals, wherein the grooves are correspondingly arranged in the interval areas of the first packaging body and the second packaging body;
and enabling the non-functional surface of the connecting chip to face the packaging substrate, and arranging the non-functional surface of the connecting chip to face the packaging substrate in a spacing area between the first packaging body and the second packaging body, wherein at least part of the connecting chip is positioned in the groove.
7. The chip packaging method according to claim 1, wherein the disposing the first package and the second package on a package substrate at an interval, and a connection chip is disposed in an interval area between the first package and the second package, comprising:
arranging the connecting chip on the packaging substrate with a groove on the surface, wherein at least part of the connecting chip is positioned in the groove, and the non-functional surface of the connecting chip faces the packaging substrate;
and arranging the first packaging body and the second packaging body at two opposite sides of the connecting chip at intervals.
8. The chip packaging method according to any one of claims 4 to 7, wherein the disposing the first package and the second package on a package substrate at an interval, and a connection chip is disposed in an interval area between the first package and the second package, and thereafter, the method comprises:
and arranging the first main chip on one side surface of the first packaging body far away from the packaging substrate, and arranging the second main chip on one side surface of the second packaging body far away from the packaging substrate.
9. The chip packaging method according to claim 8, wherein the disposing the first main chip on a side surface of the first package body away from the package substrate and disposing the second main chip on a side surface of the second package body away from the package substrate comprises:
and forming underfill between the first main chip and the second main chip and the packaging substrate.
10. The chip packaging method according to claim 1,
the first package body and the second package body comprise a plurality of package units, each package unit comprises a plurality of first conductive posts, and the first plastic package layers of the adjacent package units are connected with each other;
before the first package body and the second package body are arranged on the package substrate at intervals, the method includes: cutting off the area between the adjacent packaging units to obtain the first packaging body or the second packaging body containing the single packaging unit.
CN202010367772.4A 2020-04-30 2020-04-30 Chip packaging method Active CN111554627B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010367772.4A CN111554627B (en) 2020-04-30 2020-04-30 Chip packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010367772.4A CN111554627B (en) 2020-04-30 2020-04-30 Chip packaging method

Publications (2)

Publication Number Publication Date
CN111554627A true CN111554627A (en) 2020-08-18
CN111554627B CN111554627B (en) 2022-10-11

Family

ID=72000449

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010367772.4A Active CN111554627B (en) 2020-04-30 2020-04-30 Chip packaging method

Country Status (1)

Country Link
CN (1) CN111554627B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111415A (en) * 2002-09-13 2004-04-08 Sony Corp Circuit board, its manufacturing method, semiconductor device, and its manufacturing method
US20150303174A1 (en) * 2014-04-17 2015-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same
CN105655310A (en) * 2015-12-31 2016-06-08 华为技术有限公司 Encapsulation structure, electronic equipment and encapsulation method
US20160307870A1 (en) * 2015-04-14 2016-10-20 Amkor Technology, Inc. Semiconductor package with high routing density patch
CN107041137A (en) * 2014-09-05 2017-08-11 英帆萨斯公司 Multi-chip module and its preparation method
US20190051604A1 (en) * 2017-08-14 2019-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111415A (en) * 2002-09-13 2004-04-08 Sony Corp Circuit board, its manufacturing method, semiconductor device, and its manufacturing method
US20150303174A1 (en) * 2014-04-17 2015-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same
CN107041137A (en) * 2014-09-05 2017-08-11 英帆萨斯公司 Multi-chip module and its preparation method
US20160307870A1 (en) * 2015-04-14 2016-10-20 Amkor Technology, Inc. Semiconductor package with high routing density patch
CN105655310A (en) * 2015-12-31 2016-06-08 华为技术有限公司 Encapsulation structure, electronic equipment and encapsulation method
US20190051604A1 (en) * 2017-08-14 2019-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same

Also Published As

Publication number Publication date
CN111554627B (en) 2022-10-11

Similar Documents

Publication Publication Date Title
TW200917391A (en) Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication
JP2015095655A (en) Semiconductor package and manufacturing method of the same
KR20110128748A (en) Integrated circuit packaging system with dual side connection and method of manufacture thereof
JP2009099697A (en) Semiconductor apparatus and method of manufacturing the same
TWI538123B (en) Integrated circuit packaging system with dual side connection and method of manufacture thereof
CN111554613A (en) Chip packaging method
CN111554622B (en) Chip packaging method
US8304918B2 (en) Method for manufacturing electronic device and electronic device
CN111554617A (en) Chip packaging method
WO2022110936A1 (en) Power element packaging structure and manufacturing method therefor
CN111554620A (en) Chip packaging method
CN111554627B (en) Chip packaging method
CN111554625A (en) Chip packaging method
KR20230010399A (en) Semiconductor package
CN111554624B (en) Chip packaging method
TWI766271B (en) Electronic package and method for fabricating the same
CN111554616B (en) Chip packaging method
CN111554632B (en) Chip packaging method
CN111554618A (en) Chip packaging method
CN111554655A (en) Semiconductor packaging device
CN112490209A (en) Semiconductor packaging device
CN111554626A (en) Chip packaging method
CN111863790A (en) Semiconductor packaging device
CN111554631A (en) Chip packaging method
CN111554619A (en) Chip packaging method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant