JP2003007896A - Multilayer printed-wiring board - Google Patents

Multilayer printed-wiring board

Info

Publication number
JP2003007896A
JP2003007896A JP2001192925A JP2001192925A JP2003007896A JP 2003007896 A JP2003007896 A JP 2003007896A JP 2001192925 A JP2001192925 A JP 2001192925A JP 2001192925 A JP2001192925 A JP 2001192925A JP 2003007896 A JP2003007896 A JP 2003007896A
Authority
JP
Japan
Prior art keywords
layer
resin
chip
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001192925A
Other languages
Japanese (ja)
Other versions
JP4243922B2 (en
Inventor
Yoshinori Takenaka
芳紀 竹中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2001192925A priority Critical patent/JP4243922B2/en
Publication of JP2003007896A publication Critical patent/JP2003007896A/en
Application granted granted Critical
Publication of JP4243922B2 publication Critical patent/JP4243922B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed-wiring board which can directly electrically connect to an IC chip without a lead component. SOLUTION: In the multiplayer printed-wiring board, the IC chip 20 is located in a core board 30 in advance, a transition layer 38 consisting of a first thin film layer 33, a second thin film layer 36, and a thick film 37 are located on a copper die pad 24 of the IC chip 20. Thereby, an electrical connection between the IC chip and the multiplayer printed-circuit board can be attained without a lead component and a sealing resin. Moreover, a connectivity and its reliability between the die pad 24 and a via hole 60 can be improved by providing the transition layer 38 composed of a plurality of layers on the die pad 24.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、ビルドアップ多層
プリント配線板に関し、特にＩＣチップなどの電子部品
を内蔵する多層プリント配線板に関するのもである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board incorporating electronic parts such as IC chips.

【０００２】[0002]

【従来の技術】ＩＣチップは、ワイヤーボンディング、
ＴＡＢ、フリップチップなどの実装方法によって、プリ
ント配線板との電気的接続を取っていた。ワイヤーボン
ディングは、プリント配線板にＩＣチップを接着剤によ
りダイボンディングさせて、該プリント配線板のパッド
とＩＣチップのパッドとを金線などのワイヤーで接続さ
せた後、ＩＣチップ並びにワイヤーを守るために熱硬化
性樹脂あるいは熱可塑性樹脂などの封止樹脂を施してい
た。ＴＡＢは、ＩＣチップのバンプとプリント配線板の
パッドとをリードと呼ばれる線を半田などによって一括
して接続させた後、樹脂による封止を行っていた。フリ
ップチップは、ＩＣチップとプリント配線板のパッド部
とをバンプを介して接続させて、バンプとの隙間に樹脂
を充填させることによって行っていた。2. Description of the Related Art IC chips are wire bonded,
The electrical connection to the printed wiring board was made by a mounting method such as TAB or flip chip. Wire bonding is performed by die-bonding an IC chip to a printed wiring board with an adhesive and connecting the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire to protect the IC chip and the wire. A sealing resin such as a thermosetting resin or a thermoplastic resin has been applied to. In the TAB, wires called leads are collectively connected to the bumps of the IC chip and the pads of the printed wiring board with solder or the like, and then sealed with resin. The flip chip is performed by connecting the IC chip and the pad portion of the printed wiring board via a bump and filling a resin in a gap between the bump and the bump.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、それぞ
れの実装方法は、ＩＣチップとプリント配線板の間に接
続用のリード部品（ワイヤー、リード、バンプ）を介し
て電気的接続を行っている。それらの各リード部品は、
切断、腐食し易く、これにより、ＩＣチップとの接続が
途絶えたり、誤作動の原因となることがあった。また、
それぞれの実装方法は、ＩＣチップを保護するためにエ
ポキシ樹脂等の熱可塑性樹脂によって封止を行っている
が、その樹脂を充填する際に気泡を含有すると、気泡が
起点となって、リード部品の破壊やＩＣパッドの腐食、
信頼性の低下を招いてしまう。熱可塑性樹脂による封止
は、それぞれの部品に合わせて樹脂装填用プランジャ
ー、金型を作成する必要が有り、また、熱硬化性樹脂で
あってもリード部品、ソルダーレジストなどの材質など
を考慮した樹脂を選定しなくては成らないために、それ
ぞれにおいてコスト的にも高くなる原因にもなった。However, in each of the mounting methods, electrical connection is made between the IC chip and the printed wiring board via connecting lead parts (wires, leads, bumps). Each of those lead parts is
It is easily cut and corroded, which may cause a disconnection or a malfunction of the IC chip. Also,
In each mounting method, sealing is performed with a thermoplastic resin such as an epoxy resin in order to protect the IC chip. However, if air bubbles are included when the resin is filled, the air bubbles serve as a starting point and lead components. Destruction of IC and IC pad corrosion,
This leads to a decrease in reliability. For thermoplastic resin encapsulation, it is necessary to create a resin loading plunger and mold according to each component.Also, even for thermosetting resin, consider the lead component, solder resist, and other materials. Since such a resin must be selected, it also causes a cost increase in each case.

【０００４】本発明は上述した課題を解決するためにな
されたものであり、その目的とするところは、リード部
品を介さないで、ＩＣチップと直接電気的接続し得る多
層プリント配線板を提案することを目的とする。The present invention has been made to solve the above problems, and an object thereof is to propose a multilayer printed wiring board which can be directly electrically connected to an IC chip without using lead parts. The purpose is to

【０００５】[0005]

【課題を解決するための手段】本発明者は鋭意研究した
結果、樹脂絶縁性基板に開口部、通孔やザグリ部を設け
てＩＣチップなどの電子部品を予め内蔵させて、層間絶
縁層を積層し、該ＩＣチップのパッド上に、フォトエッ
チングあるいはレーザにより、ビアを設けて、導電層で
ある導体回路を形成させた後、更に、層間絶縁層と導電
層を繰り返して、多層プリント配線板を設けることによ
って、封止樹脂を用いず、リードレス、バンプレスによ
ってＩＣチップとの電気的接続を取ることができる構造
を案出した。Means for Solving the Problems As a result of earnest research by the present inventor, an opening, a through hole or a counterbore portion is provided in a resin insulating substrate to preliminarily incorporate an electronic component such as an IC chip, and an interlayer insulating layer is formed. After stacking, vias are provided on the pads of the IC chip by photoetching or laser to form a conductive circuit which is a conductive layer, an interlayer insulating layer and a conductive layer are further repeated to form a multilayer printed wiring board. The present invention has devised a structure in which the electric connection with the IC chip can be made by leadless or bumpless without using the sealing resin.

【０００６】更に、本発明者は、樹脂絶縁性基板に開口
部、通孔やザグリ部を設けてＩＣチップなどの電子部品
を予め内蔵させて、層間絶縁層を積層し、該ＩＣチップ
のパッド上に、フォトエッチングあるいはレーザによ
り、ビアを設けて、導電層である導体回路を形成させた
後、更に、層間絶縁層と導電層を繰り返して、多層プリ
ント配線板の表層にもＩＣチップ、コンデンサなどの電
子部品を実装させた構造を提案した。それによって、封
止樹脂を用いず、リードレス、バンプレスによってＩＣ
チップとの電気的接続を取ることができる。また、それ
ぞれの機能が異なるＩＣチップ、コンデンサなどの電子
部品を実装させることができ、より高機能な多層プリン
ト配線板を得ることができる。具体例として、内蔵ＩＣ
チップとして演算機能を有するＩＣチップを埋め込み、
表層には、キャシュメモリ、コンデンサを実装させるこ
とによって、ＩＣチップとキャシュメモリ、コンデンサ
とを近接して配置することが可能になる。Further, the present inventor further provided an opening, a through hole, and a countersunk portion in a resin insulating substrate to preliminarily incorporate an electronic component such as an IC chip, stack an interlayer insulating layer, and pad the IC chip. Vias are provided on the top by photo-etching or laser to form a conductive circuit which is a conductive layer, and then an interlayer insulating layer and a conductive layer are further repeated to form an IC chip and a capacitor on the surface layer of the multilayer printed wiring board. We proposed a structure with electronic components such as. As a result, IC can be obtained by leadless or bumpless without using sealing resin.
An electrical connection with the chip can be made. In addition, electronic parts such as IC chips and capacitors having different functions can be mounted, and a higher-performance multilayer printed wiring board can be obtained. As a specific example, built-in IC
An IC chip having an arithmetic function is embedded as a chip,
By mounting the cache memory and the capacitor on the surface layer, it becomes possible to arrange the IC chip and the cache memory and the capacitor close to each other.

【０００７】また更に、本発明者は、鋭意研究した結
果、樹脂絶縁性基板に開口部、通孔やザグリ部を設けて
ＩＣチップなどの電子部品を予め収容させて、該ＩＣチ
ップのパッドには導電層からなるトラジション層を形成
させることを案出した。トラジション層の上層には層間
絶縁層を積層し、該トラジション層上に、フォトエッチ
ングあるいはレーザにより、ビアを設けて、導電層であ
る導体回路を形成させた後、更に、層間絶縁層と導電層
を繰り返して、多層プリント配線板を設けることによっ
て、封止樹脂を用いず、リードレス、バンプレスによっ
てＩＣチップとの電気的接続を取ることができる。ま
た、ＩＣチップ部分にトラジション層が形成されている
ことから、ＩＣチップ部分には平坦化されるので、上層
の層間絶縁層も平坦化されて、膜厚みも均一になる。更
に、前述のトラジション層によって、上層のビアを形成
する際も、形状の安定性を保つことができる。Further, as a result of earnest research, the present inventor has provided an opening, a through hole or a counterbore portion in a resin insulating substrate to preliminarily accommodate an electronic component such as an IC chip, and a pad of the IC chip. Devised to form a transition layer consisting of a conductive layer. An interlayer insulating layer is laminated on the transition layer, a via is provided on the transition layer by photoetching or laser to form a conductor circuit as a conductive layer, and then an interlayer insulating layer is formed. By providing the multilayer printed wiring board by repeating the conductive layer, electrical connection with the IC chip can be made by leadless or bumpless without using the sealing resin. Further, since the transition layer is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer is also flattened and the film thickness becomes uniform. Further, the above-mentioned transition layer can maintain the shape stability even when forming the via of the upper layer.

【０００８】銅製のパッドを用いることで、従来のアル
ミニウムなどのパッドと比べて電気特性が向上する。し
かしながら、表面が酸化や窒化などされ易く、酸化銅、
窒化銅が形成されている。そのために、銅単体では電気
特性が向上したのであるが、表面に形成された金属がそ
の特性を劣化させていた。また、銅であるパッド上に直
接金属を形成させても、金属の種類や形成方法によって
は拡散してしまうために、形成不良や未形成を引き起こ
してしまうこともある。パッド上に形成されるには酸化
被膜の影響もある。そのために、パッド上にトランジシ
ョン層を設けることにより、電気特性と密着性が確保さ
れる。By using the pad made of copper, the electric characteristics are improved as compared with the conventional pad made of aluminum or the like. However, the surface is easily oxidized or nitrided, and copper oxide,
Copper nitride is formed. For this reason, although the electrical characteristics were improved with the simple substance of copper, the metal formed on the surface deteriorated the characteristics. Further, even if a metal is directly formed on the pad made of copper, it may be diffused depending on the kind of the metal and the forming method, so that defective formation or non-formation may occur. There is also an influence of an oxide film on the formation on the pad. Therefore, by providing the transition layer on the pad, the electrical characteristics and the adhesiveness are secured.

【０００９】本発明で定義されるトランジション層につ
いて説明する。トランジション層は、従来のＩＣチップ
実装技術を用いることなく、半導体素子であるＩＣチッ
プとプリント配線板と直接接続を取るために設けられた
中間の仲介層を意味する。特徴としては、２層以上の金
属層で形成され、半導体素子であるＩＣチップのダイパ
ッドよりも大きくさせることにある。それによって、電
気的接続や位置合わせ性を向上させるものであり、か
つ、ダイパッドにダメージを与えることなくレーザやフ
ォトエッチングによるバイアホール加工を可能にするも
のである。そのため、プリント配線板へのＩＣチップの
埋め込み、収容、収納や接続を確実にすることができ
る。また、トランジション層上には、直接、プリント配
線板の導体層である金属を形成することを可能にする。
その導体層の一例としては、層間樹脂絶縁層のバイアホ
ールや基板上のスルーホールなどがある。The transition layer defined in the present invention will be described. The transition layer means an intermediate intermediary layer provided for making a direct connection between the IC chip which is a semiconductor element and the printed wiring board without using the conventional IC chip mounting technology. The feature is that it is formed of two or more metal layers and is larger than the die pad of the IC chip which is a semiconductor element. This improves electrical connection and alignment, and enables via hole processing by laser or photo-etching without damaging the die pad. Therefore, it is possible to reliably embed, store, store, and connect the IC chip in the printed wiring board. Further, it is possible to directly form a metal, which is a conductor layer of the printed wiring board, on the transition layer.
Examples of the conductor layer include a via hole in the interlayer resin insulation layer and a through hole on the substrate.

【００１０】ＩＣチップのパッドにトラジション層を設
ける理由は、次の通りである。第１にダイパッドがファ
インかつ小サイズになると、ビアを形成する際のアライ
メントが困難になるので、トラジション層を設けてアラ
イメントをし易くする。トラジション層を設ければ、ダ
イパッドピッチ１５０μｍ以下、パッドサイズ２０μｍ
以下でもビルドアップ層が安定して形成できる。トラジ
ション層を形成させていないダイパッドのままで、フォ
トエッチングにより層間絶縁層のビアを形成させると、
ビア径がダイパッド径よりも大きいと、ビア底残査除
去、層間樹脂絶縁層表面粗化処理として行うデスミア処
理時に、ダイパッド表面の保護層であるポリイミド層を
溶解、損傷する。一方、レーザの場合、ビア径がダイパ
ッド径より大きいときには、ダイパッド及びパシベーシ
ョン、ポリミド層（ＩＣの保護膜）がレーザによって破
壊される。更に、ＩＣチップのパッドが非常に小さく、
ビア径がダイパッドサイズより大きくなると、フォトエ
ッチング法でも、レーザ法でも位置合わせが非常に困難
であり、ダイパッドとビアとの接続不良が多発する。The reason for providing the transition layer on the pad of the IC chip is as follows. First, when the die pad is fine and small in size, alignment becomes difficult when forming vias. Therefore, a transition layer is provided to facilitate alignment. If a transition layer is provided, the die pad pitch is 150 μm or less, and the pad size is 20 μm.
The build-up layer can be stably formed even under the following conditions. When the via of the interlayer insulating layer is formed by photoetching with the die pad on which the transition layer is not formed,
If the diameter of the via is larger than the diameter of the die pad, the polyimide layer, which is the protective layer on the surface of the die pad, is dissolved and damaged during the residual removal of the via bottom and the desmearing treatment performed as the surface roughening treatment of the interlayer resin insulation layer. On the other hand, in the case of a laser, when the via diameter is larger than the die pad diameter, the die pad, the passivation, and the polyimide layer (IC protective film) are destroyed by the laser. Furthermore, the pad of the IC chip is very small,
When the via diameter is larger than the die pad size, it is very difficult to perform alignment by the photoetching method and the laser method, and connection failure between the die pad and the via often occurs.

【００１１】これに対して、ダイパッド上にトラジショ
ン層を設けることで、ダイパッドピッチ１５０μｍ以
下、パッドサイズ２０μｍ以下になってもダイパッド上
にビアを確実に接続させることができ、パッドとビアと
の接続性や信頼性を向上させる。更に、ＩＣチップのダ
イパッド上により大きな径のトラジション層を介在させ
ることで、デスミヤ、めっき工程などの後工程の際に、
酸やエッチング液に浸漬させたり、種々のアニール工程
を経ても、ダイパッド周囲のＩＣの保護膜（パシベーシ
ョン、ポリミド層）を溶解、損傷する危険がなくなる。On the other hand, by providing the transition layer on the die pad, the via can be surely connected to the die pad even if the die pad pitch is 150 μm or less and the pad size is 20 μm or less, and the pad and the via are connected to each other. Improve connectivity and reliability. Furthermore, by interposing a transition layer having a larger diameter on the die pad of the IC chip, it is possible to perform a post-process such as a desmear or a plating process.
There is no risk of dissolving and damaging the IC protective film (passivation, polyimide layer) around the die pad even if it is dipped in an acid or etching solution or after various annealing processes.

【００１２】それぞれに多層プリント配線板だけで機能
を果たしてもいるが、場合によっては半導体装置として
のパッケージ基板としての機能させるために外部基板で
あるマザーボードやドーターボードとの接続のため、Ｂ
ＧＡ、半田バンプやＰＧＡ（導電性接続ピン）を配設さ
せてもよい。また、この構成は、従来の実装方法で接続
した場合よりも配線長を短くできて、ループインダクタ
ンスも低減できる。Although each of them functions only by a multilayer printed wiring board, in some cases, in order to function as a package board as a semiconductor device, the board is connected to an external board such as a mother board or a daughter board.
GA, solder bumps, or PGA (conductive connection pins) may be provided. Further, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case where the connection is performed by the conventional mounting method.

【００１３】本願発明に用いられるＩＣチップなどの電
子部品を内蔵させる樹脂製基板としては、エポキシ樹
脂、ＢＴ樹脂、フェノール樹脂などにガラスエポキシ樹
脂などの補強材や心材を含浸させた樹脂、エポキシ樹脂
を含浸させたプリプレグを積層させたものなどが用いら
れるが、一般的にプリント配線板で使用されるものを用
いることができる。それ以外にも両面銅張積層板、片面
板、金属膜を有しない樹脂板、樹脂フィルムを用いるこ
とができる。ただし、３５０℃以上の温度を加えると樹
脂は、溶解、炭化をしてしまう。また、セラミックで
は、外形加工性に劣るので使用することができない。As a resin substrate for incorporating an electronic component such as an IC chip used in the present invention, epoxy resin, BT resin, phenol resin or the like impregnated with a reinforcing material or core material such as glass epoxy resin, epoxy resin A laminate of prepregs impregnated with is used, but those commonly used in printed wiring boards can be used. Besides, a double-sided copper clad laminate, a single-sided plate, a resin plate having no metal film, or a resin film can be used. However, if a temperature of 350 ° C. or higher is applied, the resin will melt and carbonize. Also, ceramics cannot be used because they have poor external formability.

【００１４】コア基板等の予め樹脂製絶縁基板にＩＣチ
ップなどの電子部品を収容するキャビティをザグリ、通
孔、開口を形成したものに該ＩＣチップを接着剤などで
接合させる。The IC chip is bonded with an adhesive or the like to a resin insulating substrate such as a core substrate in which a cavity for accommodating an electronic component such as an IC chip is previously formed with a counterbore, a through hole and an opening.

【００１５】ＩＣチップを内蔵させたコア基板の全面に
蒸着、スパッタリング、無電解めっきなどを行い、全面
に導電性の金属膜（第１薄膜層）を形成させる。その金
属としては、スズ、クロム、チタン、ニッケル、亜鉛、
コバルト、金、銅などがよい。厚みとしては、０．００
１〜２．０μｍの間で形成させるのがよい。０．００１
μｍ未満では、全面に均一に積層できない。２．０μｍ
を越えるものを形成させることは困難であり、効果が高
まるのもでもなかった。クロムの場合には０．１μｍの
厚みが望ましい。Vapor deposition, sputtering, electroless plating or the like is performed on the entire surface of the core substrate containing the IC chip to form a conductive metal film (first thin film layer) on the entire surface. The metals include tin, chromium, titanium, nickel, zinc,
Cobalt, gold, copper, etc. are good. The thickness is 0.00
It is preferable to form it between 1 and 2.0 μm. 0.001
If it is less than μm, it cannot be uniformly laminated on the entire surface. 2.0 μm
It has been difficult to form more than 10%, and the effect has not been enhanced. In the case of chromium, a thickness of 0.1 μm is desirable.

【００１６】第１薄膜層により、ダイパッドの被覆を行
い、トランジション層とＩＣチップにダイパッドとの界
面の密着性を高めることができる。また、これら金属で
ダイパッドを被覆することで、界面への湿分の侵入を防
ぎ、ダイパッドの溶解、腐食を防止し、信頼性を高める
ことができる。また、この第１薄膜層によって、リード
のない実装方法によりＩＣチップとの接続を取ることが
できる。ここで、銅、クロム、ニッケル、チタンを用い
ることが、金属との密着性がよく、また、界面への湿分
の侵入を防ぐために望ましい。ダイパッドが銅から成る
ため、銅が最適である。The first thin film layer can cover the die pad to improve the adhesion between the transition layer and the IC chip at the interface with the die pad. Further, by covering the die pad with these metals, it is possible to prevent moisture from entering the interface, prevent the die pad from melting and corroding, and improve the reliability. In addition, the first thin film layer enables connection with the IC chip by a leadless mounting method. Here, it is preferable to use copper, chromium, nickel, or titanium in order to obtain good adhesion to a metal and to prevent moisture from entering the interface. Copper is the best choice because the die pad is made of copper.

【００１７】第１薄膜層上に、スパッタ、蒸着、又は、
無電解めっきにより第２薄膜層を形成させる。その金属
としてはニッケル、銅、金、銀などがある。電気特性、
経済性、また、ダイパッドが銅からなり、後程で形成さ
れる厚付け層は主に銅であることから、銅を用いるとよ
い。On the first thin film layer, sputtering, vapor deposition, or
The second thin film layer is formed by electroless plating. The metal includes nickel, copper, gold and silver. Electrical characteristics,
It is preferable to use copper because it is economical and the die pad is made of copper, and the thick layer formed later is mainly copper.

【００１８】ここで第２薄膜層を設ける理由は、第１薄
膜層では、後述する厚付け層を形成するための電解めっ
き用のリードを取ることができ難いためである。第２薄
膜層３６は、厚付けのリードとして用いられる。その厚
みは０．０１〜５．０μｍの範囲で行うのがよい。０．
０１μｍ未満では、リードとしての役割を果たし得ず、
５．０μｍを越えると、エッチングの際、下層の第１薄
膜層がより多く削れて隙間ができてしまい、湿分が侵入
し易くなり、信頼性が低下するからである。電気特性、
経済性、また、ダイパッドが銅からなり、後程で形成さ
れる厚付け層は主に銅であることから、銅を用いるとよ
い。The reason why the second thin film layer is provided here is that it is difficult to take a lead for electrolytic plating for forming a thickening layer described later in the first thin film layer. The second thin film layer 36 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5.0 μm. 0.
If it is less than 01 μm, it cannot serve as a lead,
This is because if the thickness exceeds 5.0 μm, the lower first thin film layer is shaved more to form a gap during etching, moisture is likely to enter, and the reliability is reduced. Electrical characteristics,
It is preferable to use copper because it is economical and the die pad is made of copper, and the thick layer formed later is mainly copper.

【００１９】第２薄膜層上に、無電解あるいは電解めっ
きにより厚付けさせる。形成される金属の種類としては
ニッケル、銅、金、銀、亜鉛、鉄などがある。電気特
性、経済性、トランジション層としての強度や構造上の
耐性、また、後程で形成されるビルドアップである導体
層は主に銅であることから、銅を用い電解めっきで形成
するのが望ましい。その厚みは１〜２０μｍの範囲で行
うのがよい。１μｍより薄いと、上層のバイアホールと
の接続信頼性が低下し、２０μｍよりも厚くなると、エ
ッチングの際にアンダーカットが起こってしまい、形成
されるトラジション層とバイアホールと界面に隙間が発
生するからである。また、場合によっては、第１薄膜層
上に直接厚付けめっきしても、さらに、多層に積層して
もよい。The second thin film layer is thickly applied by electroless or electrolytic plating. The types of metals that can be formed include nickel, copper, gold, silver, zinc and iron. Electrical properties, economy, strength as a transition layer and structural resistance, and the conductor layer that is the buildup that is formed later is mainly copper, so it is desirable to form it by electrolytic plating using copper. . The thickness is preferably in the range of 1 to 20 μm. If the thickness is less than 1 μm, the connection reliability with the upper via hole decreases, and if the thickness is more than 20 μm, an undercut occurs during etching, and a gap occurs at the interface between the formed transition layer and the via hole. Because it does. In some cases, the first thin film layer may be directly subjected to thick plating, or may be further laminated in multiple layers.

【００２０】その後、エッチングレジストを形成して、
露光、現像してトラジション層以外の部分の金属を露出
させてエッチングを行い、ＩＣチップのダイパッド上に
第１薄膜層、第２薄膜層、厚付け層からなるトラジショ
ン層を形成させる。After that, an etching resist is formed,
Exposure and development are performed to expose the metal in the portion other than the transition layer to perform etching to form a transition layer including a first thin film layer, a second thin film layer, and a thickening layer on the die pad of the IC chip.

【００２１】また、上記トラジション層の製造方法以外
にも、ＩＣチップ及びコア基板の上に形成した金属膜上
にドライフィルムレジストを形成してトラジション層に
該当する部分を除去させて、電解めっきによって厚付け
した後、レジストを剥離してエッチング液によって、同
様にＩＣチップのダイパッド上にトラジション層を形成
させることもできる。In addition to the above-mentioned method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate to remove the portion corresponding to the transition layer, and electrolysis is performed. It is also possible to form the transition layer on the die pad of the IC chip in the same manner by removing the resist after removing the resist after thickening by plating.

【００２２】[0022]

【発明の実施の形態】以下、本発明の実施形態について
図を参照して説明する。先ず、本発明の第１実施形態に
係る多層プリント配線板の構成について、多層プリント
配線板１０の断面を示す図６を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. 6 showing a cross section of the multilayer printed wiring board 10.

【００２３】図６に示すように多層プリント配線板１０
は、ＩＣチップ２０を収容するコア基板３０と、層間樹
脂絶縁層５０、層間樹脂絶縁層１５０とからなる。層間
樹脂絶縁層５０には、バイアホール６０および導体回路
５８が形成され、層間樹脂絶縁層１５０には、バイアホ
ール１６０および導体回路１５８が形成されている。As shown in FIG. 6, the multilayer printed wiring board 10 is shown.
Includes a core substrate 30 that houses the IC chip 20, an interlayer resin insulating layer 50, and an interlayer resin insulating layer 150. A via hole 60 and a conductor circuit 58 are formed in the interlayer resin insulation layer 50, and a via hole 160 and a conductor circuit 158 are formed in the interlayer resin insulation layer 150.

【００２４】ＩＣチップ２０には、パッシベーション膜
２２が被覆され、該パッシベーション膜２２の開口内に
入出力端子を構成するダイパッド２４が配設されてい
る。主として銅から成るダイパッド２４の上には、トラ
ジション層３８が形成されている。該トランジション層
３８は、第１薄膜層３３、第２薄膜層３６、厚付け膜３
７の３層構造からなる。The IC chip 20 is covered with a passivation film 22, and a die pad 24 constituting an input / output terminal is provided in the opening of the passivation film 22. A transition layer 38 is formed on the die pad 24 which is mainly made of copper. The transition layer 38 includes the first thin film layer 33, the second thin film layer 36, and the thickening film 3
7 has a three-layer structure.

【００２５】層間樹脂絶縁層１５０の上には、ソルダー
レジスト層７０が配設されている。ソルダーレジスト層
７０の開口部７１下の導体回路１５８には、図示しない
ドータボード、マザーボード等の外部基板と接続するた
めの半田バンプ７６が設けられている。A solder resist layer 70 is provided on the interlayer resin insulation layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connecting to an external substrate such as a daughter board or a mother board (not shown).

【００２６】本実施形態の多層プリント配線板１０で
は、コア基板３０にＩＣチップ２０を予め内蔵させて、
該ＩＣチップ２０のダイパッド２４にはトラジション層
を３８を配設させている。このため、リード部品や封止
樹脂を用いず、ＩＣチップと多層プリント配線板（パッ
ケージ基板）との電気的接続を取ることができる。ま
た、ＩＣチップ部分にトラジション層３８が形成されて
いることから、ＩＣチップ部分には平坦化されるので、
上層の層間絶縁層５０も平坦化されて、膜厚みも均一に
なる。更に、トラジション層によって、上層のバイアホ
ール６０を形成する際も形状の安定性を保つことができ
る。In the multilayer printed wiring board 10 of this embodiment, the IC chip 20 is previously built in the core substrate 30,
A transition layer 38 is disposed on the die pad 24 of the IC chip 20. Therefore, the IC chip and the multilayer printed wiring board (package substrate) can be electrically connected without using lead components or sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened,
The upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Further, the transition layer can maintain the shape stability even when the upper via hole 60 is formed.

【００２７】更に、４０μｍ前後の径のダイパッド２４
上に６０μｍ径以上のトラジション層３８を介在させる
ことで、６０μｍ径のバイアホールを確実に接続させる
ことができる。また、コア基板上の位置決めマーク（図
示せず）に対して位置合わせしてトランジション層３８
を形成し、更に、該位置決めマークに対して位置合わせ
をしてバイアホール６０を形成するため、トランジショ
ン層３８を介してダイパッド２４をバイアホール６０へ
確実に接続させることができる。Further, the die pad 24 having a diameter of about 40 μm
By interposing the transition layer 38 having a diameter of 60 μm or more on the upper side, a via hole having a diameter of 60 μm can be surely connected. Further, the transition layer 38 is aligned with a positioning mark (not shown) on the core substrate.
Further, since the via hole 60 is formed by aligning with the positioning mark, the die pad 24 can be surely connected to the via hole 60 via the transition layer 38.

【００２８】引き続き、図６を参照して上述した多層プ
リント配線板の製造方法について、図１〜図５を参照し
て説明する。Subsequently, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 6 will be described with reference to FIGS.

【００２９】（１）先ず、ガラスクロス等の心材にエポ
キシ等の樹脂を含浸させたプリプレグを積層した絶縁樹
脂基板（コア基板）３０を出発材料とする（図１（Ａ）
参照）。次に、コア基板３０の片面に、ザグリ加工でＩ
Ｃチップ収容用の凹部３２を形成する（図１（Ｂ）参
照）。ここでは、ザグリ加工により凹部を設けている
が、開口を設けた絶縁樹脂基板と開口を設けない樹脂絶
縁基板とを張り合わせることで、収容部を備えるコア基
板を形成できる。(1) First, an insulating resin substrate (core substrate) 30 in which a core material such as glass cloth is laminated with a prepreg impregnated with a resin such as epoxy is used as a starting material (FIG. 1A).
reference). Next, on one surface of the core substrate 30, I
A recess 32 for accommodating the C chip is formed (see FIG. 1B). Here, the concave portion is provided by the counterbore processing, but the core substrate including the accommodation portion can be formed by bonding the insulating resin substrate having the opening and the resin insulating substrate having no opening.

【００３０】（２）その後、凹部３２に、印刷機を用い
て接着材料３４を塗布する。このとき、塗布以外にも、
ポッティングなどをしてもよい。次に、ＩＣチップ２０
を接着材料３４上に載置する（図１（Ｃ）参照）。(2) After that, the adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides applying
You can also do potting. Next, the IC chip 20
Is placed on the adhesive material 34 (see FIG. 1C).

【００３１】（３）そして、ＩＣチップ２０の上面を押
す、もしくは叩いて凹部３２内に完全に収容させる（図
１（Ｄ）参照）。これにより、コア基板３０を平滑にす
ることができる。(3) Then, the upper surface of the IC chip 20 is pushed or struck to be completely accommodated in the recess 32 (see FIG. 1D). Thereby, the core substrate 30 can be made smooth.

【００３２】（４）その後、ＩＣチップ２０を収容させ
たコア基板３０の全面に蒸着、スパッタリング、無電解
めっきなどを行い、全面に導電性の第１薄膜層３３を形
成させる（図２（Ａ））。その金属としては、スズ、ク
ロム、チタン、ニッケル、亜鉛、コバルト、金、銅など
がよい。特に、銅、ニッケル、クロム、チタンを用いる
ことが、金属との密着性がよく、また、界面への湿分の
侵入を防ぐために望ましい。ダイパッドが銅からなるた
め、銅を用いるのが最適である。厚みとしては、０．０
０１〜２．０μｍの間で形成させるのがよい。特に、
０．１〜１．０μｍが望ましい。クロムの場合には０．
１μｍの厚みが望ましい。(4) After that, vapor deposition, sputtering, electroless plating, etc. are performed on the entire surface of the core substrate 30 accommodating the IC chip 20 to form the conductive first thin film layer 33 (FIG. 2A). )). As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. In particular, it is preferable to use copper, nickel, chromium, and titanium because they have good adhesiveness to a metal and prevent moisture from entering the interface. Copper is best used because the die pad is made of copper. The thickness is 0.0
It is preferable to form it between 01 and 2.0 μm. In particular,
0.1 to 1.0 μm is desirable. 0 for chrome.
A thickness of 1 μm is desirable.

【００３３】第１薄膜層３３により、主として銅から成
るダイパッド２４の被覆を行い、トランジション層とＩ
Ｃチップにダイパッド２４との界面の密着性を高めるこ
とができる。また、これら金属でダイパッド２４を被覆
することで、界面への湿分の侵入を防ぎ、ダイパッドの
信頼性を高めることができる。また、この第１薄膜層３
３によって、リードのない実装方法によりＩＣチップと
の接続を取ることができる。The first thin film layer 33 covers the die pad 24, which is mainly made of copper.
It is possible to improve the adhesiveness of the interface between the C chip and the die pad 24. Further, by covering the die pad 24 with these metals, it is possible to prevent moisture from entering the interface and improve the reliability of the die pad. In addition, the first thin film layer 3
3, the connection with the IC chip can be established by a leadless mounting method.

【００３４】（５）第１薄膜層３３上に、スパッタ、蒸
着、又は、無電解めっきにより、第２薄膜層３６を形成
させる（図２（Ｂ））。その金属としてはニッケル、
銅、金、銀などがある。電気特性、経済性、また、後程
で形成されるビルドアップである導体層は主に銅である
ことから、銅を用いるとよい。なお、第１薄膜層３３上
に、第２薄膜層３６を設けることなく厚付け層を直接形
成することもできる。(5) The second thin film layer 36 is formed on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 2 (B)). The metal is nickel,
There are copper, gold and silver. It is preferable to use copper because electrical characteristics, economy, and a conductor layer which is a buildup formed later is mainly copper. Note that the thickening layer may be directly formed on the first thin film layer 33 without providing the second thin film layer 36.

【００３５】第２薄膜層を設ける理由は、第１薄膜層で
は、後述する厚付け層を形成するための電解めっき用の
リードを取ることができ難いためである。第２薄膜層３
６は、厚付けのリードとして用いられる。その厚みは
０．０１〜５．０μｍの範囲で行うのがよい。０．０１
μｍ未満では、リードとしての役割を果たし得ず、５．
０μｍを越えると、エッチングの際、下層の第１薄膜層
がより多く削れて隙間ができてしまい、湿分が侵入し易
くなり、信頼性が低下するからである。なお、望ましい
第１薄膜層と第２薄膜層との組み合わせは、銅−銅、ク
ロム−銅、クロム−ニッケル、チタン−銅、チタン−ニ
ッケルである。金属との接合性や電気伝達性という点で
他の組み合わせよりも優れる。The reason for providing the second thin film layer is that it is difficult to take a lead for electrolytic plating for forming a thickening layer described later in the first thin film layer. Second thin film layer 3
6 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5.0 μm. 0.01
If it is less than μm, it cannot serve as a lead.
This is because if the thickness exceeds 0 μm, the lower first thin film layer is more abraded and a gap is formed during etching, moisture is likely to enter, and reliability is reduced. The desirable combination of the first thin film layer and the second thin film layer is copper-copper, chromium-copper, chromium-nickel, titanium-copper, titanium-nickel. It is superior to other combinations in terms of bondability with metals and electric conductivity.

【００３６】（６）その後、レジストを塗布し、コア基
板上の図示しない位置決めマークを基準として露光、現
像してＩＣチップのダイパッドの上部に開口を設けるよ
うにメッキレジスト３５を設け、以下の条件で電解めっ
きを施し、電解めっき膜（厚付け膜）３７を設ける（図
２（Ｃ））。(6) After that, a resist is applied, and a plating resist 35 is provided so as to provide an opening above the die pad of the IC chip by exposing and developing with reference to a positioning mark (not shown) on the core substrate. Electroplating is carried out to provide an electrolytic plating film (thickening film) 37 (FIG. 2 (C)).

【００３７】〔電解めっき水溶液〕 硫酸 ２．２４ ｍｏｌ／ｌ 硫酸銅 ０．２６ ｍｏｌ／ｌ 添加剤（アトテックジャパン製、カパラシドＨＬ）１
９．５ ｍｌ／ｌ 〔電解めっき条件〕 電流密度 １Ａ／dm２ 時間 ６５分 温度 ２２±２℃[Electrolytic plating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (manufactured by Atotech Japan, Kaparaside HL) 1
9.5 ml / l [Electrolytic plating conditions] Current density 1 A / dm 2 hours 65 minutes Temperature 22 ± 2 ° C

【００３８】メッキレジスト３５を除去した後、メッキ
レジスト３５下の無電解第２薄膜層３６、第１薄膜層３
３をエッチングで除去することで、ＩＣチップのダイパ
ッド２４上にトラジション層３８を形成する（図２
（Ｄ））。ここでは、メッキレジストによりトラジショ
ン層を形成したが、無電解第２薄膜層３６の上に電解め
っき膜を均一に形成した後、エッチングレジストを形成
して、露光、現像してトラジション層以外の部分の金属
を露出させてエッチングを行い、ＩＣチップのダイパッ
ド上にトラジション層を形成させることも可能である。
電解めっき膜は、ニッケル、銅、金、銀、亜鉛、鉄によ
り形成するのが望ましく、厚みは１〜２０μｍの範囲が
よい。それより厚くなると、エッチングの際にアンダー
カットが起こってしまい、形成されるトラジション層と
バイアホールと界面に隙間が発生することがあるからで
ある。After removing the plating resist 35, the electroless second thin film layer 36 and the first thin film layer 3 under the plating resist 35.
By removing 3 by etching, a transition layer 38 is formed on the die pad 24 of the IC chip (FIG. 2).
(D)). Here, the transition layer is formed by the plating resist. However, after the electrolytic plating film is uniformly formed on the electroless second thin film layer 36, an etching resist is formed and exposed and developed to remove the transition layer other than the transition layer. It is possible to form a transition layer on the die pad of the IC chip by exposing the metal of the above portion and exposing it.
The electrolytic plating film is preferably formed of nickel, copper, gold, silver, zinc, iron, and the thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, undercutting may occur during etching, and a gap may be generated at the interface between the transition layer and the via hole to be formed.

【００３９】（７）次に、基板にエッチング液をスプレ
イで吹きつけ、トラジション層３８の表面をエッチング
することにより粗化面３８αを形成する（図３（Ａ）参
照）。なお、粗化面は、無電解めっき、酸化還元処理に
より形成することもできる。図３（Ａ）中のトランジシ
ョン層３８を拡大して図７（Ａ）に示し、図７（Ａ）の
Ｂ矢視を図７（Ｂ）に示す。トランジション層３８は、
第１薄膜層３３、第２薄膜層３６、厚付け膜３７の３層
構造からなる。図７（Ａ）に示すように、トランジショ
ンは円形に形成されているが、この代わりに、図７
（Ｃ）に示すように楕円形に、図７（Ｄ）に示すように
矩形に、図７（Ｅ）に示すように小判型に形成すること
も可能である。(7) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (see FIG. 3A). The roughened surface can also be formed by electroless plating or redox treatment. The transition layer 38 in FIG. 3 (A) is enlarged and shown in FIG. 7 (A), and the arrow B of FIG. 7 (A) is shown in FIG. 7 (B). The transition layer 38 is
It has a three-layer structure of a first thin film layer 33, a second thin film layer 36, and a thickening film 37. As shown in FIG. 7A, the transition is formed in a circular shape.
It is also possible to form an ellipse as shown in (C), a rectangle as shown in FIG. 7 (D), and an oval shape as shown in FIG. 7 (E).

【００４０】（８）上記工程を経た基板に、厚さ５０μ
ｍの熱硬化型樹脂シートを温度５０〜１５０℃まで昇温
しながら圧力５ｋｇ／ｃｍ2で真空圧着ラミネートし、
層間樹脂絶縁層５０を設ける（図３（Ｂ）参照）。真空
圧着時の真空度は、１０ｍｍＨｇである。(8) The substrate that has undergone the above steps has a thickness of 50 μm.
m thermosetting resin sheet is vacuum pressure-bonded and laminated at a pressure of 5 kg / cm 2 while raising the temperature to 50 to 150 ° C.
An interlayer resin insulating layer 50 is provided (see FIG. 3B). The degree of vacuum during vacuum pressure bonding is 10 mmHg.

【００４１】（９）次に、コア基板上の図示しない位置
決めマークを基準として位置合わせを行い、波長１０．
４μｍのＣＯ2ガスレーザにて、ビーム径５ｍｍ、トッ
プハットモード、パルス幅５．０μ秒、マスクの穴径
０．５ｍｍ、１ショットの条件で、層間樹脂絶縁層５０
に直径８０μｍのバイアホール用開口４８を設ける（図
３（Ｃ）参照）。クロム酸を用いて、開口４８内の樹脂
残りを除去する。ダイパッド２４上に銅製のトラジショ
ン層３８を設けることで、ダイパッド２４上の樹脂残り
を防ぐことができ、これにより、ダイパッド２４と後述
するバイアホール６０との接続性や信頼性を向上させ
る。更に、４０μｍ径前後のダイパッド２４上に６０μ
ｍ以上の径のトラジション層３８を介在させることで、
６０μｍ径のバイアホール用開口４８を確実に接続させ
ることができる。なお、ここでは、過マンガン酸を用い
て樹脂残さを除去したが、酸素プラズマを用いてデスミ
ア処理を行うことも可能である。(9) Next, alignment is performed with reference to a positioning mark (not shown) on the core substrate, and the wavelength of 10.
With a 4 μm CO 2 gas laser, the interlayer resin insulation layer 50 was formed under the conditions of beam diameter 5 mm, top hat mode, pulse width 5.0 μsec, mask hole diameter 0.5 mm, and one shot.
An opening 48 for a via hole having a diameter of 80 μm is provided in (FIG. 3 (C)). Chromic acid is used to remove the resin residue in the openings 48. By providing the copper transition layer 38 on the die pad 24, it is possible to prevent resin residue on the die pad 24, thereby improving the connectivity and reliability between the die pad 24 and a via hole 60 described later. Furthermore, 60μ on the die pad 24 with a diameter of around 40μm
By interposing the transition layer 38 having a diameter of m or more,
The via hole opening 48 having a diameter of 60 μm can be reliably connected. Although the resin residue was removed using permanganic acid here, desmear treatment can also be performed using oxygen plasma.

【００４２】（１０）次に、クロム酸、過マンガン酸塩
などの酸化剤等に浸漬させることによって、層間樹脂絶
縁層５０の粗化面５０αを設ける（図３（Ｄ）参照）。
該粗化面５０αは、０．１〜５μｍの範囲で形成される
ことがよい。その一例として、過マンガン酸ナトリウム
溶液５０ｇ／ｌ、温度６０℃中に５〜２５分間浸漬させ
ることによって、２〜３μｍの粗化面５０αを設ける。
上記以外には、日本真空技術株式会社製のＳＶ−４５４
０を用いてプラズマ処理を行い、層間樹脂絶縁層５０の
表面に粗化面５０αを形成することもできる。この際、
不活性ガスとしてはアルゴンガスを使用し、電力２００
Ｗ、ガス圧０．６Ｐａ、温度７０℃の条件で、２分間プ
ラズマ処理を実施する。(10) Next, the roughened surface 50α of the interlayer resin insulation layer 50 is provided by immersing it in an oxidizing agent such as chromic acid or permanganate (see FIG. 3D).
The roughened surface 50α is preferably formed in the range of 0.1 to 5 μm. As an example thereof, a roughened surface 50α of 2-3 μm is provided by immersing in a sodium permanganate solution of 50 g / l and a temperature of 60 ° C. for 5 to 25 minutes.
Other than the above, SV-454 manufactured by Nippon Vacuum Technology Co., Ltd.
It is also possible to perform a plasma treatment using 0 to form a roughened surface 50α on the surface of the interlayer resin insulation layer 50. On this occasion,
Argon gas is used as the inert gas, and the power is 200
Plasma treatment is performed for 2 minutes under the conditions of W, gas pressure of 0.6 Pa, and temperature of 70 ° C.

【００４３】（１１）粗化面５０αが形成された層間樹
脂絶縁層５０上に、金属層５２を設ける（図４（Ａ）参
照）。金属層５２は、無電解めっきによって形成させ
る。予め層間樹脂絶縁層５０の表層にパラジウムなどの
触媒を付与させて、無電解めっき液に５〜６０分間浸漬
させることにより、０．１〜５μｍの範囲でめっき膜で
ある金属層５２を設ける。その一例として、 〔無電解めっき水溶液〕 ＮｉＳＯ4 ０．００３ ｍｏｌ／ｌ 酒石酸 ０．２００ ｍｏｌ／ｌ 硫酸銅 ０．０３０ ｍｏｌ／ｌ ＨＣＨＯ ０．０５０ ｍｏｌ／ｌ ＮａＯＨ ０．１００ ｍｏｌ／ｌ α、α′−ビピルジル １００ ｍｇ／ｌ ポリエチレングリコール（ＰＥＧ） ０．１０ ｇ／ｌ ３４℃の液温度で４０分間浸漬させた。上記以外でも上
述したプラズマ処理と同じ装置を用い、内部のアルゴン
ガスを交換した後、Ｎｉ及びＣｕをターゲットにしたス
パッタリングを、気圧０．６Ｐａ、温度８０℃、電力２
００Ｗ、時間５分間の条件で行い、Ｎｉ／Ｃｕ金属層５
２を層間樹脂絶縁層５０の表面に形成することもでき
る。このとき、形成されるＮｉ／Ｃｕ金属層５２の厚さ
は０．２μｍである。(11) A metal layer 52 is provided on the interlayer resin insulation layer 50 on which the roughened surface 50α is formed (see FIG. 4A). The metal layer 52 is formed by electroless plating. A metal layer 52, which is a plating film, is provided in a range of 0.1 to 5 μm by previously applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 50 and immersing the catalyst in an electroless plating solution for 5 to 60 minutes. As an example thereof, [electroless plating aqueous solution] NiSO 4 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α ′ -Bipyrudil 100 mg / l Polyethylene glycol (PEG) 0.10 g / l Immersed at a liquid temperature of 34 ° C. for 40 minutes. Other than the above, the same apparatus as the plasma processing described above is used, and after the internal argon gas is exchanged, sputtering with Ni and Cu as targets is performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 2
Ni / Cu metal layer 5
2 may be formed on the surface of the interlayer resin insulation layer 50. At this time, the thickness of the Ni / Cu metal layer 52 formed is 0.2 μm.

【００４４】（１２）上記処理を終えた基板３０に、市
販の感光性ドライフィルムを貼り付け、クロムガラスマ
スクを載置して、４０ｍＪ／ｃｍ2で露光した後、０．
８％炭酸ナトリウムで現像処理し、厚さ２５μｍのめっ
きレジスト５４を設ける。次に、以下の条件で電解めっ
きを施して、厚さ１８μｍの電解めっき膜５６を形成す
る（図４（Ｂ）参照）。なお、電解めっき水溶液中の添
加剤は、アトテックジャパン社製のカパラシドＨＬであ
る。(12) A commercially available photosensitive dry film is attached to the substrate 30 which has been subjected to the above treatment, a chrome glass mask is placed on the substrate 30, and the substrate is exposed at 40 mJ / cm 2 .
Development processing is performed with 8% sodium carbonate to provide a plating resist 54 having a thickness of 25 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plated film 56 having a thickness of 18 μm (see FIG. 4B). The additive in the electrolytic plating solution is Caparaside HL manufactured by Atotech Japan.

【００４５】〔電解めっき水溶液〕 硫酸 ２．２４ ｍｏｌ／ｌ 硫酸銅 ０．２６ ｍｏｌ／ｌ 添加剤（アトテックジャパン製、カパラシドＨＬ）１
９．５ ｍｌ／ｌ 〔電解めっき条件〕 電流密度 １Ａ／dm２ 時間 ６５分 温度 ２２±２℃[Electrolytic plating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (manufactured by Atotech Japan, Kaparaside HL) 1
9.5 ml / l [Electrolytic plating conditions] Current density 1 A / dm 2 hours 65 minutes Temperature 22 ± 2 ° C

【００４６】（１３）めっきレジスト５４を５％ＮａＯ
Ｈで剥離除去した後、そのめっきレジスト下のＮｉ−Ｃ
ｕ合金層５２を硝酸および硫酸と過酸化水素の混合液を
用いるエッチングにて溶解除去し、Ｎｉ−Ｃｕ合金層５
２と電解めっき膜５６からなる厚さ１６μｍの導体回路
５８及びバイアホール６０を形成し、第二銅錯体と有機
酸とを含有するエッチング液によって、粗化面５８α、
６０αを形成する（図４（Ｃ）参照）。(13) The plating resist 54 is 5% NaO
After peeling off with H, Ni-C under the plating resist
The u alloy layer 52 is dissolved and removed by etching using a mixed solution of nitric acid and sulfuric acid and hydrogen peroxide, and the Ni—Cu alloy layer 5 is formed.
A conductor circuit 58 and a via hole 60 having a thickness of 16 μm, which are composed of 2 and the electrolytic plating film 56, and are roughened by an etching solution containing a cupric complex and an organic acid.
60α is formed (see FIG. 4C).

【００４７】（１４）次いで、上記（９）〜（１３）の
工程を、繰り返すことにより、さらに上層の層間樹脂絶
縁層１５０及び導体回路１５８（バイアホール１６０を
含む）を形成する（図５（Ａ）参照）。(14) Next, the above steps (9) to (13) are repeated to form an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including the via hole 160) (FIG. 5 ( See A)).

【００４８】（１５）次に、ジエチレングリコールジメ
チルエーテル（ＤＭＤＧ）に６０重量％の濃度になるよ
うに溶解させた、クレゾールノボラック型エポキシ樹脂
（日本化薬社製）のエポキシ基５０％をアクリル化した
感光性付与のオリゴマー（分子量４０００）４６．６７
重量部、メチルエチルケトンに溶解させた８０重量％の
ビスフェノールＡ型エポキシ樹脂（油化シェル社製、商
品名：エピコート１００１）１５重量部、イミダゾール
硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）
１．６重量部、感光性モノマーである多官能アクリルモ
ノマー（共栄化学社製、商品名：Ｒ６０４）３重量部、
同じく多価アクリルモノマー（共栄化学社製、商品名：
ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ
社製、商品名：Ｓ−６５）０．７１重量部を容器にと
り、攪拌、混合して混合組成物を調整し、この混合組成
物に対して光重量開始剤としてベンゾフェノン（関東化
学社製）２．０重量部、光増感剤としてのミヒラーケト
ン（関東化学社製）０．２重量部を加えて、粘度を２５
℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物
（有機樹脂絶縁材料）を得る。なお、粘度測定は、Ｂ型
粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの
場合はローターNo.４、６ｒｐｍの場合はローターNo.３
によった。(15) Next, a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight, and acrylated with 50% of epoxy groups. Oligomer (molecular weight 4000) 46.67
15 parts by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., trade name: Epicoat 1001) of 80% by weight dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer which is a photosensitive monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604)
Similarly, polyvalent acrylic monomer (Kyoei Chemical Co., Ltd., trade name:
DPE6A) 1.5 parts by weight, dispersion type antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.71 parts by weight are put in a container, stirred and mixed to prepare a mixed composition, and this mixed composition To the composition, 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photogravimetric initiator and 0.2 part by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at 0 ° C. is obtained. The viscosity was measured with a B-type viscometer (DVL-B type manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm, rotor No. 4, and at 6 rpm, rotor No. 3.
According to

【００４９】（１６）次に、基板３０に、上記ソルダー
レジスト組成物を２０μｍの厚さで塗布し、７０℃で２
０分間、７０℃で３０分間の条件で乾燥処理を行った
後、ソルダーレジストレジスト開口部のパターンが描画
された厚さ５ｍｍのフォトマスクをソルダーレジスト層
７０に密着させて１０００ｍＪ／ｃｍ2の紫外線で露光
し、ＤＭＴＧ溶液で現像処理し、ランド径６２０μｍ、
開口径４６０μｍの開口７１を形成する（図５（Ｂ）参
照）。(16) Next, the solder resist composition is applied to the substrate 30 to a thickness of 20 μm, and the solder resist composition is applied at 70 ° C. for 2 hours.
After performing a drying process for 0 minutes at 70 ° C. for 30 minutes, a photomask having a thickness of 5 mm on which a pattern of a solder resist resist opening is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm 2 is applied. Exposure, and development processing with DMTG solution, land diameter 620 μm,
An opening 71 having an opening diameter of 460 μm is formed (see FIG. 5B).

【００５０】（１７）次に、ソルダーレジスト層（有機
樹脂絶縁層）７０を形成した基板を、塩化ニッケル
（２．３×１０-1ｍｏｌ／ｌ）、次亞リン酸ナトリウム
（２．８×１０-1ｍｏｌ／ｌ）、クエン酸ナトリウム
（１．６×１０-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無
電解ニッケルめっき液に２０分間浸漬して、開口部７１
に厚さ５μｍのニッケルめっき層７２を形成する。さら
に、その基板を、シアン化金カリウム（７．６×１０-3
ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０-1ｍｏ
ｌ／ｌ）、クエン酸ナトリウム（１．２×１０-1ｍｏｌ
／ｌ）、次亜リン酸ナトリウム（１．７×１０-1ｍｏｌ
／ｌ）を含む無電解めっき液に８０℃の条件で７．５分
間浸漬して、ニッケルめっき層７２上に厚さ０．０３μ
ｍの金めっき層７４を形成することで、導体回路１５８
に半田パッド７５を形成する（図５（Ｃ）参照）。(17) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is treated with nickel chloride (2.3 × 10 −1 mol / l) and sodium hypophosphate (2.8 ×). 10 −1 mol / l) and sodium citrate (1.6 × 10 −1 mol / l) for 20 minutes in an electroless nickel plating solution of pH = 4.5 to form the opening 71.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate is treated with potassium gold cyanide (7.6 × 10 −3
mol / l), ammonium chloride (1.9 × 10 -1 mo)
l / l), sodium citrate (1.2 × 10 −1 mol
/ L), sodium hypophosphite (1.7 × 10 −1 mol
/ L) in an electroless plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm thick layer on the nickel plating layer 72.
By forming the gold plating layer 74 of m, the conductor circuit 158
A solder pad 75 is formed on the substrate (see FIG. 5C).

【００５１】（１８）この後、ソルダーレジスト層７０
の開口部７１に、はんだペーストを印刷して、２００℃
でリフローすることにより、半田バンプ７６を形成す
る。これにより、ＩＣチップ２０を内蔵し、半田バンプ
７６を有する多層プリント配線板１０を得ることができ
る（図６参照）。(18) Thereafter, the solder resist layer 70
Solder paste is printed on the opening 71 of the
Then, the solder bumps 76 are formed by reflowing. As a result, the multilayer printed wiring board 10 having the IC chip 20 built therein and having the solder bumps 76 can be obtained (see FIG. 6).

【００５２】図１３（Ａ）は、第１実施形態に係る多層
プリント配線板１０の平面図を示している。第１実施形
態の多層プリント配線板１０の表面には、格子状に半田
バンプ（ボールグリットアレー）７６が基板全面に配設
されている。第１実施形態では、ＩＣチップ２０上の領
域Ｒ１にも半田バンプ７６を形成することで、ＩＣチッ
プ２０からの配線長さを短縮することができる。なお、
半田バンプ７６は、図１３（Ｂ）に示すように基板全面
に千鳥状に形成されてもよい。FIG. 13A shows a plan view of the multilayer printed wiring board 10 according to the first embodiment. On the surface of the multilayer printed wiring board 10 of the first embodiment, solder bumps (ball grit array) 76 are arranged in a grid pattern over the entire surface of the substrate. In the first embodiment, by forming the solder bumps 76 also in the region R1 on the IC chip 20, the wiring length from the IC chip 20 can be shortened. In addition,
The solder bumps 76 may be formed in a zigzag pattern on the entire surface of the substrate as shown in FIG.

【００５３】上述した実施形態では、層間樹脂絶縁層５
０、１５０に熱硬化型シクロオレフィン系樹脂シート、
エポキシ系樹脂シートを用いることができる。この熱硬
化型樹脂シートには、難溶性樹脂、可溶性粒子、硬化
剤、その他の成分が含有されている。それぞれについて
以下に説明する。In the above-described embodiment, the interlayer resin insulation layer 5
0 to 150 thermosetting cycloolefin resin sheet,
An epoxy resin sheet can be used. The thermosetting resin sheet contains a poorly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.

【００５４】本発明の製造方法において使用し得る熱硬
化型樹脂シートは、酸または酸化剤に可溶性の粒子（以
下、可溶性粒子という）が酸または酸化剤に難溶性の樹
脂（以下、難溶性樹脂という）中に分散したものであ
る。なお、本発明で使用する「難溶性」「可溶性」とい
う語は、同一の酸または酸化剤からなる溶液に同一時間
浸漬した場合に、相対的に溶解速度の早いものを便宜上
「可溶性」と呼び、相対的に溶解速度の遅いものを便宜
上「難溶性」と呼ぶ。The thermosetting resin sheet which can be used in the production method of the present invention is a resin in which particles soluble in an acid or an oxidant (hereinafter referred to as soluble particles) are hardly soluble in an acid or an oxidant (hereinafter, a sparingly soluble resin). That is) dispersed in. The terms "poorly soluble" and "soluble" used in the present invention are referred to as "soluble" for the sake of convenience, those having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time. For convenience, those having a relatively slow dissolution rate are called "poorly soluble".

【００５５】上記可溶性粒子としては、例えば、酸また
は酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒
子）、酸または酸化剤に可溶性の無機粒子（以下、可溶
性無機粒子）、酸または酸化剤に可溶性の金属粒子（以
下、可溶性金属粒子）等が挙げられる。これらの可溶性
粒子は、単独で用いても良いし、２種以上併用してもよ
い。Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), acid or an oxidizing agent. Examples thereof include soluble metal particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more kinds.

【００５６】上記可溶性粒子の形状は特に限定されず、
球状、破砕状等が挙げられる。また、上記可溶性粒子の
形状は、一様な形状であることが望ましい。均一な粗さ
の凹凸を有する粗化面を形成することができるからであ
る。The shape of the soluble particles is not particularly limited,
Examples thereof include spherical shapes and crushed shapes. Further, it is desirable that the soluble particles have a uniform shape. This is because it is possible to form a roughened surface having unevenness with a uniform roughness.

【００５７】上記可溶性粒子の平均粒径としては、０．
１〜１０μｍが望ましい。この粒径の範囲であれば、２
種類以上の異なる粒径のものを含有してもよい。すなわ
ち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均
粒径が１〜３μｍの可溶性粒子とを含有する等である。
これにより、より複雑な粗化面を形成することができ、
導体回路との密着性にも優れる。なお、本発明におい
て、可溶性粒子の粒径とは、可溶性粒子の一番長い部分
の長さである。The average particle size of the soluble particles is 0.
1-10 micrometers is desirable. Within this particle size range, 2
You may contain the thing of different particle diameters more than a kind. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
This makes it possible to form a more complicated roughened surface,
Excellent adhesion with conductor circuits. In addition, in this invention, the particle diameter of a soluble particle is the length of the longest part of a soluble particle.

【００５８】上記可溶性樹脂粒子としては、熱硬化性樹
脂、熱可塑性樹脂等からなるものが挙げられ、酸あるい
は酸化剤からなる溶液に浸漬した場合に、上記難溶性樹
脂よりも溶解速度が速いものであれば特に限定されな
い。上記可溶性樹脂粒子の具体例としては、例えば、エ
ポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフ
ェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等から
なるものが挙げられ、これらの樹脂の一種からなるもの
であってもよいし、２種以上の樹脂の混合物からなるも
のであってもよい。Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin and the like, and those having a faster dissolution rate than the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. It is not particularly limited as long as it is. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be one of these resins. However, it may be composed of a mixture of two or more kinds of resins.

【００５９】また、上記可溶性樹脂粒子としては、ゴム
からなる樹脂粒子を用いることもできる。上記ゴムとし
ては、例えば、ポリブタジエンゴム、エポキシ変性、ウ
レタン変性、（メタ）アクリロニトリル変性等の各種変
性ポリブタジエンゴム、カルボキシル基を含有した（メ
タ）アクリロニトリル・ブタジエンゴム等が挙げられ
る。これらのゴムを使用することにより、可溶性樹脂粒
子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸
を用いて可溶性樹脂粒子を溶解する際には、強酸以外の
酸でも溶解することができ、酸化剤を用いて可溶性樹脂
粒子を溶解する際には、比較的酸化力の弱い過マンガン
酸塩でも溶解することができる。また、クロム酸を用い
た場合でも、低濃度で溶解することができる。そのた
め、酸や酸化剤が樹脂表面に残留することがなく、後述
するように、粗化面形成後、塩化パラジウム等の触媒を
付与する際に、触媒が付与されなたかったり、触媒が酸
化されたりすることがない。As the soluble resin particles, resin particles made of rubber may be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in the acid or the oxidizing agent. That is, when dissolving soluble resin particles using an acid, it is possible to dissolve an acid other than a strong acid, and when dissolving soluble resin particles using an oxidizing agent, permanganese, which has a relatively weak oxidizing power, is dissolved. The acid salt can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid and the oxidizing agent do not remain on the resin surface, and as described later, when the catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.

【００６０】上記可溶性無機粒子としては、例えば、ア
ルミニウム化合物、カルシウム化合物、カリウム化合
物、マグネシウム化合物およびケイ素化合物からなる群
より選択される少なくとも一種からなる粒子等が挙げら
れる。Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

【００６１】上記アルミニウム化合物としては、例え
ば、アルミナ、水酸化アルミニウム等が挙げられ、上記
カルシウム化合物としては、例えば、炭酸カルシウム、
水酸化カルシウム等が挙げられ、上記カリウム化合物と
しては、炭酸カリウム等が挙げられ、上記マグネシウム
化合物としては、マグネシア、ドロマイト、塩基性炭酸
マグネシウム等が挙げられ、上記ケイ素化合物として
は、シリカ、ゼオライト等が挙げられる。これらは単独
で用いても良いし、２種以上併用してもよい。Examples of the aluminum compound include alumina and aluminum hydroxide, and examples of the calcium compound include calcium carbonate and
Examples include calcium hydroxide and the like, examples of the potassium compound include potassium carbonate and the like, examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

【００６２】上記可溶性金属粒子としては、例えば、
銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、
マグネシウム、カルシウムおよびケイ素からなる群より
選択される少なくとも一種からなる粒子等が挙げられ
る。また、これらの可溶性金属粒子は、絶縁性を確保す
るために、表層が樹脂等により被覆されていてもよい。Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples thereof include particles made of at least one selected from the group consisting of magnesium, calcium and silicon. The surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.

【００６３】上記可溶性粒子を、２種以上混合して用い
る場合、混合する２種の可溶性粒子の組み合わせとして
は、樹脂粒子と無機粒子との組み合わせが望ましい。両
者とも導電性が低くいため樹脂フィルムの絶縁性を確保
することができるとともに、難溶性樹脂との間で熱膨張
の調整が図りやすく、樹脂フィルムからなる層間樹脂絶
縁層にクラックが発生せず、層間樹脂絶縁層と導体回路
との間で剥離が発生しないからである。When two or more kinds of the above-mentioned soluble particles are mixed and used, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both can ensure the insulation of the resin film because the conductivity is low, it is easy to adjust the thermal expansion with the poorly soluble resin, cracks do not occur in the interlayer resin insulation layer made of the resin film, This is because peeling does not occur between the interlayer resin insulation layer and the conductor circuit.

【００６４】上記難溶性樹脂としては、層間樹脂絶縁層
に酸または酸化剤を用いて粗化面を形成する際に、粗化
面の形状を保持できるものであれば特に限定されず、例
えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等
が挙げられる。また、これらの樹脂に感光性を付与した
感光性樹脂であってもよい。感光性樹脂を用いることに
より、層間樹脂絶縁層に露光、現像処理を用いてバイア
ホール用開口を形成することできる。これらのなかで
は、熱硬化性樹脂を含有しているものが望ましい。それ
により、めっき液あるいは種々の加熱処理によっても粗
化面の形状を保持することができるからである。The sparingly soluble resin is not particularly limited as long as it can retain the shape of the roughened surface when the roughened surface is formed in the interlayer resin insulation layer by using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, it may be a photosensitive resin obtained by imparting photosensitivity to these resins. By using the photosensitive resin, the via hole opening can be formed in the interlayer resin insulation layer by exposure and development. Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.

【００６５】上記難溶性樹脂の具体例としては、例え
ば、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、
ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン
樹脂、フッ素樹脂等が挙げられる。これらの樹脂は単独
で用いてもよいし、２種以上を併用してもよい。熱硬化
性樹脂、熱可塑性樹脂、それらの複合体であってもよ
い。さらには、１分子中に、２個以上のエポキシ基を有
するエポキシ樹脂がより望ましい。前述の粗化面を形成
することができるばかりでなく、耐熱性等にも優れてる
ため、ヒートサイクル条件下においても、金属層に応力
の集中が発生せず、金属層の剥離などが起きにくいから
である。Specific examples of the sparingly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include polyimide resin, polyphenylene resin, polyolefin resin, and fluororesin. These resins may be used alone or in combination of two or more. It may be a thermosetting resin, a thermoplastic resin, or a composite thereof. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the roughened surface described above be formed, but also because it has excellent heat resistance, stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer does not easily occur. Because.

【００６６】上記エポキシ樹脂としては、例えば、クレ
ゾールノボラック型エポキシ樹脂、ビスフェノールＡ型
エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェ
ノールノボラック型エポキシ樹脂、アルキルフェノール
ノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ
樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエ
ン型エポキシ樹脂、フェノール類とフェノール性水酸基
を有する芳香族アルデヒドとの縮合物のエポキシ化物、
トリグリシジルイソシアヌレート、脂環式エポキシ樹脂
等が挙げられる。これらは、単独で用いてもよく、２種
以上を併用してもよい。それにより、耐熱性等に優れる
ものとなる。Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of a condensation product of a phenol and an aromatic aldehyde having a phenolic hydroxyl group,
Examples thereof include triglycidyl isocyanurate and alicyclic epoxy resin. These may be used alone or in combination of two or more. As a result, the heat resistance is excellent.

【００６７】本発明で用いる樹脂フィルムにおいて、上
記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散さ
れていることが望ましい。均一な粗さの凹凸を有する粗
化面を形成することができ、樹脂フィルムにバイアホー
ルやスルーホールを形成しても、その上に形成する導体
回路の金属層の密着性を確保することができるからであ
る。また、粗化面を形成する表層部だけに可溶性粒子を
含有する樹脂フィルムを用いてもよい。それによって、
樹脂フィルムの表層部以外は酸または酸化剤にさらされ
ることがないため、層間樹脂絶縁層を介した導体回路間
の絶縁性が確実に保たれる。In the resin film used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the sparingly soluble resin. It is possible to form a roughened surface having unevenness with a uniform roughness, and even if a via hole or a through hole is formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Moreover, you may use the resin film which contains a soluble particle only in the surface layer part which forms a roughened surface. Thereby,
Since the parts other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is surely maintained.

【００６８】上記樹脂フィルムにおいて、難溶性樹脂中
に分散している可溶性粒子の配合量は、樹脂フィルムに
対して、３〜４０重量％が望ましい。可溶性粒子の配合
量が３重量％未満では、所望の凹凸を有する粗化面を形
成することができない場合があり、４０重量％を超える
と、酸または酸化剤を用いて可溶性粒子を溶解した際
に、樹脂フィルムの深部まで溶解してしまい、樹脂フィ
ルムからなる層間樹脂絶縁層を介した導体回路間の絶縁
性を維持できず、短絡の原因となる場合がある。In the above resin film, the compounding amount of the soluble particles dispersed in the sparingly soluble resin is preferably 3 to 40% by weight based on the resin film. If the content of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities, and if it exceeds 40% by weight, when the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film may be dissolved to a deep portion, and the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin film cannot be maintained, which may cause a short circuit.

【００６９】上記樹脂フィルムは、上記可溶性粒子、上
記難溶性樹脂以外に、硬化剤、その他の成分等を含有し
ていることが望ましい。上記硬化剤としては、例えば、
イミダゾール系硬化剤、アミン系硬化剤、グアニジン系
硬化剤、これらの硬化剤のエポキシアダクトやこれらの
硬化剤をマイクロカプセル化したもの、トリフェニルホ
スフィン、テトラフェニルホスフォニウム・テトラフェ
ニルボレート等の有機ホスフィン系化合物等が挙げられ
る。The resin film preferably contains a curing agent and other components in addition to the soluble particles and the sparingly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents, microencapsulations of these curing agents, organics such as triphenylphosphine, tetraphenylphosphonium / tetraphenylborate, etc. Examples thereof include phosphine compounds.

【００７０】上記硬化剤の含有量は、樹脂フィルムに対
して０．０５〜１０重量％であることが望ましい。０．
０５重量％未満では、樹脂フィルムの硬化が不十分であ
るため、酸や酸化剤が樹脂フィルムに侵入する度合いが
大きくなり、樹脂フィルムの絶縁性が損なわれることが
ある。一方、１０重量％を超えると、過剰な硬化剤成分
が樹脂の組成を変性させることがあり、信頼性の低下を
招いたりしてしまうことがある。The content of the above curing agent is preferably 0.05 to 10% by weight based on the resin film. 0.
If it is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidant into the resin film becomes large, and the insulating property of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive amount of the curing agent component may modify the composition of the resin, which may lead to a decrease in reliability.

【００７１】上記その他の成分としては、例えば、粗化
面の形成に影響しない無機化合物あるいは樹脂等のフィ
ラーが挙げられる。上記無機化合物としては、例えば、
シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂
としては、例えば、ポリイミド樹脂、ポリアクリル樹
脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラ
ニン樹脂、オレフィン系樹脂等が挙げられる。これらの
フィラーを含有させることによって、熱膨脹係数の整合
や耐熱性、耐薬品性の向上などを図り多層プリント配線
板の性能を向上させることができる。Examples of the above-mentioned other components include inorganic compounds or fillers such as resins that do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, the performance of the multilayer printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance.

【００７２】また、上記樹脂フィルムは、溶剤を含有し
ていてもよい。上記溶剤としては、例えば、アセトン、
メチルエチルケトン、シクロヘキサノン等のケトン類、
酢酸エチル、酢酸ブチル、セロソルブアセテートやトル
エン、キシレン等の芳香族炭化水素等が挙げられる。こ
れらは単独で用いてもよいし、２種類以上併用してもよ
い。ただし、これらの層間樹脂絶縁層は、３５０℃以上
の温度を加えると溶解、炭化をしてしまう。The resin film may contain a solvent. Examples of the solvent include acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, xylene and the like can be mentioned. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are melted and carbonized when a temperature of 350 ° C. or higher is applied.

【００７３】上記樹脂フィルムを張り付けた後、レーザ
で開口させて、層間樹脂絶縁層にバイアホールを開口さ
せる。その後、酸あるいは酸化剤に浸漬させて、層間樹
脂絶縁層に粗化層を形成する。酸としては、硫酸、リン
酸、塩酸、蟻酸などの強酸を用いることができ、酸化剤
としてはクロム酸、クロム硫酸、過マンガン塩酸などを
用いることができる。それにより、可溶性粒子を溶解あ
るいは脱落させることによって層間樹脂絶縁層の表面に
粗化層を形成させる。その粗化層の形成された層間樹脂
絶縁層に、Ｐｂなどの触媒を付与させた後、無電解めっ
きを施す。無電解めっき膜上にレジストを施して露光、
現像を経てめっきレジストの非形成部を形成させる。該
非形成部に電解めっきを施してレジストを剥離、エッチ
ングによって層間樹脂絶縁層上の無電解めっき膜を除去
してバイアホールと導体回路を形成させた。After the resin film is attached, it is opened by a laser to form a via hole in the interlayer resin insulation layer. Then, it is immersed in an acid or an oxidizing agent to form a roughening layer on the interlayer resin insulation layer. A strong acid such as sulfuric acid, phosphoric acid, hydrochloric acid, or formic acid can be used as the acid, and chromic acid, chromic sulfuric acid, permanganate hydrochloric acid, or the like can be used as the oxidizing agent. Thus, the soluble particles are dissolved or fallen off to form a roughened layer on the surface of the interlayer resin insulation layer. After applying a catalyst such as Pb to the interlayer resin insulation layer on which the roughened layer is formed, electroless plating is performed. Exposure by applying a resist on the electroless plating film,
A non-formed portion of the plating resist is formed through development. The non-formed portion was subjected to electrolytic plating to remove the resist, and the electroless plated film on the interlayer resin insulation layer was removed by etching to form a via hole and a conductor circuit.

【００７４】引き続き、本発明の第１実施形態の改変例
に係る多層プリント配線板について、図８を参照して説
明する。上述した第１実施形態では、ＢＧＡを配設した
場合で説明した。改変例では、第１実施形態とほぼ同様
であるが、図８に示すように導電性接続ピン９６を介し
て接続を取るＰＧＡ方式に構成されている。Subsequently, a multilayer printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. In the above-described first embodiment, the case where the BGA is provided has been described. The modified example is almost the same as that of the first embodiment, but is configured by the PGA method in which the connection is made through the conductive connection pin 96 as shown in FIG.

【００７５】次に、本発明の第２実施形態に係る多層プ
リント配線板について、図９を参照して説明する。上述
した第１実施形態では、コア基板３０にザグリで設けた
凹部３２にＩＣチップを収容した。これに対して、第２
実施形態では、コア基板３０に形成した通孔３２にＩＣ
チップ２０を収容してある。この第２実施形態では、Ｉ
Ｃチップ２０の裏面側にヒートシンクを直接取り付ける
ことができるため、ＩＣチップ２０を効率的に冷却でき
る利点がある。Next, a multilayer printed wiring board according to the second embodiment of the present invention will be described with reference to FIG. In the above-described first embodiment, the IC chip is housed in the recess 32 provided in the core substrate 30 by the counterbore. In contrast, the second
In the embodiment, the IC is formed in the through hole 32 formed in the core substrate 30.
It contains a chip 20. In this second embodiment, I
Since the heat sink can be directly attached to the back surface side of the C chip 20, there is an advantage that the IC chip 20 can be efficiently cooled.

【００７６】次に、本発明の第３実施形態に係る多層プ
リント配線板について、図１０を参照して説明する。上
述した第１実施形態では、多層プリント配線板内にＩＣ
チップを収容した。これに対して、第３実施形態では、
多層プリント配線板内にＩＣチップ２０を収容すると共
に、表面にＩＣチップ１２０を載置してある。内蔵のＩ
Ｃチップ２０としては、発熱量の比較的小さいキャシュ
メモリが用いられ、表面のＩＣチップ１２０としては、
演算用のＣＰＵが載置されている。Next, a multilayer printed wiring board according to the third embodiment of the present invention will be described with reference to FIG. In the above-described first embodiment, the IC is installed in the multilayer printed wiring board.
Housed chips. On the other hand, in the third embodiment,
The IC chip 20 is accommodated in the multilayer printed wiring board, and the IC chip 120 is placed on the surface. Built-in I
A cache memory that generates a relatively small amount of heat is used as the C chip 20, and the IC chip 120 on the front surface is
A calculation CPU is mounted.

【００７７】ＩＣチップ２０のダイパッド２４と、ＩＣ
チップ１２０のダイパッド１２４とは、トラジション層
３８−バイアホール６０−導体回路５８−バイアホール
１６０−導体回路１５８−半田バンプ７６Ｕを介して接
続されている。一方、ＩＣチップ１２０のダイパッド１
２４と、ドータボード９０のパッド９２とは、半田バン
プ７６Ｕ−導体回路１５８−バイアホール１６０−導体
回路５８−バイアホール６０−スルーホール１３６−バ
イアホール６０−導体回路５８−バイアホール１６０−
導体回路１５８−半田バンプ７６Ｕを介して接続されて
いる。The die pad 24 of the IC chip 20 and the IC
The die pad 124 of the chip 120 is connected via the transition layer 38-via hole 60-conductor circuit 58-via hole 160-conductor circuit 158-solder bump 76U. On the other hand, the die pad 1 of the IC chip 120
24 and the pad 92 of the daughter board 90 include a solder bump 76U, a conductor circuit 158, a via hole 160, a conductor circuit 58, a via hole 60, a through hole 136, a via hole 60, a conductor circuit 58, and a via hole 160.
The conductor circuit 158 and the solder bump 76U are connected to each other.

【００７８】第３実施形態では、歩留まりの低いキャシ
ュメモリ２０をＣＰＵ用のＩＣチップ１２０と別に製造
しながら、ＩＣチップ１２０とキャシュメモリ２０とを
近接して配置することが可能になり、ＩＣチップの高速
動作が可能となる。この第３実施形態では、ＩＣチップ
を内蔵すると共に表面に載置することで、それぞれの機
能が異なるＩＣチップなどの電子部品を実装させること
ができ、より高機能な多層プリント配線板を得ることが
できる。In the third embodiment, it becomes possible to dispose the IC chip 120 and the cache memory 20 close to each other while manufacturing the cache memory 20 having a low yield separately from the IC chip 120 for the CPU. It enables high-speed operation. In the third embodiment, by mounting an IC chip and mounting it on the surface, electronic components such as IC chips having different functions can be mounted, and a higher-performance multilayer printed wiring board can be obtained. You can

【００７９】次に、本発明の第４実施形態に係る多層プ
リント配線板について、図１１を参照して説明する。上
述した第１実施形態では、基板全面に半田バンプ７６を
形成した。これに対して、第４実施形態では、ＩＣチッ
プ２０の領域Ｒ１以外の領域Ｒ２にのみ半田バンプ（外
部接続端子）７６を形成してある。Next, a multilayer printed wiring board according to the fourth embodiment of the present invention will be described with reference to FIG. In the above-described first embodiment, the solder bumps 76 are formed on the entire surface of the substrate. On the other hand, in the fourth embodiment, the solder bumps (external connection terminals) 76 are formed only in the region R2 other than the region R1 of the IC chip 20.

【００８０】図１１に示す第４実施形態の多層プリント
配線板は、ＩＣチップ２０を収容するコア基板３０と、
層間樹脂絶縁層５０、層間樹脂絶縁層１５０とからな
る。層間樹脂絶縁層５０には、バイアホール６０および
導体回路５８が形成され、層間樹脂絶縁層１５０には、
バイアホール１６０および導体回路１５８が形成されて
いる。The multilayer printed wiring board of the fourth embodiment shown in FIG. 11 includes a core substrate 30 for accommodating the IC chip 20,
It is composed of an interlayer resin insulation layer 50 and an interlayer resin insulation layer 150. The via hole 60 and the conductor circuit 58 are formed in the interlayer resin insulation layer 50, and the interlayer resin insulation layer 150 is formed in the interlayer resin insulation layer 150.
A via hole 160 and a conductor circuit 158 are formed.

【００８１】層間樹脂絶縁層１５０の上には、ソルダー
レジスト層７０が配設されている。ソルダーレジスト層
７０の開口部７１下の導体回路１５８には、図示しない
ドータボード、マザーボード等の外部基板と接続するた
めの半田バンプ７６が設けられている。半田バンプ７６
は、ＩＣチップ２０の直上の領域Ｒ１以外の領域Ｒ２に
配設されている。A solder resist layer 70 is provided on the interlayer resin insulation layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connecting to an external substrate such as a daughter board or a mother board (not shown). Solder bump 76
Are arranged in a region R2 other than the region R1 immediately above the IC chip 20.

【００８２】図１１中の多層プリント配線板のＥ−Ｅ断
面を図１２に示す。図１２の点線で示される内側の領域
は、ＩＣチップ２０が内蔵されている領域Ｒ１である。
図１２の点線の外側から実線の内側の領域は、ＩＣチッ
プ２０が内蔵されていない領域Ｒ２である。導体回路１
５８は、放射線状に領域Ｒ１から領域Ｒ２へ広がるよう
に形成されている。半田バンプ７６と接続するための半
田パッド７５は、領域Ｒ２内で格子状に配置されてい
る。FIG. 12 shows an EE cross section of the multilayer printed wiring board shown in FIG. The inner region shown by the dotted line in FIG. 12 is a region R1 in which the IC chip 20 is embedded.
The region from the outside of the dotted line to the inside of the solid line in FIG. 12 is a region R2 in which the IC chip 20 is not incorporated. Conductor circuit 1
58 is formed so as to radially spread from the region R1 to the region R2. The solder pads 75 for connecting to the solder bumps 76 are arranged in a grid pattern in the region R2.

【００８３】図１３（Ｃ）は、第４実施形態の多層プリ
ント配線板の平面図を示している。半田バンプ７６又は
導電性接続ピンは、領域Ｒ２内で格子状に配置されて、
図示しないドータボード、マザーボード等の外部基板と
接続される。なお、半田バンプ７６は、図１３（Ｄ）に
示すように領域Ｒ２内で千鳥状に形成されてもよい。FIG. 13C is a plan view of the multilayer printed wiring board according to the fourth embodiment. The solder bumps 76 or the conductive connection pins are arranged in a grid pattern in the region R2,
It is connected to an external board (not shown) such as a daughter board or a mother board. Note that the solder bumps 76 may be formed in a zigzag shape in the region R2 as shown in FIG.

【００８４】第４実施形態の多層プリント配線板では、
ＩＣチップ２０が内蔵されていない基板上の領域Ｒ２に
半田バンプ７６を配設する。これにより、セラミックか
ら成り熱膨張係数の小さなＩＣチップ２０と、樹脂から
成り熱膨張係数の大きな層間絶縁層５０、１５０および
ソルダーレジスト層７０との熱膨張による影響を小さく
できるため、半田バンプ７６の周囲などに発生する剥
離、クラックを防止できる。これにより、半田パンプ７
６の脱落や位置ずれを防止して、電気的接続性や信頼性
を向上させることが可能となる。In the multilayer printed wiring board of the fourth embodiment,
The solder bumps 76 are arranged in the region R2 on the substrate in which the IC chip 20 is not built. This can reduce the influence of thermal expansion of the IC chip 20 made of ceramic and having a small thermal expansion coefficient, and the interlayer insulating layers 50 and 150 made of resin and having a large thermal expansion coefficient, and the solder resist layer 70. It is possible to prevent peeling and cracks that occur in the surroundings. As a result, the solder pump 7
It is possible to prevent the falling of 6 and the displacement thereof, and to improve the electrical connectivity and reliability.

【００８５】引き続き、本発明の第５実施形態に係る多
層プリント配線板について、図１４を参照して説明す
る。上述した第１実施形態では、ＩＣチップ２０のパッ
ド２４上にトラジション層３８を形成し、該トラジショ
ン層３８に層間樹脂絶縁層５０のビア６０を接続した。
これに対して、第５実施形態では、トラジション層を設
けることなくビア６０をパッド２４へ直接接続してあ
る。即ち、ＩＣチップ２０のダイパッドが銅から成るた
め、銅から成るバイアホール６０にて直接接続を取って
いる。この第４実施形態は、第１〜第３実施形態と比較
して工程を削減できるため、廉価に構成できる利点があ
る。Next, a multilayer printed wiring board according to the fifth embodiment of the present invention will be described with reference to FIG. In the above-described first embodiment, the transition layer 38 is formed on the pad 24 of the IC chip 20, and the via 60 of the interlayer resin insulation layer 50 is connected to the transition layer 38.
On the other hand, in the fifth embodiment, the via 60 is directly connected to the pad 24 without providing the transition layer. That is, since the die pad of the IC chip 20 is made of copper, the via hole 60 made of copper is used for direct connection. The fourth embodiment has an advantage that it can be constructed at a low cost because the number of steps can be reduced as compared with the first to third embodiments.

【００８６】[0086]

【発明の効果】本発明の構造により、リード部品を介さ
ずに、ＩＣチップとプリント配線板との接続を取ること
ができる。そのため、樹脂封止も不要となる。更に、リ
ード部品や封止樹脂に起因する不具合が起きないので、
接続性や信頼性が向上する。また、ＩＣチップのダイパ
ッドとプリント配線板の導電層が直接接続されているの
で、電気特性も向上させることができる。更に、従来の
ＩＣチップの実装方法に比べて、ＩＣチップ〜基板〜外
部基板までの配線長も短くできて、ループインダクタン
スを低減できる効果もある。According to the structure of the present invention, the IC chip and the printed wiring board can be connected without the interposition of lead parts. Therefore, resin sealing is also unnecessary. Furthermore, since there are no problems caused by lead parts or sealing resin,
Connectivity and reliability are improved. Moreover, since the die pad of the IC chip and the conductive layer of the printed wiring board are directly connected, the electrical characteristics can be improved. Further, compared with the conventional IC chip mounting method, the wiring length from the IC chip to the substrate to the external substrate can be shortened, and the loop inductance can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の
第１実施形態に係る多層プリント配線板の製造工程図で
ある。1A, 1B, 1C and 1D are manufacturing process diagrams of a multilayer printed wiring board according to a first embodiment of the present invention.

【図２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の
第１実施形態に係る多層プリント配線板の製造工程図で
ある。2 (A), (B), (C), and (D) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

【図３】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の
第１実施形態に係る多層プリント配線板の製造工程図で
ある。3 (A), (B), (C), and (D) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

【図４】（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施
形態に係る多層プリント配線板の製造工程図である。4 (A), (B) and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

【図５】（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施
形態に係る多層プリント配線板の製造工程図である。5 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

【図６】本発明の第１実施形態に係る多層プリント配線
板の断面図である。FIG. 6 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

【図７】（Ａ）は、図３（Ａ）中のトランジション層を
拡大して示す図であり、（Ｂ）は、図７（Ａ）のＢ矢視
図であり、（Ｃ）、（Ｄ）、（Ｅ）は、トランジション
層の改変例の説明図である。7 (A) is an enlarged view of the transition layer in FIG. 3 (A), FIG. 7 (B) is a view taken in the direction of arrow B in FIG. 7 (A), and FIG. (D), (E) is explanatory drawing of the modification of a transition layer.

【図８】本発明の第１実施形態の改変例に係る多層プリ
ント配線板の断面図である。FIG. 8 is a cross-sectional view of a multilayer printed wiring board according to a modified example of the first embodiment of the present invention.

【図９】本発明の第２実施形態に係る多層プリント配線
板の断面図である。FIG. 9 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

【図１０】本発明の第３実施形態に係る多層プリント配
線板の断面図である。FIG. 10 is a sectional view of a multilayer printed wiring board according to a third embodiment of the present invention.

【図１１】本発明の第４実施形態に係る多層プリント配
線板の断面図である。FIG. 11 is a sectional view of a multilayer printed wiring board according to a fourth embodiment of the present invention.

【図１２】図１１のＥ−Ｅ断面図である。12 is a sectional view taken along line EE of FIG.

【図１３】（Ａ）は、本発明の第１実施形態に係る多層
プリント配線板の平面図であり、（Ｂ）は、バンプが千
鳥状に配置された第１実施形態に係る多層プリント配線
板の平面図であり、（Ｃ）は、第４実施形態に係る多層
プリント配線板の平面図であり、（Ｄ）は、バンプが千
鳥状に配置された第４実施形態に係る多層プリント配線
板の平面図である。13A is a plan view of the multilayer printed wiring board according to the first embodiment of the present invention, and FIG. 13B is a multilayer printed wiring board according to the first embodiment in which bumps are arranged in a staggered pattern. It is a top view of a board, (C) is a top view of a multilayer printed wiring board concerning a 4th embodiment, and (D) is a multilayer printed wiring concerning a 4th embodiment in which bumps are arranged in a zigzag pattern. It is a top view of a board.

【図１４】本発明の第５実施形態に係る多層プリント配
線板の断面図である。FIG. 14 is a sectional view of a multilayer printed wiring board according to a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

２０ ＩＣチップ（電子部品） ２４ ダイパッド ３０ コア基板 ３２ 凹部 ３３ 第１薄膜層 ３６ 第２薄膜層 ３７ 電解めっき膜（厚付け膜） ３８ トラジション層 ５０ 層間樹脂絶縁層 ５８ 導体回路 ６０ バイアホール ７０ ソルダーレジスト層 ７６ 半田バンプ（外部接続端子） ９０ ドータボード ９６ 導電性接続ピン（外部接続端子） ９７ 導電性接着剤 １２０ ＩＣチップ（電子部品） １５０ 層間樹脂絶縁層 １５８ 導体回路 １６０ バイアホール 20 IC chips (electronic parts) 24 die pad 30 core substrate 32 recess 33 First thin film layer 36 Second thin film layer 37 Electrolytic plating film (thick film) 38 Transition Layer 50 interlayer resin insulation layer 58 Conductor circuit 60 via holes 70 Solder resist layer 76 Solder bump (external connection terminal) 90 Daughter Board 96 Conductive connection pin (external connection terminal) 97 Conductive adhesive 120 IC chips (electronic parts) 150 interlayer resin insulation layer 158 Conductor circuit 160 via holes

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 基板上に層間絶縁層と導体層とが繰り返
し形成され、該層間絶縁層には、ビアが形成され、該ビ
アを介して電気的接続される多層プリント配線板におい
て、 前記基板には、パッドが銅から成る電子部品が内蔵され
ていることを特徴とする多層プリント配線板。1. A multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and a via is formed in the interlayer insulating layer, and electrically connected through the via, the substrate. The multi-layer printed wiring board is characterized in that the pad has built-in electronic components made of copper. 【請求項２】 表面に電子部品が実装されていることを
特徴とする請求項１に記載の多層プリント配線板。2. The multilayer printed wiring board according to claim 1, wherein an electronic component is mounted on the surface. 【請求項３】 基板上に層間絶縁層と導体層とが繰り返
し形成され、該層間絶縁層には、ビアが形成され、該ビ
アを介して電気的接続される多層プリント配線板におい
て、 前記基板には、パッドが銅から成る電子部品が内蔵さ
れ、 前記該電子部品のダイパッド上部には、最下層の層間絶
縁層のビアと接続させるためのトラジション層が形成さ
れていることを特徴とする多層プリント配線板。3. A multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and a via is formed in the interlayer insulating layer, and electrically connected through the via, the substrate. An electronic component whose pad is made of copper is built in, and a transition layer for connecting to a via of the lowermost interlayer insulating layer is formed above the die pad of the electronic component. Multilayer printed wiring board. 【請求項４】 前記電子部品がＩＣチップであることを
特徴とする請求項１〜３に記載の多層プリント配線板。4. The multilayer printed wiring board according to claim 1, wherein the electronic component is an IC chip.
JP2001192925A 2001-06-26 2001-06-26 Multilayer printed wiring board Expired - Lifetime JP4243922B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001192925A JP4243922B2 (en) 2001-06-26 2001-06-26 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001192925A JP4243922B2 (en) 2001-06-26 2001-06-26 Multilayer printed wiring board

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007140148A Division JP4651643B2 (en) 2007-05-28 2007-05-28 Multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JP2003007896A true JP2003007896A (en) 2003-01-10
JP4243922B2 JP4243922B2 (en) 2009-03-25

Family

ID=19031305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001192925A Expired - Lifetime JP4243922B2 (en) 2001-06-26 2001-06-26 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP4243922B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165810A (en) * 2005-12-16 2007-06-28 Ibiden Co Ltd Multilayer printed wiring board, and method of manufacturing same
JPWO2005076351A1 (en) * 2004-02-09 2007-08-02 株式会社村田製作所 Component built-in module and manufacturing method thereof
WO2008093531A1 (en) * 2007-01-29 2008-08-07 Nec Corporation Semiconductor device and method for manufacturing the same
US7545049B2 (en) 2003-02-13 2009-06-09 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure
US7544537B2 (en) 2005-09-28 2009-06-09 Tdk Corporation Semiconductor IC-embedded substrate and method for manufacturing same
US7547975B2 (en) 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
JP2010192781A (en) * 2009-02-20 2010-09-02 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing same
US7868464B2 (en) 2004-09-16 2011-01-11 Tdk Corporation Multilayer substrate and manufacturing method thereof
US8188375B2 (en) 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
US8217509B2 (en) 2008-02-18 2012-07-10 Shinko Electric Industries Co., Ltd. Semiconductor device
US8687096B2 (en) 2007-02-23 2014-04-01 Intellectual Ventures Ii Llc Adapted piecewise linear processing drive
WO2014103530A1 (en) * 2012-12-26 2014-07-03 株式会社村田製作所 Substrate with built-in component

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7964950B2 (en) 2003-02-13 2011-06-21 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US7545049B2 (en) 2003-02-13 2009-06-09 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure
US7691673B2 (en) 2003-02-13 2010-04-06 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US7547975B2 (en) 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
US7569925B2 (en) 2004-02-09 2009-08-04 Murata Manufacturing Co. Ltd. Module with built-in component
JPWO2005076351A1 (en) * 2004-02-09 2007-08-02 株式会社村田製作所 Component built-in module and manufacturing method thereof
US7868464B2 (en) 2004-09-16 2011-01-11 Tdk Corporation Multilayer substrate and manufacturing method thereof
US7544537B2 (en) 2005-09-28 2009-06-09 Tdk Corporation Semiconductor IC-embedded substrate and method for manufacturing same
US8530752B2 (en) 2005-11-29 2013-09-10 Tdk Corporation Multilayer circuit board and method for manufacturing the same
US8188375B2 (en) 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
JP2007165810A (en) * 2005-12-16 2007-06-28 Ibiden Co Ltd Multilayer printed wiring board, and method of manufacturing same
JP4673207B2 (en) * 2005-12-16 2011-04-20 イビデン株式会社 Multilayer printed wiring board and manufacturing method thereof
WO2008093531A1 (en) * 2007-01-29 2008-08-07 Nec Corporation Semiconductor device and method for manufacturing the same
US8043953B2 (en) 2007-01-29 2011-10-25 Renesas Electronics Corporation Semiconductor device including an LSI chip and a method for manufacturing the same
JPWO2008093531A1 (en) * 2007-01-29 2010-05-20 日本電気株式会社 Semiconductor device and manufacturing method thereof
US8687096B2 (en) 2007-02-23 2014-04-01 Intellectual Ventures Ii Llc Adapted piecewise linear processing drive
US8217509B2 (en) 2008-02-18 2012-07-10 Shinko Electric Industries Co., Ltd. Semiconductor device
US9048242B2 (en) 2008-02-18 2015-06-02 Shinko Electric Industries Co., Ltd. Semiconductor device manufacturing method, semiconductor device, and wiring board
JP2010192781A (en) * 2009-02-20 2010-09-02 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing same
WO2014103530A1 (en) * 2012-12-26 2014-07-03 株式会社村田製作所 Substrate with built-in component
JP5574071B1 (en) * 2012-12-26 2014-08-20 株式会社村田製作所 Component built-in board
US9484397B2 (en) 2012-12-26 2016-11-01 Murata Manufacturing Co., Ltd. Component-embedded substrate

Also Published As

Publication number Publication date
JP4243922B2 (en) 2009-03-25

Similar Documents

Publication Publication Date Title
JP4854845B2 (en) Multilayer printed circuit board
JP4270769B2 (en) Manufacturing method of multilayer printed wiring board
WO2001063991A1 (en) Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4108285B2 (en) Manufacturing method of multilayer printed wiring board
JP4869488B2 (en) Manufacturing method of multilayer printed wiring board
JP4248157B2 (en) Multilayer printed wiring board
JP4771608B2 (en) Printed wiring board
JP4137389B2 (en) Method for manufacturing multilayer printed wiring board incorporating semiconductor element
JP4957638B2 (en) Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP4243922B2 (en) Multilayer printed wiring board
JP2002170840A (en) Manufacturing method of semiconductor device and multi-layer printed circuit board including the same
JP4475836B2 (en) Manufacturing method of semiconductor device
JP4854846B2 (en) Manufacturing method of multilayer printed wiring board
JP4934900B2 (en) Manufacturing method of multilayer printed wiring board
JP4618919B2 (en) Method for manufacturing multilayer printed wiring board incorporating semiconductor element
JP4854847B2 (en) Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4722961B2 (en) Method for manufacturing multilayer printed wiring board incorporating semiconductor element
JP4549366B2 (en) Multilayer printed wiring board
JP4049554B2 (en) Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4033639B2 (en) Multilayer printed wiring board
JP2002185145A (en) Multilayer printed wiring board and its manufacturing method
JP4458716B2 (en) Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4749563B2 (en) Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4785268B2 (en) Multilayer printed wiring board with built-in semiconductor elements
JP4651643B2 (en) Multilayer printed wiring board

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050901

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050909

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070405

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070410

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070528

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080115

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080304

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20081224

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081224

R150 Certificate of patent or registration of utility model

Ref document number: 4243922

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120116

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130116

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130116

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term