KR101193212B1 - Wiring board having built-in semiconductor chip and method for manufacturing the same - Google Patents

Abstract

Provided is a method for manufacturing a semiconductor chip-embedded wiring board which can simplify the manufacturing process while increasing the connection reliability of the semiconductor chip and can shorten the manufacturing time. Specifically, in the lamination step, the thermosetting resin film 21b having the semiconductor chip 50 provided with the stud bump made of Au and the pad 31 on the electrode 51a is formed through the thermoplastic resin film 22b. 52a) and the pad 31 are arranged in the direction facing each other. In the pressing and heating step, the pad 31, the stud bumps 52a, and the electrodes 51a and the stud bumps 52a are joined by solid phase diffusion bonding, thereby forming Cu and the stud bumps 52a. The CuAu alloy layer 522, which is an alloy layer of Au, is formed, and all of Al of the electrode 51a is AuAl alloyed to form an AuAl alloy layer 521 containing no Al.

Description

WIRING BOARD HAVING BUILT-IN SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip embedded wiring board having a wiring portion formed on an insulating substrate containing a thermoplastic resin and having a semiconductor chip embedded therein, and a method of manufacturing the same.

DESCRIPTION OF RELATED ART Conventionally, the thing of patent document 1 is known as a manufacturing method of the board | substrate with which the wiring part is formed in the insulating base material containing a thermoplastic resin, and the electronic component is embedded.

In this manufacturing method, several resin films, including a resin film having a conductive pattern formed on its surface and a resin film filled with a conductive paste in a via hole, are laminated so as to incorporate electronic components into a laminate.

The thermoplastic resin contained in the resin film is softened by heating while pressing the laminate from above and below. Thus, the resin film is bonded to each other and integrated, and the electronic component is sealed. In addition, the conductive paste filled in the via hole is sintered to form an interlayer connection portion (conductive composition), and the pads (conductor patterns) and conductor patterns corresponding to the electrodes of the electronic component are electrically connected to each other.

According to this, the multilayer board | substrate which embeds an electronic component can be formed collectively by pressurization and heating, and a manufacturing process can be simplified.

However, in the semiconductor chip (IC chip) in which the device is integrated, the electrode spacing is narrower (so-called fine pitch) due to the high integration of the device, the high speed, and the suppression of the buildup of the semiconductor chip (substrate incorporating the semiconductor chip). Has been. For this reason, in the case of employing a semiconductor chip (bare chip) as an embedded electronic component and flip chip mounting without rewiring, in the above-described method, if the electrical insulation between neighboring interlayer connections is to be ensured, very small diameters (eg For example, it is considered that via holes having a diameter of several μm to about 10 μm) must be formed, so that the formation of the via holes and the filling of the conductive paste become difficult.

In addition, since the filling amount of the conductive paste is small, it is also considered that an amount of the conductive particles sufficient for diffusion bonding with the metal constituting the electrode of the semiconductor chip or the pad of the substrate cannot be secured.

On the other hand, it is also conceivable to employ a flip chip mounting in which a stud bump is provided on an electrode of a semiconductor chip and the stud bump is connected to a pad of a substrate. In particular, as described in Patent Document 2, by directly heating Au bumps of a semiconductor chip and a copper pad (electrode) of a substrate by heating while pressing, electrical connection reliability can be improved while corresponding to fine pitch.

On the other hand, as a technique of improving the connection reliability of the electrode and bump of a semiconductor chip, there exists a semiconductor package which has a junction structure of Al electrode and Au (gold) bump disclosed in patent document 3. As shown in FIG. In this semiconductor package, Au bumps are formed on the Al electrode of the semiconductor chip (transistor chip) by a ball bonding method, and Au bumps are formed by heat treatment at, for example, 300 ° C.-2h or 250 ° C.-10h. All of the Al constituting the lower Al electrode is changed to AuAl alloy. Thereby, the intensity | strength of an Al electrode / Au bump can be improved.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2007-324550 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-60602 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2000-349125

However, as shown in patent document 2, in order to directly bond a bump and a pad, time required as pressurization and heating time is needed. Further, as shown in Patent Document 3, the time required (for example, 300 deg. C to 2 h or 250 deg. C to 10 h) is required to change all Al constituting the Al electrode to AuAl alloy. For this reason, the time taken to form a semiconductor chip embedded wiring board becomes long.

SUMMARY OF THE INVENTION In view of the above problems, a first object of the present invention is to provide a method for manufacturing a semiconductor chip-embedded wiring board which can simplify the manufacturing process while increasing the connection reliability of the semiconductor chip, thereby shortening the manufacturing time. Another object of the present invention is to provide a semiconductor chip-embedded wiring board which can increase the connection reliability of the semiconductor chip.

According to a first example of the present invention for achieving the above object,

As a manufacturing method of a semiconductor chip embedded wiring board which embeds the semiconductor chip which has the 1st electrode which consists of Al type material in one surface,

A plurality of resin films including a resin film having a conductive pattern made of Cu on the surface and a resin film filled with a conductive paste in a via hole, and a thermoplastic resin film containing a thermoplastic resin are positioned at at least one interval of the semiconductor chip. A lamination step of laminating the electrode forming surface and the back surface of the electrode forming surface to form a laminate;

Pressing from above and below the stacking direction while heating the laminate to soften the thermoplastic resin and to integrate a plurality of resin films collectively, seal the semiconductor chip and use the conductive particles in the conductive paste as the sintered body to form the sintered body and the conductor pattern. And a pressurizing and heating step of forming an excitation wiring section,

In the lamination step, the stud bump and the pad face each other via a second film as the thermoplastic resin film, the first film including a semiconductor chip and a resin film provided with a stud bump made of Au and a pad formed as part of a conductor pattern on the first electrode. Place it in the viewing direction,

In the pressurization and heating process, the pad, the stud bump, and the first electrode and the stud bump are joined by solid phase diffusion bonding to form a CuAu alloy layer, which is an alloy layer of Cu constituting the pad and AU constituting the stud bump. In addition, AuAl alloys all Al in the thickness direction of the site | part which opposes the stud bump in a 1st electrode, and makes a 1st electrode the AuAl alloy layer which does not contain Al, It is characterized by the above-mentioned.

In the first example of the present invention, a plurality of resin films comprising a thermoplastic resin film are laminated to be laminated so that the thermoplastic resin films are positioned at least one sheet apart and adjacent to the electrode forming surface of the semiconductor chip and the back surface of the electrode forming surface. do. Therefore, by softening the thermoplastic resin contained in the thermoplastic resin film by pressurization and heating, the plurality of resin films can be integrally integrated, and at least the semiconductor chip can be sealed by the thermoplastic resin film adjacent to the semiconductor chip. Moreover, the wiring part can be formed with a conductor pattern by making the electroconductive particle in an electroconductive paste into a sintered compact by the said pressurization and heating. For this reason, a manufacturing process can be simplified.

In addition, in the pressurizing and heating step, the laminate is bonded to the pad, the stud bump, and the first electrode and the stud bump by solid phase diffusion bonding, thereby forming CuAu alloy which is an alloy layer of Cu constituting the pad and Au constituting the stud bump. In addition to forming the layer, Al of the first electrode is AuAl alloyed in the thickness direction of the portion facing the stud bump to form an AuAl alloy layer. In this way, by forming alloy layers on both sides of the stud bump (the semiconductor chip side and the opposite side), the connection reliability of the semiconductor chip can be improved.

In particular, on the semiconductor chip side of the stud bumps, if Al of the first electrode of the semiconductor chip remains (i.e., Al remains between the semiconductor chip and the stud bumps), the Al remains in the high temperature use environment. Au constituting the stud bump is solid phase diffused to produce Au ₅ Al ₂ . Since the Au ₅ the growth rate of Al ₂ is compared with the Au ₄ Al is much faster, this, Au ₅ Al because the diffusion of Au not complete the generation of the _second, larger Kendall voids at the interface between the Au ₄ Al and Au ₅ Al ₂ ( kirkendall void) In addition, a crack occurs based on the Kirkendal void.

Therefore, in the first example of the present invention, all the Al in the thickness direction of the portion facing the stud bump in the first electrode is AuAl alloyed to form an AuAl alloy layer, which constitutes the stud bump even in a high temperature use environment. Since Au can be prevented from diffusing in solid phase, it is possible to suppress the occurrence of Kerkendal voids and even cracks.

As described above, the present invention forms the CuAu alloy layer, which is an alloy layer of Cu constituting the pad and Au constituting the stud bump, by using heat and pressure during the pressurizing and heating step with respect to the laminate. Since Al is all AuAl alloyed in the thickness direction of the part facing the stud bump to form an AuAl alloy layer, when Al bumps are formed on the Al electrode by ball bonding, Al is AlAu alloyed and flipped. In the chip mounting step, the stud bump and the pad are brought into a bonded state, and the manufacturing time can be shortened as compared with the method of performing the pressurization and heating step thereafter. Moreover, this CuAu alloy layer and AuAl alloy layer can also be sealed by a thermoplastic resin film by this pressurization and a heating process.

As described above, the manufacturing process of the semiconductor chip embedded wiring board can be simplified while increasing the connection reliability of the semiconductor chip, and the manufacturing time can be shortened.

Moreover, as several resin films, you may have the thermosetting resin film containing a thermosetting resin besides a thermoplastic resin film. In the pressurizing and heating step, the thermoplastic resin constituting the thermoplastic resin film is softened, and thus, the resin films are bonded to each other to be integrated, so that the thermoplastic resin films may be positioned at least one sheet apart as a laminate.

As a thermoplastic resin film containing a thermoplastic resin, the film containing inorganic materials, such as glass fiber, can also be employ | adopted with a thermoplastic resin except the 2nd film which consists of thermoplastic resins. The same applies to the film containing the thermoplastic resin. In addition, as a 1st film, either a film containing a thermoplastic resin and the film containing a thermosetting resin can be employ | adopted.

Further, according to the second example of the present invention, it is preferable that the AuAl alloy layer mainly containing Au ₄ Al alloy is used in the pressing and heating step.

According to a third example of the present invention, it is preferable to form a CuAu alloy layer containing a CuAu ₃ alloy in the pressing and heating step.

In addition, according to the fourth example of the present invention, as a preliminary step of the lamination step, an attaching step of attaching the second film to the pad forming surface of the substrate so as to cover the pad by pressurizing while heating the substrate including the first film. And pressurizing while heating at a temperature equal to or higher than the melting point of the thermoplastic resin constituting the second film while pushing the stud bump while melting the second film and pressure welding the corresponding pad to the melted second film. You may provide the flip chip mounting process which seals between a semiconductor chip and a board | substrate.

As described above, in the pre-processing of the lamination step, the second film made of the thermoplastic resin film is disposed between the semiconductor chip and the substrate including the first film, and is pressed while heating to a temperature equal to or higher than the melting point of the thermoplastic resin. do. Therefore, while raising the temperature to the melting point or more of the thermoplastic resin, the thermoplastic resin constituting the second film can be made to have fluidity, thereby moving the thermoplastic resin positioned between the stud bump and the pad by pressurization, and the stud bump. Can be brought into direct contact with the stud bumps and the pads (in other words, provisionally bonded states).

At this time, the thermoplastic resin having fluidity by heating seals between the semiconductor chip and the substrate, including the periphery of the connection portion of the stud bump and the pad, thereby ensuring electrical insulation between the connection portions. Moreover, the connection reliability in a connection part can be improved.

At the time when the stud bump and the pad are brought into a press-contact state, the flip chip mounting process (heating and pressurization) is terminated, and the stud bump and the pad are solid-phase diffusion-bonded by pressurization and heating received in the pressurization and heating process. As described above, since the stud bumps and the pads are solid-phase diffusion-bonded by using the heat and pressure of the pressurization / heating process, the electrical connection reliability of the electrodes and the pads of the semiconductor chip can be improved as compared with the pressure welding state.

In the flip chip mounting process, the stud bumps and the pads are placed in a press-contact state, and the stud bumps and the pads are solid-phase diffusion-bonded by using the heat and pressure of the pressurization / heating process. The production time can be shortened as a solid phase diffusion bonding, after which the pressurization and heating step can be performed.

In addition, if the stud bumps are brought into contact with the pads by pressing and heating without being brought into contact with the pads before the lamination step and brought into a bonded state, the stud bumps are formed by the buffering effect of the softened thermoplastic resin. It is also difficult to be pushed in, and as a result, a thermoplastic resin remains between the stud bump and the pad. On the other hand, in the fourth example of the present invention, the stud bumps and the pads are press-contacted prior to the lamination process, so that the stud bumps and the pads can be reliably joined by the pressurization and heating of the pressurization and heating processes.

Moreover, according to the 5th example of this invention, the state which attached the 2nd film in which the through-hole was attached to the pad formation surface at the position corresponding to the pad with respect to the board | substrate containing a 1st film as a front process of a lamination process. Pressurizes the stud bump to a corresponding pad through the through hole by heating while pressing at a temperature equal to or higher than the glass transition point of the thermoplastic resin constituting the second film, and between the semiconductor chip and the substrate with the softened second film. A flip chip mounting step of sealing may be provided.

As described above, since the through holes corresponding to the pads are provided in advance in the second film before heating and pressing in the flip chip mounting step, if the calories are the same, the pressure contact state between the stud bumps and the pads and the sealing by the second film are short. The structure can be formed. In other words, the heating and pressing time in the flip chip mounting step, and further, the manufacturing time of the semiconductor chip embedded wiring board can be shortened.

In addition, if the heating and pressing time and pressurization conditions are the same, it is possible to secure the pressure contact state of the stud bump and the land with less heat than the method of the fourth example.

This through hole may be provided for each pad as in the sixth example of the present invention. According to this, since a thermoplastic resin film is located between the stud bump and each connection part of a pad, in a flip chip mounting process, the softened thermoplastic resin is easy to cover a connection part. That is, it is easy to ensure the electrical insulation between each connection part, even if a through hole is provided and it is easy to improve the connection reliability in a connection part.

In addition, when the 1st electrode of a semiconductor chip is a fine pitch, a pad also becomes a fine pitch. For this reason, it is difficult to form the through hole smaller than a pad (for example, 30 micrometers in diameter). However, unlike via holes for forming interlayer connections, conductive holes are not filled in the through holes, and these through holes do not define the buildup of the connecting portions for electrically connecting the electrodes and pads of the semiconductor chip. Therefore, the through hole may have a greater degree of freedom in forming a hole than the via hole because it may be larger than the pad, and can be provided for each pad.

On the other hand, as in the seventh example of the present invention, one may be provided for each of the plurality of pads. According to this, it is easy to form a through hole compared with the structure (pitch) between pads compared with the structure which provides one through hole for every pad. In other words, it is suitable for fine pitch.

In addition, as in the eighth example of the present invention, a flip chip mounting step includes a step of attaching a second film provided with a through hole to a pad forming surface of the substrate by pressing while heating a position different from the position where the through hole is formed. Do it.

According to this structure, the semiconductor chip is attached by heating and pressing a position different from the position where the through hole is formed so that the through hole is not crushed by heating or pressing when the second film is attached to the substrate while the through hole is provided in advance. When mounting on a board | substrate, a stud bump and a pad can be made into a pressure contact state for a short time.

On the other hand, as in the ninth example of the present invention, in the flip chip mounting step, the second film is attached to the pad forming surface of the substrate so as to cover the pad by pressing while heating, and then corresponds to the pad in the second film. You may include the process of forming a through hole in a position.

According to this, since a through hole is formed after a 2nd film is affixed on a board | substrate, a through hole can be formed with high positional precision.

As in the tenth example of the present invention, in the lamination step, the semiconductor chip and the first film are laminated in a state in which the stud bumps and the pad are separated from each other through the second film, and the stud is applied in the pressing and heating step. The bumps may be pushed while melting the second film to bond the pads, the stud bumps, and the first electrode and the stud bumps by solid phase diffusion bonding.

By doing in this way, since the semiconductor chip built-in wiring board can be manufactured without performing the said previous process, manufacturing time can be shortened.

In addition, as in the eleventh example of the present invention, the semiconductor chip may have the second electrode on the back surface of the electrode formation surface on which the first electrode is formed.

In the lamination step, as in the twelfth example of the present invention, a heat dissipation member made of a metal material is disposed on the surface layer in the direction facing the second electrode of the semiconductor chip in the laminate. You may make it join together the heat conductive member and the electrically conductive paste filled in the via hole of the resin film.

By doing in this way, heat dissipation can be improved, without increasing the number of manufacturing processes of a semiconductor chip embedded wiring board.

In addition, when the thermoplastic resin film (for example, 2nd film) which seals a semiconductor chip is less than 5 micrometers, there exists a possibility that a stress may become high in a pressurization and a heating process, and it may peel off from the surface of a semiconductor chip. Therefore, as shown in the thirteenth example of the present invention, the thermoplastic resin film sealing the semiconductor chip is preferably 5 µm or more in thickness.

By doing in this way, peeling from the surface of a semiconductor chip can be suppressed.

In addition, as shown in the fourteenth example of the present invention, it is preferable that the thermoplastic resin film (for example, the second film) sealing the semiconductor chip does not contain a filler.

By doing in this way, the stress with respect to a semiconductor chip can be reduced in a pressurization and a heating process.

According to a fifteenth example of the present invention for achieving the second object, a semiconductor chip embedded wiring board,

An insulating substrate comprising at least a thermoplastic resin,

The semiconductor chip which has a 1st electrode on one surface, is embedded in the insulating base material, and is sealed by the thermoplastic resin of this insulating base material, with several elements comprised,

It is provided in an insulating base material and is electrically connected with the 1st electrode of a semiconductor chip, The conductor pattern which consists of Cu, The interlayer connection part provided in the via hole, The Au which connects the 1st electrode and pad as part of a conductor pattern A wiring portion including a connection portion,

At the interface of a connection part and a pad, it has a CuAu alloy layer which is an alloy layer of Au which comprises a connection part, and Cu which comprises a pad,

The site | part facing the connection part in a 1st electrode consists of AuAl alloy layer which does not contain Al in the thickness direction. It is characterized by the above-mentioned.

Thus, while having the CuAu alloy layer which is an alloy layer of Au which comprises a stud bump and Cu which comprises a pad at the interface of a pad as part of a stud bump and a conductor pattern, the thickness of the site | part which opposes a connection part is 1st electrode. By using the AuAl alloy layer containing no Al in the direction, the connection reliability of the semiconductor chip to be embedded can be improved.

In particular, on the semiconductor chip side of the stud bumps, if Al of the first electrode of the semiconductor chip remains (i.e., Al remains between the semiconductor chip and the stud bumps), the Al remains in the high temperature use environment. Au constituting the stud bump is solid phase diffused to produce Au ₅ Al ₂ . The growth rate of Au ₅ Al ₂ is much faster than that of Au ₄ Al. Therefore, Au diffusion is not completed when Au ₅ Al ₂ is generated, resulting in a kekendal void at the interface between Au ₄ Al and Au ₅ Al ₂ . . In addition, a crack occurs based on the Kirkendal void.

Therefore, in the present invention, all the Al is AuAl alloyed in the thickness direction of the portion facing the connecting portion of the first electrode to form an AuAl alloy layer mainly containing Au ₄ Al alloy, so that the stud bump is used even in a high temperature use environment. Since Au which constitutes a solid phase can be prevented from spreading, it is possible to suppress occurrence of Kerkendal voids, and thus cracks.

In addition, as shown in the sixteenth example of the present invention, the first electrode is preferably made to mainly contain Au ₄ Al alloy.

In addition, as shown in the seventeenth example of the present invention, it is preferable to include CuAu ₃ alloy as the CuAu alloy layer at the interface between the connecting portion and the pad.

In addition, as shown in the eighteenth example of the present invention, in the insulating substrate, a plurality of films are laminated so as to be adjacent to both electrode formation surfaces of the semiconductor chip while the thermoplastic resin film containing the thermoplastic resin is positioned at least at one interval. The resin film may be bonded to each other by using an adhesive layer.

As the embedded semiconductor chip, as shown in the nineteenth example of the present invention, one having a second electrode on the back surface of the electrode formation surface on which the first electrode is formed can be adopted. In this case, this second electrode is electrically connected to the interlayer connecting portion.

In addition, as shown in the twentieth example of the present invention, a heat dissipation member made of a metal material is disposed on the surface layer in the direction facing the second electrode of the semiconductor chip in the insulating substrate, and the heat dissipation member is formed by the wiring portion. You may be connected with 2 electrodes.

By doing in this way, heat dissipation can be improved.

In addition, as shown in the twenty-first example of the present invention, the thermoplastic resin for sealing the semiconductor chip may not include a filler.

By doing in this way, the stress with respect to a semiconductor chip can be reduced in a pressurization and a heating process. Therefore, the reliability of the semiconductor chip can be improved.

1 is a cross-sectional view showing a schematic configuration of a semiconductor chip embedded wiring board formed by the manufacturing method according to the first embodiment.
FIG. 2: is sectional drawing which shows the preparation process of the resin film laminated | stacked on the board | substrate with which the semiconductor chip was mounted among the manufacturing processes of the semiconductor chip embedded wiring board shown in FIG.
(A)-(d) is sectional drawing which shows the process of flip-chip mounting a semiconductor chip on a board | substrate among the manufacturing processes of the semiconductor chip embedded wiring board shown in FIG.
It is a top view which shows the state which attached the 2nd film to the pad formation surface of the board | substrate in the process shown in FIG.
FIG. 5: is sectional drawing which shows the lamination process among the manufacturing processes of the semiconductor chip embedded wiring board shown in FIG.
FIG. 6 is a cross-sectional view showing a pressing and heating step in the manufacturing step of the semiconductor chip embedded wiring board shown in FIG. 1.
FIG. 7 is an enlarged view of a connecting portion in the semiconductor chip embedded wiring board shown in FIG. 1. FIG.
FIG. 8 is a cross-sectional view of a connecting portion at the time of stud bump formation in a semiconductor chip embedded wiring board formed by the manufacturing method according to the first embodiment. FIG.
9 is a cross-sectional view of a connecting portion after a forming step of a semiconductor unit in a semiconductor chip embedded wiring board formed by the manufacturing method according to the first embodiment.
10 is a cross-sectional view of the connecting portion after the pressing and heating step in the semiconductor chip embedded wiring board formed by the manufacturing method according to the first embodiment.
FIG. 11 is an enlarged view of the dotted line XI of FIG. 10.
12 is a cross-sectional view of the connecting portion after the pressing and heating step in the semiconductor chip embedded wiring board formed by the manufacturing method of the comparative example.
Fig. 13 is a cross-sectional view of the connecting portion after the pressing and heating step in the semiconductor chip embedded wiring board formed by the manufacturing method according to the first embodiment.
FIG. 14 is an enlarged image of a semiconductor chip portion in FIG. 13.
It is a figure which shows the state which attached the 2nd film to the pad formation surface of a board | substrate in the process of flip-chip mounting a semiconductor chip on a board | substrate among the manufacturing processes which concern on 2nd Embodiment, (a) is a top view and (b) are sectional drawing along the VIIB-VIIB line of (a).
It is a figure which shows the modification of the state which attached the 2nd film, (a) is a top view, (b) is sectional drawing along the VIIIB-VIIIB line of (a).
It is sectional drawing which shows schematic structure of the semiconductor chip embedded wiring board in a modification.

According to the present invention, in forming a semiconductor chip embedded wiring board, 1) a semiconductor chip (IC chip in a bare state) provided with stud bumps is formed on a substrate made of a first film provided with pads through a second film made of thermoplastic resin. 2) After flip-chip mounting and 2) mounting, when forming a wiring board by the batch lamination method known as PALAP, it carries out two steps of embedding the board | substrate with which the semiconductor chip was mounted, and in these two steps The main feature is the connection between the stud bump and the pad.

Therefore, as long as there is no notice in particular about the basic structure of a wiring board and a manufacturing method, the structure regarding PALAP which the applicant of this application applied so far can be employ | adopted suitably. In addition, PALAP is a registered trademark of Denso Corporation.

(First Embodiment)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the thickness direction (in other words, the lamination direction of several resin films) of the insulating base material 20 is shown simply in the thickness direction, and the direction perpendicular | vertical to this thickness direction is shown simply in a vertical direction. In addition, unless otherwise indicated, thickness shall show the thickness along a thickness direction.

The semiconductor chip-embedded wiring board 10 (hereinafter, simply referred to as the wiring board 10) shown in FIG. 1 is a basic component of the wiring board in which the semiconductor chip is embedded, and is applied to the insulating substrate 20 and the insulating substrate 20. The semiconductor chip 50 embedded in the conductor pattern 30, the interlayer connection part 40, and the insulating base material 20 which were provided, ie, it is provided is provided. In addition, the wiring board 10 shown in FIG. 1 is provided with the heat radiation member 60 in addition to the said basic component. Since the semiconductor chip embedded wiring board 10 is equipped with such a component, it can also be called simply a semiconductor device.

The insulating base material 20 consists of an electrically insulating material, and components other than this insulating base material 20, in the example shown in FIG. 1, the conductor pattern 30, the interlayer connection part 40, the semiconductor chip 50, and the heat radiation member It completes the function as the base material which keeps 60 at a predetermined position, and also completes the function which hold | maintains and protects the semiconductor chip 50 inside.

This insulating base material 20 mainly contains resin, and contains at least a thermoplastic resin as this resin, and several resin films containing a thermoplastic resin film are laminated | stacked, and it adheres and integrates by pressurization and heating. . The reason for including the thermoplastic resin is that the thermoplastic resin which can withstand high temperature when forming the insulating base 20 collectively in a pressurization and heating step described later is used as the adhesive and the sealing material.

For this reason, as several resin films, a thermoplastic resin film may be included so that it may be located at least 1 space | interval in a laminated state. For example, you may make it the structure containing only a thermoplastic resin film, and you may be set as the structure containing a thermosetting resin film with a thermoplastic resin film.

As a thermoplastic resin film, at least one of the film which consists of inorganic materials, such as glass fiber and aramid fiber, and the thermoplastic resin which does not contain an inorganic material can be employ | adopted with a thermoplastic resin. Similarly, as a thermosetting resin film, at least one of the film containing the said inorganic material with the thermosetting resin, and the film which consists of a thermosetting resin which does not contain an inorganic material can be employ | adopted.

As shown in FIG. 1, the insulating base material 20 which concerns on this embodiment is a thermosetting resin film 21a, a thermoplastic resin film 22a, and a thermosetting resin film 21b from the one surface 20a side in a thickness direction. 8 resin films are laminated | stacked in order of the thermoplastic resin film 22b, the thermosetting resin film 21c, the thermoplastic resin film 22c, the thermosetting resin film 21d, and the thermoplastic resin film 22d in order. That is, the thermoplastic resin film and the thermosetting resin film are laminated | stacked alternately, and the insulating base material 20 is comprised.

Moreover, the film which consists of thermosetting polyimide (PI) which does not contain inorganic materials, such as glass fiber, is employ | adopted as thermosetting resin films 21a-21d. On the other hand, 30 weight% of polyether ether ketones (PEEK) and polyetherimide (PEI) which do not contain the inorganic fillers for adjusting inorganic materials, such as glass fiber, a linear expansion coefficient, etc. as thermoplastic resin films 22a-22d. The resin film which consists of 70 weight% is employ | adopted.

The thermosetting resin film 21b corresponds to the board | substrate (1st film) in which the semiconductor chip 50 is mounted among the above-mentioned resin films, and the thermoplastic resin film 22b is a thermosetting resin film as the semiconductor chip 50 and a board | substrate ( It corresponds to the 2nd film sealing between 21b).

The conductor pattern 30 is formed by patterning the conductor foil, and is used as a wiring portion for electrically connecting the semiconductor chip 50 with the outside. Furthermore, not only the electrical wiring part but also the heat dissipation wiring part for radiating heat by the operation | movement of the element comprised in the semiconductor chip 50 to the outside can also be used.

On the other hand, in the resin film, the interlayer connecting portion 40 is formed by filling a via hole (through hole) provided along the thickness direction and sintering the conductive particles in the conductive paste by pressing and heating. This interlayer connection part 40 corresponds to the sintered compact as described in a claim. The interlayer connecting portion 40 is also used as a wiring portion for electrically connecting the semiconductor chip 50 to the outside together with the conductor pattern 30. Moreover, it can also be used as said heat radiation wiring part.

In the present embodiment, the conductor pattern 30 and the interlayer connecting portion 40 electrically connect the electrodes 51a (AuAl alloy layer 521), 51b of the semiconductor chip 50, and the external connection electrode 35 to each other. The wiring part is comprised. In addition, the conductor pattern 30 and the interlayer connecting portion 40 constituting the wiring portion may be formed by a separate conductor pattern 30 and the interlayer connecting portion 40 and the dummy electrode 51c and the heat dissipation member 60 of the semiconductor chip 50. The heat radiation wiring part which thermally connects () is comprised. In addition, the electrode 51a corresponds to the 1st electrode described in the claim, and the electrodes 51b and 51c correspond to the 2nd electrode described in the claim. In addition, although the electrode 51a is demonstrated in detail later, it is an electrode which consists of Al type material provided in the semiconductor chip 50 before a pressurization and a heating process. However, after the pressing and heating step, in the thickness direction of the portion facing the connecting portion 52 of the electrode 51a, all Al constituting the electrode 51a is AuAl alloyed and mainly contains Au ₄ Al alloy. An alloy layer 521 is provided (see FIG. 7). In other words, immediately below the connecting portion 52 is an AuAl alloy layer 521. In other words, the portion sandwiched by the semiconductor chip 50 and the connecting portion 52 is the AuAl alloy layer 521 containing no Al constituting the electrode 51a. At least the AuAl alloy layer 521 may be all in the thickness direction of the portion sandwiched by the semiconductor chip 50 and the connecting portion 52, that is, the portion facing the connecting portion 52 of the electrode 51a. However, as shown in FIG. 7, Al which comprises the electrode 51a remains in the site | part covered with the insulating film 53 which consists of SiN etc., for example.

Specifically, the wiring portion is formed by patterning the copper (Cu) foil with the conductor pattern 30. As the conductor pattern 30, the pad 31 corresponding to the electrode 51a of the semiconductor chip 50, the pad 32 corresponding to the electrode 51b, and the pad corresponding to the dummy electrode 51c similarly ( 33), the horizontal wiring portion 34 extending in the vertical direction. Furthermore, the external connection electrode 35 used for connection with an external device is also included as a part of the conductor pattern 30.

Each of the pads 31 to 33 is provided at a pitch that matches the pitch of the corresponding electrode 51 of the semiconductor chip 50. Although not shown, in this embodiment, the electrodes 51a are arranged in a rectangular annular line with one side of ten, and the pads 31 corresponding to the electrodes 51a also have a plurality of pads corresponding to the arrangement of the electrodes 51a. As shown in FIG. 4, 31 is provided in a rectangular annular shape. As shown in FIG. 1, each pad 31 is drawn out (rewired) to the outside or inside of the rectangular annular ring (the outside is illustrated in FIG. 1) by the horizontal wiring part 34 provided on the same layer. It is connected with the connection part 40. In addition, in FIG. 4, the horizontal wiring part 34 is abbreviate | omitted and shown for convenience.

In addition, in this embodiment, the interlayer connection part 40 consists of Ag-Sn alloy. The interlayer connecting portion 40 includes an interlayer connecting portion 41 constituting the vertical wiring portion of the wiring portion, and an interlayer connecting portion 42 for thermally connecting the dummy electrode 51c and the heat dissipation member 60.

And the wiring part is comprised including the interlayer connection part 41, the horizontal wiring part 34, and pads 31 and 32. As shown in FIG. Moreover, the heat dissipation wiring part is comprised including the interlayer connection part 42 and the pad 33. As shown in FIG.

At the interface between the conductor pattern 30 made of Cu and the interlayer connecting portion 40 made of Ag-Sn alloy, a metal diffusion layer (Cu-Sn alloy layer) in which Cu and Sn are mutually diffused is formed, whereby a conductor pattern ( The connection reliability between 30) and the interlayer connection part 40 is improved.

Moreover, the wiring 31 which is provided on the pad 31 as the conductor pattern 30 which consists of Cu, and the electrode 51a of the semiconductor chip 50, consists of gold (Au), and electrically connects the semiconductor chip 50 and the exterior. A CuAu alloy layer 522 (preferably comprising a CuAu ₃ alloy) is formed at the interface of the connection portion 52 used as a negative electrode, which is a metal diffusion layer formed by mutual diffusion of Cu and Au (see FIG. 7). The connection reliability of the pad 31 and the connection part 52 is improved.

Moreover, in this embodiment, the external connection electrode 35 is formed in the inner surface of the thermosetting resin film 21a which forms the surface layer of the one surface 20a side of the insulating base material 20 as the conductor pattern 30. As shown in FIG.

The semiconductor chip 50 is an IC chip (bare chip) in which elements such as transistors, diodes, resistors, and capacitors are integrated on a semiconductor substrate such as silicon to form a circuit (large scale integrated circuit). The electrode 51 is formed in the surface of this semiconductor chip 50 for the connection with the exterior, and this electrode 51 contains the electrode with which the said wiring part is connected at least. In addition, the semiconductor chip 50 is sealed by the insulating base material 20 mentioned above.

In this embodiment, as shown in FIG. 1, the AuAl alloy layer 521 and the electrode 51b electrically connected with the said circuit, and the dummy electrode which are not connected to the said circuit and do not provide an electrical connection function ( 51c) is formed.

One surface side of the semiconductor chip 50 is made of Au-Al alloy (mainly Au ₄ Al alloy) by Al phase diffusion of Al constituting the connecting portion 52 and Al of the electrode 51a of the semiconductor chip 50, A plurality of AuAl alloy layers 521 which do not contain (Al) as a metal single body are formed. That is, the AuAl alloy layer 521 is formed by alloying the electrode 51a of the semiconductor chip 50 before the pressing and heating step, and corresponds to the electrode (first electrode) of the semiconductor chip 50 after the pressing and heating step. will be. Therefore, the connection part 52 which consists of Au is connected to this AuAl alloy layer 521, respectively. The AuAl alloy layer 521 is an electrode 51a composed of an Al-based material that does not contain Au until the pressurization and heating step described later, and all Al is caused by solid phase diffusion of Au to Al in the pressurization and heating process. In combination with Au, it does not contain Al as a single metal. The element constituting the connecting portion 52 (the stud bump 52a before the pressing and heating step) (Au here) employs a melting point higher than the melting point of the thermoplastic resin.

If Al remains alone in the AuAl alloy layer 521 on the joint surface (interface) under the connecting portion 52 (that is, at the interface between the semiconductor chip 50 and the stud bump 52a (the connecting portion 52)), If Al of the electrode 51a is left alone, Au in the connection portion 52 is solid-phase diffused in Al of the electrode 51a to produce Au ₅ Al ₂ . The growth rate of Au ₅ Al ₂ is much faster than that of Au ₄ Al. Therefore, Au diffusion is not completed when Au ₅ Al ₂ is generated, and thus, between the semiconductor chip 50 and the junction 52 (for example, For example, a Kerkendal void is generated between Au ₅ Al ₂ and Au ₄ Al (void B1 in FIG. 12). In addition, cracks occur based on the Kirkendal void.

In contrast, in the present embodiment, the AuAl alloy layer 521 does not contain Al alone, but mainly contains Au ₄ Al alloy which is the final product of the Au-Al alloy. Therefore, even in a high-temperature use environment, it is possible to suppress the occurrence of curkendal voids and even cracks. Therefore, the semiconductor chip embedded wiring board 10 manufactured by the manufacturing method of this invention is arrange | positioned at the engine room of a vehicle, etc., and is most suitable for the electronic device etc. which use environment becomes high temperature.

The pitch (interval) between the electrodes 51a (AuAl alloy layer 521) is narrower than the pitches of the electrodes 51b and 51c formed on the surface on the opposite side of the semiconductor chip 50. As shown in FIG. Specifically, it is set to several tens of micrometer pitch (for example, 60 micrometer pitch).

On the other hand, the electrode 51b and the dummy electrode 51c made of Ni-based material are formed on the surface opposite to the electrode 51a forming surface of the semiconductor chip 50, respectively. The interlayer connection parts 41 and 42 are connected to these electrodes 51b and 51c as connection parts with the corresponding pads 32 and 33, respectively. At the interface between the electrodes 51b and 51c made of Ni and the interlayer connecting portions 41 and 42 made of Ag-Sn alloy, a metal diffusion layer (Ni-Sn alloy layer) in which Sn and Ni are mutually diffused is formed. The connection reliability of the conductor pattern 30 and the interlayer connection part 40 is improved. In addition, the electrodes 51b and 51c are formed in the pitch of 100 micrometers, for example. In addition, at least one element (here, Sn) constituting the interlayer connecting portions 41 and 42 electrically connected to the electrodes 51b and 51c has a melting point at which the glass transition point of the thermoplastic resin (in other words, the thermoplastic resin softens). Softening point). That is, the metal diffusion layer is formed by the liquid phase diffusion of the electrodes 51b and 51c and the interlayer connecting portions 41 and 42 in the pressurization and heating step described later.

Thus, the semiconductor chip 50 has the electrodes 51a and 51b which provide an electrical connection function on both surfaces, and also has the dummy electrode 51c which does not provide an electrical connection function. The reason why the electrodes 51a and 51b are provided on both surfaces is that the device includes a device in which current flows in the thickness direction, for example, a vertical MOSFET, an IGBT, a resistor, and the like.

The heat dissipation member 60 is made of a metal material such as Cu, and is for dissipating heat to the outside by the operation of the element formed in the semiconductor chip 50. As such a heat radiating member 60, what is called a heat sink, a heat radiating fin, etc. can be employ | adopted.

In the present embodiment, a flat heat dissipation member 60 made of Cu and having a size and a shape substantially coincident with one surface 20b of the insulating base 20 is employed. The heat radiation member 60 is fixed to one surface 20b of the insulating base 20 by bringing the thermoplastic resin film 22d into close contact with the heat dissipation member 60.

In addition, one end of the interlayer connecting portion 42 formed in the thermoplastic resin film 22d is connected to the heat dissipation member 60. In this embodiment, a metal diffusion layer (Cu-Sn alloy layer) in which Cu and Sn diffuse into each other is formed at an interface between the heat dissipation member 60 made of Cu and the interlayer connecting portion 42 made of Ag-Sn alloy. Therefore, the connection reliability of the interlayer connection part 42 (heat radiation wiring part) and the heat radiation member 60 is improved.

In the present embodiment, heat generated in the semiconductor chip 50 is transferred from the dummy electrode 51c to the heat dissipation member 60 through the heat dissipation wiring portion formed of the interlayer connection portion 42 and the pad 33. For this reason, heat dissipation is improved.

Further, a conductive member such as a plating film is disposed on one surface 20a side of the insulating base 20 in a hole formed from the one surface 20a side with the external connection electrode 35 as the bottom surface, and the solder is placed on the conductive member. The ball 70 is formed.

As described above, in the present embodiment, the heat dissipation member 60 is provided on one surface 20b side of the insulating base 20 while the semiconductor chips 50 have electrodes 51a and 51b providing electrical connection functions on both surfaces. Then, the external connection electrode 35 is provided only on one surface 20a side of the insulating base 20. That is, while the semiconductor chip 50 has a double-sided electrode structure, the wiring board 10 has a single-sided electrode structure.

Next, the manufacturing method of the above-mentioned wiring board (semiconductor device) 10 is demonstrated. In addition, in the parenthesis after the code | symbol 40a which shows an electrically conductive paste, the code | symbol of the corresponding interlayer connection part is described.

First, in order to form the wiring board 10 by pressurizing and heating a laminated body, the element which comprises a laminated body is prepared. A substrate (hereinafter referred to as a semiconductor unit 80) on which the semiconductor chip 50 is mounted and a plurality of resin films laminated on the semiconductor unit 80 are prepared.

In this embodiment, as above-mentioned, the film which consists of thermosetting polyimide (PI) which does not contain inorganic materials, such as glass fiber, is employ | adopted as thermosetting resin films 21a-21d. In this embodiment, as an example, the thickness of all the resin films 21a-21d is made the same (for example, 50 micrometers).

On the other hand, 30 weight% of polyether ether ketones (PEEK) and polyetherimide (PEI) which do not contain the inorganic fillers for adjusting inorganic materials, such as glass fiber, a linear expansion coefficient, etc. as thermoplastic resin films 22a-22d. A resin film made of 70% by weight is employed. In this embodiment, as an example, the resin films 22a, 22c, and 22d are the same thickness (for example, 80 micrometers), and the thermoplastic resin film 22b as a 2nd film is the said resin films 22a, 22c, and 22d. ) To a thickness thinner (for example, 50 µm).

In this preparatory step, the conductor pattern 30 is formed on the resin film constituting the insulating base 20 before the batch lamination, as known in the batch lamination method known as PALAP, or the sintering is used as the interlayer connecting portion 40. The conductive paste 40a is filled in the via hole. The arrangement of the via holes filled with the conductor pattern 30 and the conductive paste 40a is appropriately determined in accordance with the wiring portion or the heat dissipation wiring portion.

The conductor pattern 30 can be formed by patterning the conductor foil adhering to the surface of the resin film. As several resin films which comprise the insulating base material 20, the resin film which has the conductor pattern 30 should just be included, for example, the structure in which all the resin films have the conductor pattern 30, or some resin film The structure which does not have the conductor pattern 30 can also be employ | adopted. In addition, as a resin film which has the conductor pattern 30, either the resin film which has the conductor pattern 30 only in one side, and the resin film which has the conductor pattern 30 in both surfaces in a lamination direction can be employ | adopted. .

On the other hand, the electrically conductive paste 40a can be obtained by adding ethylcellulose resin, an acrylic resin, etc. to electroconductive particle for the provision of shape retention, and kneading in the state which added the organic solvent, such as terpineol. A via hole penetrating the resin film is formed by a carbon dioxide laser or the like, and the conductive paste 40a is filled into the via hole by screen printing or the like. The via hole may be formed with the conductor pattern 30 as the bottom surface, or the via hole may be formed at a position where the conductor pattern 30 is not present.

When the via hole is formed on the conductive pattern 30, the conductive pattern 40 may be at the bottom so that the conductive paste 40a may be contained in the via hole. On the other hand, in the case where the via hole is formed at a resin film not having the conductor pattern 30 or at a position different from the formation position of the conductor pattern 30 while having the conductor pattern 30, the conductive paste is formed in the via hole without the bottom. In order to contain 40a, the electrically conductive paste 40a of patent application 2008-296074 by this applicant is used. In addition, what is necessary is just to employ | adopt the apparatus (method) of patent application 2009-75034 by this applicant as an apparatus (method) to fill this electrically conductive paste 40a.

This conductive paste 40a decomposes or volatilizes with respect to electroconductive particle at the temperature lower than the sintering temperature of electroconductive particle, and becomes low melting | fusing point at the temperature lower than this temperature, higher than room temperature, and becomes a solid state at room temperature Room temperature solid resin is added. As the low melting room temperature solid resin, for example, paraffin is used. According to this, a low melting room temperature solid resin melt | dissolves into a paste form by heating at the time of filling, and a low melting room temperature solid resin solidifies in cooling after filling, and the electrically conductive paste 40a becomes hard and can hold | maintain in a via hole. have. In addition, when filling, one end of the via hole may be closed by a flat member.

First, the process of preparing the six resin films 21a, 21c, 21d, 22a, 22c, 22d laminated | stacked on the semiconductor unit 80 is demonstrated.

In this embodiment, as shown in FIG. 2, among the six resin films 21a, 21c, 21d, 22a, 22c, and 22d, only the thermosetting resin films 21a, 21c, and 21d are copper foils (for example, A film with a thickness of 18 μm) was prepared, and copper foil was patterned to form conductor patterns 30, respectively. Moreover, also about the remaining two resin films 21b and 22b which comprise the semiconductor unit 80, only the thermosetting resin film 21b prepares the film with copper foil (18 micrometers in thickness) on one side, and this copper foil Is patterned to form a conductor pattern 30.

That is, the thermosetting resin films 21a-21d are made into the structure which has the conductor pattern 30 in single side, and the thermoplastic resin films 22a-22d do not have the conductor pattern 30 in it.

Moreover, in the six resin films 21a, 21c, 21d, 22a, 22c, and 22d, the external connection electrode 35 is provided as the conductor pattern 30 on one side (inner surface in laminated state), and the insulating base material 20 is carried out. Via holes (not shown) are formed in each of the five resin films 21c, 21d, 22a, 22c, and 22d except for the thermosetting resin film 21a constituting the surface layer on one surface 20a side of the film. The conductive paste 40a is filled. After the filling, the solvent is volatilized by a drying step.

In this embodiment, since the conductor pattern 30 is formed only in the thermosetting resin films 21a, 21c, and 21d, about the thermoplastic resin films 22a, 22c, and 22d which do not form the conductor pattern 30, it is an electroconductive particle. The electrically conductive paste 40a which contains Ag particle | grains and Sn particle | grains at a predetermined ratio, and which added low melting-point room temperature solid resins, such as paraffin, is used as mentioned above.

For the thermosetting resin films 21a, 21c, and 21d, a conductive paste 40a such as the thermoplastic resin films 22a, 22c, and 22d may be used, and Ag particles and Sn particles are included as conductive particles in a predetermined ratio. You may employ | adopt the electrically conductive paste 40a which does not contain the low melting-point room temperature solid resin.

In addition, in this preparatory process, in order for a laminated body to have the cavity which accommodates the semiconductor chip 50, the cavity part is previously formed in a part of several sheets of resin film. In this embodiment, the cavity 23 for accommodating the semiconductor chip 50 is formed in the thermosetting resin film 21c. For this reason, the thermosetting resin film 21c which has the cavity part 23 shows a rectangular frame shape.

The cavity 23 can be formed by mechanical processing with a punch, a drill, or the like, and is irradiated with a laser beam, and is formed with a predetermined margin with respect to the buildup of the semiconductor chip 50. As formation timing of the cavity part 23, either before and after formation of the conductor pattern 30 and the interlayer connection part 40 may be sufficient.

Moreover, the formation process (pre-process) of the semiconductor unit 80 is performed in parallel with the preparation process of said resin film 21a, 21c, 21d, 22a, 22c, 22d.

First, the resin film which comprises the at least 1st film and comprises the board | substrate for mounting the semiconductor chip 50, and the 2nd film which seals between the board | substrate and the semiconductor chip 50 are prepared.

In this embodiment, as shown to Fig.3 (a), the thermosetting resin film 21b as a 1st film which comprises a board | substrate and the thermoplastic resin film 22b as a 2nd film are prepared. About the thermosetting resin film 21b, the thing with copper foil adhered on one side is prepared, this copper foil is patterned, and the conductor pattern 30 is formed. At this time, the pad 31 is also formed as the conductor pattern 30.

Subsequently, the thermoplastic resin film 22b is attached to the pad formation surface of a board | substrate so that the pad 31 may be covered by heating and pressing.

In this embodiment, as shown in FIG.3 (b) and FIG.4, the thermoplastic resin film 22b is thermocompression-bonded to the pad formation surface of the thermosetting resin film 21b as a board | substrate so that the pad 31 may be covered. 4 shows the mounting region 24 of the semiconductor chip 50.

Specifically, the thermoplastic softened by pressing on the thermosetting resin film 21b side while heating so that the temperature of the thermoplastic resin film 22b becomes more than the glass transition point and below the melting point of the thermoplastic resin which comprises the said film 22b. The resin is brought into close contact with the land forming surface of the thermosetting resin film 21b and the surface of the conductor pattern 30.

After the thermoplastic resin film 22b is thermocompression-bonded to the thermosetting resin film 21b, via holes are formed on the resin films 21b and 22b with the bottom surface of the conductor pattern 30, and the via holes are shown in Fig. 3. As shown in (b), the conductive paste 40a is filled. In either case, since the conductive pattern 30 is the bottom surface, a conductive paste containing no low melting point room temperature solid resin may be employed as the conductive paste 40a, and a conductive paste containing low melting point room temperature solid resin is employed. You may also

Next, the semiconductor chip 50 prepared separately is flip-chip mounted on a board | substrate.

The stud bump 52a is formed in the semiconductor chip 50 on the electrode 51a of the mounting surface with respect to a board | substrate. In the present embodiment, a stud bump 52a (rivet-shaped bump) made of Au is formed on a electrode 51a made of Al-based material, for example, by a known method using a wire. In this step, as shown in FIG. 8, Al of the electrode 51a remains between the semiconductor chip 50 and the stud bumps 52a.

And as shown in FIG.3 (c), the semiconductor chip 50 is pressurized toward the board | substrate, heating from the back surface side of a board | substrate mounting surface, for example by the heat-heating crimping tool 100 of a pulse heat system. At this time, it presses to the thermosetting resin film 21b side, heating at the temperature more than melting | fusing point (PEEK: PEI = 30: 70 to 330 degreeC) of the thermoplastic resin which comprises the thermoplastic resin film 22b.

When the heat from the thermocompression tool 100 is transmitted to the semiconductor chip 50 and the tip temperature of the stud bumps 52a becomes equal to or higher than the melting point of the thermoplastic resin constituting the thermoplastic resin film 22b, the stud bumps 52a The part of the thermoplastic resin film 22b which touches melts. Therefore, while melting the thermoplastic resin film 22b, the stud bumps 52a can be pushed into the thermoplastic resin film 22b and brought into contact with the corresponding pads 31. Thereby, as shown in FIG.3 (d), the stud bump 52a and the pad 31 can be brought into a press contact state. In this step, as shown in FIG. 9, Al of the electrode 51a remains between the semiconductor chip 50 and the stud bumps 52a.

The molten and softened thermoplastic resin flows under pressure, and the substrate mounting surface of the semiconductor chip 50, the pad formation surface of the thermosetting resin film 21b, the conductor pattern 30, the electrode 51a, and the stud bump ( 52a). Therefore, as shown in FIG.3 (d), the thermoplastic resin film 22b can seal between the semiconductor chip 50 and the thermosetting resin film 21b (substrate). In this way, the semiconductor unit 80 is formed.

In this embodiment, the heating temperature at the time of flip chip mounting is set to 350 degreeC which is slightly higher than melting | fusing point, and the pressure which applies the load applied to one stud bump 52a about 20-50 gf is applied. Thereby, the stud bump 52a and the pad 31 can be brought into a press contact state in a short time.

In addition, if heating and pressurization are continued even after the pressure contact state, the Au constituting the stud bump 52a and the Cu constituting the pad 31 are diffused to each other (solid phase diffusion) to form a metal diffusion layer (Cu-Au alloy layer). Form. Further, Au constituting the stud bump 52a diffuses in solid phase with respect to Al contained in the electrode 51a to form a metal diffusion layer (Au-Al alloy layer). However, forming such a metal diffusion layer requires a long time as heating and pressing time as compared with forming the above-mentioned pressure welding state. If it takes a long time to mount one semiconductor chip 50 on a substrate, the formation time of the wiring board 10 in which the semiconductor chip 50 is embedded becomes long as a result, and the manufacturing cost also increases. In addition, unnecessary heat is applied to parts other than the electrical connection part of the electrode 51a, the stud bump 52a, and the pad 31 during that time. For this reason, in this mounting process, the connection state of the stud bump 52a and the pad 31 is kept in a press contact state.

In addition, in this embodiment, after attaching the thermoplastic resin film 22b to the thermosetting resin film 21b, the via hole was formed and the example which filled the electrically conductive paste 40a was shown. However, via holes may be formed in each of the resin films 21b and 22b in the state before adhesion, and the conductive paste 40a may be filled.

About the conductive paste 40a, when the semiconductor chip 50 is formed before heating and pressurization when flip-chip mounting to a board | substrate, or before the attachment of the thermoplastic resin film 22b, electroconductive particle by pressurization and heating at the time of attachment May be sintered to form the interlayer connecting portions 40 (41), or may not be sintered and may be in the state of the conductive paste 40 a at the time when the semiconductor unit 80 is formed. Moreover, you may make it the state which one part sintered. In this embodiment, the conductive paste 40a is formed in the state after flip chip mounting.

Next, the lamination process of forming a laminated body is performed. In this step, a plurality of resin films including a resin film having a conductive pattern 30 formed on the surface thereof and a resin film filled with a conductive paste 40a in a via hole are placed on at least one interval while the thermoplastic resin film is positioned at at least one interval. 50) is laminated so as to be adjacent to the electrode formation surface and the back surface of the electrode formation surface.

In this embodiment, as shown in FIG. 5, from the one end side in a lamination direction, the thermosetting resin film 21a, the thermoplastic resin film 22a, the thermosetting resin film 21b, the thermoplastic resin film 22b, and the thermosetting resin film The plurality of resin films 21a, 21c, 21d, 22a, 22c, 22d, and the semiconductor unit 80 in order of 21c, the thermoplastic resin film 22c, the thermosetting resin film 21d, and the thermoplastic resin film 22d. Laminated. As described above, in the present embodiment, the thermoplastic resin films 22a to 22d and the thermosetting resin films 21a to 21d are laminated alternately.

Furthermore, the heat radiating member 60 is laminated | stacked on the thermoplastic resin film 22d. In addition, in FIG. 5, the element which comprises a laminated body is shown by spaced apart for convenience.

In detail, the thermoplastic resin film 22a is laminated | stacked on the conductor pattern formation surface of the thermosetting resin film 21a, the semiconductor unit 80 is mounted on the thermoplastic resin film 22a, and the thermosetting resin film 21b is mounted. It laminates as a surface. It is on the thermoplastic resin film 22b in the semiconductor unit 80, and the thermosetting resin film 21c is laminated around the semiconductor chip 50, with the surface opposite to the conductor pattern formation surface as a mounting surface. In addition, the thermoplastic resin film 22c is laminated on the thermosetting resin film 21c and the semiconductor chip 50, and the thermosetting resin film 21d is placed on the thermoplastic resin film 22c with the conductor pattern forming surface as the mounting surface. Laminated. And the thermoplastic resin film 22d is laminated | stacked on the thermosetting resin film 21d, and the heat dissipation member 60 is laminated | stacked, and one laminated body is formed.

In this laminated body, the resin film adjacent to the semiconductor chip 50 turns into thermoplastic resin films 22b and 22c in a lamination direction. At least these resin films 22b and 22c complete the function of sealing the periphery of the semiconductor chip 50 in the pressing and heating step. In this embodiment, since the resin film surrounding the semiconductor chip 50 is a thermosetting resin film 21c in the vertical direction, the two resin films 22b and 22c seal the circumference of the semiconductor chip 50. To complete.

As described above, the thermoplastic resin films 22b and 22c sealing the semiconductor chip 50 not only contain inorganic materials such as glass fibers and aramid fibers in the thermoplastic resin film, but also inorganic materials for adjusting the linear expansion coefficient and melting point. It is preferable to employ | adopt what does not contain a filler (filler). By doing in this way, local stress in the semiconductor chip 50 can be suppressed in a pressurization and a heating process.

However, if the thermoplastic resin films 22b and 22c that do not contain an inorganic filler for adjusting the linear expansion coefficient or melting point are employed, the difference in the coefficient of linear expansion with the semiconductor chip 50 becomes larger as there is no inorganic filler, and the accompanying stress increases. I think. Therefore, for reducing the stress, a resin film having a low elastic modulus (for example, 10 GPa or less) may be employed as the thermoplastic resin films 22b and 22c.

Moreover, as thermoplastic resin films 22b and 22c which seal the semiconductor chip 50, it is preferable to employ | adopt that thickness is 5 micrometers or more. When the thickness is less than 5 µm, the stress of the resin films 22b and 22c increases in the pressurization and heating step, and may be peeled off from the surface of the semiconductor chip 50.

Subsequently, a pressurization / heating step of heating the laminate while pressing the laminate from above and below the lamination direction is performed using a vacuum heat press. In this step, the thermoplastic resin is softened to integrate the multiple resin films collectively, the semiconductor chip 50 is sealed, and the conductive particles in the conductive paste 40a are used as sintered bodies. To form a wiring portion having a.

In the pressurization and heating process, in order to integrate the resin film collectively into the insulating base 20 and to make the conductive particles in the conductive paste 40a into a sintered body, the glass transition point of the thermoplastic resin constituting the resin film is equal to or lower than the melting point. The temperature and the pressure of several MPa are maintained for a predetermined time. In this embodiment, the press temperature of 280 degreeC-330 degreeC and the pressure of 4-5 Mpa are maintained for 5 minutes or more (for example, 10 minutes).

First, the connection of a resin film part in a pressurization and a heating process is demonstrated.

The thermoplastic resin films 22a to 22d arranged at one sheet are softened by the above heating. At this time, since the pressure is applied, the softened thermoplastic resin films 22a to 22d are in close contact with the adjacent thermosetting resin films 21a to 21d. Thereby, the some resin film 21a-21d, 22a-22d is integrated together, and the insulating base material 20 is formed. At this time, since the thermoplastic resin film 22d adjacent to the heat dissipation member 60 is in close contact with each other, the heat dissipation member 60 is also integrated with the insulating base 20.

In addition, the thermoplastic resin films 22b and 22c adjacent to the semiconductor chip 50 flow under pressure, and are formed on the electrode 51a forming surface of the semiconductor chip 50 and the electrode 51b and 51c forming surfaces thereof. Close contact In addition, the gap between the side surface of the semiconductor chip 50 and the thermosetting resin film 21c is also entered, and the gap is filled with the side surface of the semiconductor chip 50. Therefore, the semiconductor chip 50 is sealed by thermoplastic resin (thermoplastic resin films 22b and 22c).

Next, the connection of the electrode 51 of the semiconductor chip 50, the conductor pattern 30, and the interlayer connection part 40 in a pressurization and a heating process is demonstrated.

By heating, Sn (melting point 232 占 폚) in the conductive paste 40a melts, and similarly diffuses into Ag particles in the conductive paste 40a to form an Ag-Sn alloy (melting point 480 占 폚). In addition, since pressure is applied to the conductive paste 40a, the interlayer connecting portions 40 (41, 42) made of an alloy integrated by sintering are formed in the via holes.

Molten Sn also diffuses with Cu which comprises the conductor pattern 30 (pads 31-33). As a result, a metal diffusion layer (Cu-Sn alloy layer) is formed at the interface between the interlayer connecting portion 40 and the conductor pattern 30.

The molten Sn also diffuses with Ni constituting the electrodes 51b and 51c of the semiconductor chip 50. As a result, a metal diffusion layer (Ni-Sn alloy layer) is formed at the interface between the interlayer connecting portion 40 and the electrodes 51b and 51c.

In addition, Au constituting the stud bump 52a is solid-phase diffused into Al of the electrode 51a of the semiconductor chip 50. Since the electrode 51a is a fine pitch electrode, the amount of Al in the electrode 51a is less than the amount of Au constituting the stud bump 52a, and all Al constituting the electrode 51a is consumed for alloying with Au. After the pressing and heating step, Al is not included as a single metal as described above. Further, after the pressing and heating electrodes (51a) (i.e., AuAl alloy layer 521) as the AuAl alloy, are that mainly include Au ₄ Al alloy. This AuAl alloy layer 521 is made of Au ₄ Al and Au ₅ Al ₂ , for example, as shown in FIG. 10.

Also, in the pressurization and heating step, even if Au ₅ Al ₂ is formed before the Au ₄ Al alloy is formed, the pressure is applied even if Au ₅ Al ₂ is generated. The production of can be suppressed. In addition, in FIG. 10, it is an example in the case where the film thickness of the electrode 51a is 1.0 micrometer.

In contrast, as a comparative example, a cross-sectional view of the portion of the AuAl alloy layer 521 in the semiconductor chip-embedded wiring board manufactured without pressure is shown in FIG. 12. As is also apparent from FIG. 12, when the semiconductor chip-embedded wiring board is manufactured under no pressure, voids B1 are formed.

In addition, Au constituting the stud bumps 52a and Cu constituting the conductor pattern 30 (the pad 31) are mutually diffused. Accordingly, as shown in Fig. 10, CuAu alloy layer 522 at the interface between the connecting portion 52 and the pad 31 of the stud bump origin (CuAu alloy ₃₎ is formed. A Cu-Au alloy can be produced if there is heating at about 250 ° C. or higher, and according to the pressure and heating conditions described above, a CuAu ₃ alloy can be formed.

The stud bump 52a is formed of an AuAl alloy layer 521 made of Au-Al alloy and a pad 31 having CuAu ₃ alloy at an interface by the remainder of Au consumed for solid phase diffusion bonding. It becomes the connection part 52 which electrically connects. Thus, in the pressurization and heating process, the connection state of the stud bump 52a and the pad 31 is made into the direct bonding state.

In addition, it is preferable that Cu constituting the pad 31 adopt a lower modulus material than Au of the connection portion 52 (the stud bump 52a). By doing in this way, the thermal stress based on the difference of the thermal expansion coefficient of the semiconductor chip 50 and the insulating base material 20 can be concentrated in the pad 31 which consists of Cu. As a result, as shown in FIG. 13, a crack is generated in the pad 31 so that the thermal stress applied to the semiconductor chip 50 can be alleviated. Therefore, as shown in FIG. 14, it can suppress that a crack generate | occur | produces in the semiconductor chip 50, and can suppress that the semiconductor chip 50 is destroyed.

As described above, as shown in FIG. 6, the semiconductor chip 50 is embedded in the insulating base 20, the semiconductor chip 50 is sealed by a thermoplastic resin, and the semiconductor chip 50 and the electrode 35 for external connection. ) Is electrically connected by the wiring portion, and a substrate in which the semiconductor chip 50 and the heat dissipation member 60 are thermally connected by the heat dissipation wiring portion can be obtained.

Then, a hole having the bottom surface of the electrode for external connection 35 is formed on the substrate from one surface 20a side of the insulating base 20, and a conductive member such as a plating film is disposed in the hole. By forming the solder balls 70 in the wiring board 10 shown in FIG. 1 can be obtained.

Next, the effect of the characteristic part in the wiring board 10 shown in the said embodiment and its manufacturing method is demonstrated.

In this embodiment, in forming the wiring board 10, while the thermoplastic resin films 22a-22d are located at least 1 sheet space | interval, the back surface of the electrode 51a formation surface and this electrode formation surface of the semiconductor chip 50 is carried out. Several resin films 21a-21d and 22a-22d are laminated | stacked so that it may adjoin, and it is set as a laminated body.

Therefore, by pressing and heating, several sheets of resin films 21a-21d and 22a-22d can be integrated together by using the thermoplastic resin which comprises thermoplastic resin films 22a-22d as an adhesive material. In addition, the semiconductor chip 50 can be sealed by the thermoplastic resin films 22b and 22c which are adjacent to the semiconductor chip 50 at least. Furthermore, the wiring part can be formed with the conductor pattern 30 using the electroconductive particle in the electrically conductive paste 40a as a sintered compact by the said pressurization and heating. For this reason, the manufacturing process of the wiring board 10 can be simplified.

In this embodiment, the CuAu alloy layer 522 is formed by solid phase diffusion of Cu constituting the pad 31 and Au constituting the stud bumps 52a by this pressing and heating step, and the electrode ( The AuAl alloy layer 521 made of Au-Al alloy, in which Al as a metallic element does not exist, is formed by solid phase diffusion of Al constituting Al of the 51a and the stud bumps 52a. That is, the electrode 51a is made of the AuAl alloy layer 521 in the thickness direction of the portion facing the connecting portion 52. For this reason, generation | occurrence | production of the kekendal void by the diffusion of Au can also be suppressed also in high temperature use environment. Further, the AuAl alloy layer 521 and the CuAu alloy layer 522 are formed in the same process (pressing and heating process), and the AuAl alloy layer 521 and the CuAu alloy layer 522 are the same process (pressing and heating). Process), and the manufacturing process can be simplified.

As mentioned above, according to this invention, the manufacturing process of a semiconductor chip internal wiring board can be simplified, and the manufacturing time can be shortened, improving the connection reliability of a semiconductor chip.

In the present embodiment, the CuAu alloy layer 522 is provided at the interface between the stud bump 52a and the pad 31, and at least a portion of the AuAl alloy layer is disposed between the semiconductor chip 50 and the stud bump 52a. By having 521, the connection reliability of the semiconductor chip embedded can be improved.

In addition, the thermoplastic resin film 22b is arrange | positioned between the semiconductor chip 50 and the board | substrate (thermosetting resin film 21b) before the lamination process of forming a laminated body, and pressurizing, heating at the temperature more than melting | fusing point of a thermoplastic resin. Therefore, while raising the temperature to the melting point or more of the thermoplastic resin, the thermoplastic resin can be made to have fluidity, and the thermoplastic resin positioned between the stud bump 52a and the pad 31 is moved by pressurization so that the stud bump ( The stud bump 52a and the pad 31 can be brought into pressure contact by directly contacting the pad 31 with the 52a).

At this time, the molten thermoplastic resin flows under pressure, and seals between the semiconductor chip 50 and the substrate (thermosetting resin film 21b), including the periphery of the connecting portion of the stud bump 52a and the pad 31. do. Therefore, electrical insulation between each connection part can be ensured. Moreover, the connection reliability in a connection part can be improved.

At the time when the stud bump 52a and the pad 31 are brought into a press contact state, the flip chip mounting process (heating and pressurization) is terminated, and the stud bump 52a and the pad are pressurized and heated in the pressurizing and heating process. Let (31) be a joining state. As described above, since the stud bump 52a (connecting portion 52) and the pad 31 are bonded to each other by using the heat and pressure of the pressurization and heating process, the electrodes 51a of the semiconductor chip 50 The electrical connection reliability of the pad 31 can be improved.

In the flip chip mounting step, the stud bumps 52a and the pads 31 are placed in a press-contact state, and the stud bumps 52a and the pads 31 are joined to each other by using heat and pressure in the pressurization / heating step. Therefore, in the flip chip process, the stud bump 52a and the pad 31 are brought into a bonded state, and the manufacturing time can be shortened as compared with the method of performing the pressurization / heating process thereafter.

In addition, if the stud bumps 52a are brought into contact with the pads 31 in a pressing and heating step without being brought into contact with the pads 31 before the lamination step, the softened thermoplastics are brought into a bonded state. Due to the buffering effect of the resin, the stud bumps 52a are difficult to be pushed into the thermoplastic resin film 22b as the second film. As a result, it is also conceivable that the thermoplastic resin remains between the stud bumps 52a and the pad 31.

In contrast, in the present embodiment, the stud bumps 52a and the pads 31 are press-contacted prior to the lamination step, so that the stud bumps 52a and the pads 31 are reliably secured by pressurization and heating of the pressurization and heating steps. It can be made into a joined state.

In addition, in this embodiment, the conductor pattern 30 is formed only in the thermosetting resin films 21a-21d, and the conductor pattern 30 is not formed in the thermoplastic resin films 22a-22d. Therefore, even if the thermoplastic resin softens by a pressurization / heating step or the like and flows under pressure, the conductor pattern 30 is fixed to the thermosetting resin films 21a to 21d, so that the displacement of the conductor pattern 30 can be suppressed. have. For this reason, it is most suitable for the wiring board 10 in which the semiconductor chip 50 corresponding to fine pitch is incorporated.

By the way, in the semiconductor chip 50 having the electrodes 51 on both sides, when the electrodes 51 are solid-diffused and bonded, the semiconductor chip 50 is in contact with the semiconductor chip 50 during the pressurization and heating process. The pressure (press pressure) applied is high. In particular, when the electrodes 51 provided on both surfaces are solid-diffused and bonded together, the pressure (press pressure) applied to the semiconductor chip 50 becomes further high. On the other hand, in this embodiment, the electrode 51a and the pad 31 are electrically connected by solid phase diffusion of Au in one surface side of the semiconductor chip 50, and melted in the surface side opposite to the semiconductor chip 50. The liquid phase diffusion of Sn electrically connects the electrodes 51b and 51c to the pads 32 and 33. Therefore, the pressure applied to the semiconductor chip 50 at the liquid phase side can be buffered. For this reason, it is possible to improve the reliability of the semiconductor chip 50 by reducing the pressure applied to the semiconductor chip 50 in the pressurizing / heating step while coping with fine pitch by using one side as solid phase diffusion using the stud bumps 52a.

In addition, in this embodiment, since the thermoplastic resin films 22b and 22c employ | adopt inorganic materials, such as glass fiber, and the resin film which does not contain an inorganic filler, it also applies to the semiconductor chip 50 by a pressurization and a heating process by this. The pressure can be reduced.

(Second Embodiment)

In the first embodiment, the thermoplastic resin film having the stud bumps 52a attached on the pad formation surface of the thermosetting resin film 21b when the semiconductor chip 50 is flip chip mounted on the thermosetting resin film 21b as a substrate. The example which pushed into 22b) and secured the contact state with the pad 31 was shown.

On the other hand, in this embodiment, as shown to FIG. 15 (a), (b), the thermoplastic hole provided with the through-hole 25 in the position corresponding to the pad 31 in the pad formation surface of the thermosetting resin film 21b. It is characterized in that the resin film 22b is attached so that the through hole 25 covers the pad 31.

In the example shown to FIG. 15 (a), (b), the through hole 25 is provided for each pad 31. As shown in FIG. According to this, since the thermoplastic resin film 22b is located between the stud bump 52a and each connection part of the pad 31, in a flip chip mounting process, the softened thermoplastic resin is easy to cover a connection part. That is, it is easy to ensure the electrical insulation between each connection part, even if the through hole 25 is provided, and it is easy to improve the connection reliability in a connection part.

In addition, when the electrode 51a of the semiconductor chip 50 is a fine pitch, the pad 31 also becomes a fine pitch. Therefore, it is difficult to form the through hole 25 smaller than the pad 31 (for example, 30 micrometers in diameter). However, unlike the via hole (through hole) for forming the interlayer connecting portion 40, the conductive hole 40a is not filled in the through hole 25, and the electrode 51a and pad of the semiconductor chip 50 are also filled. It does not prescribe the physique of the connection part 52 which electrically connects 31. Therefore, since the through hole 25 may be made larger than the pad 31, the through hole 25 has a higher degree of freedom in forming the through hole than the via hole, and can be provided for each pad 31.

The semiconductor chip 50 is flip-chip mounted on the thermosetting resin film 21b by being pressed while heating to a temperature higher than or equal to the glass transition point (in other words, the softening point at which the thermoplastic resin softens) of the thermoplastic resin constituting the thermoplastic resin film 22b. do. Thereby, while pressing the stud bump 52a of the semiconductor chip 50 to the corresponding pad 31 through the through-hole 25, the semiconductor chip 50 and the thermosetting resin film ( Seal between 21b).

Using such a method can achieve the same effect as the manufacturing method shown in 1st Embodiment.

Moreover, according to the manufacturing method shown in this embodiment, in forming the pressure contact state of the stud bump 52a and the pad 31, it is not necessary to melt the thermoplastic resin film 22b. What is necessary is just to be able to seal between the semiconductor chip 50 and the thermosetting resin film 21b with the thermoplastic resin softened by pressurizing by heating to the temperature more than the glass transition point of the thermoplastic resin which comprises the thermoplastic resin film 22b. In other words, what is necessary is just to be able to thermo-compress the semiconductor chip 50 to the thermoplastic resin film 22b. Since the through-hole 25 is provided in advance in the thermoplastic resin film 22b before flip chip mounting, compared with the method shown in 1st embodiment, a pressure contact state can be formed easily.

Therefore, if the calories are the same, the pressed structure of the stud bump 52a and the pad 31 and the sealing structure by the thermoplastic resin film 22b can be formed in a shorter time than the method shown in 1st Embodiment. That is, the heating and pressing time in the flip chip mounting process, and further, the manufacturing time of the wiring board 10 can be shortened.

In addition, if the heating and pressing time and pressurization conditions are the same, the pressure contact state of the stud bumps 52a and the pad 31 can be ensured with less heat than the method shown in the first embodiment.

In addition, the through-hole 25 may be formed before attaching the thermoplastic resin film 22b to the thermosetting resin film 21b, and may be formed after attaching. In this embodiment, after attaching, the through-hole 25 is formed in a position corresponding to the pad 31 in the thermoplastic resin film 22b by a carbon dioxide laser or the like. By adopting such a method, the through hole 25 can be formed with high positional accuracy.

On the other hand, in the case where the through holes 25 are formed by irradiation of laser light or the like before the application, when forming the thermoplastic resin film 22b, the through holes 25 in the resin film 22b are different from the formation positions of the through holes 25. It is good to pressurize while heating a position. Since a position different from the position at which the through hole 25 is formed is attached by heating and pressing, it is possible to prevent crushing (close) of the through hole 25. Therefore, when mounting the semiconductor chip 50 on a board | substrate, the stud bump 52a and the pad 31 can be brought into a press contact state for a short time.

In the present embodiment, an example in which the through holes 25 are provided for each pad 31 is shown. However, one through hole 25 may be provided for each of the plurality of pads 31. For example, in the example shown to Fig.16 (a), (b), the some pad 31 is arrange | positioned at ten by one side in a linear annular shape, and the through hole 25 is each side, ie, One through hole 25 is provided for the ten pads 31. That is, it is a through hole 25 long in one direction in the vertical direction.

According to this configuration, the through-holes (not pitches) between the pads 31 are compared with the configuration in which one through-hole 25 is provided for each of the pads 31 shown in FIGS. 15A and 15B. 25). That is, the freedom degree of formation of the through hole 25 is high, and it is suitable for the fine pitch.

As mentioned above, although preferred embodiment of this invention was described, this invention is not restrict | limited to the above-mentioned embodiment at all, It can be variously modified and implemented in the range which does not deviate from the summary of this invention.

In the above embodiment, an example in which the lamination step and the pressurization and heating step are adopted after the semiconductor unit 80 is formed is employed, but the present invention is not limited thereto. In the lamination step, the semiconductor chip 50, the first film (thermosetting resin film 21b) and the second film (thermoplastic resin film 22b) may be laminated in a separated state. That is, the semiconductor chip 50 and the 1st film (thermosetting resin film 21b) are separated in the direction which the stud bump 52a and the pad 31 face through the 2nd film (thermoplastic resin film 22b). It may be laminated in a state. That is, in the lamination process shown in FIG. 5, the thermosetting resin film 21b, the thermoplastic resin film 22b, and the semiconductor chip 50 are arrange | positioned (in this order from the lower surface side) in the space where the semiconductor unit 80 is arrange | positioned. You may do so. In the pressurizing and heating step, the stud bump 52a is pushed while melting the thermoplastic resin film 22b, so that the pad 31, the stud bump 52a, the electrode 51a, and the stud bump 52a are subjected to solid phase diffusion bonding. By bonding. By doing in this way, the process of forming the semiconductor unit 80 can be skipped and the manufacturing time of a semiconductor chip built-in wiring board can be shortened.

In addition, the structure of the several sheets of resin film which comprises the insulating base material 20 is not limited to the said example. The longevity of a resin film is not limited to the said example (eight pieces). The longevity which can contain the semiconductor chip 50 should just be sufficient.

The constituent material of the thermoplastic resin film is not limited to the above example. For example, even if it consists of PEEK / PEI, what is different from the said example may be employ | adopted. Moreover, you may employ | adopt constituent materials other than PEEK / PEI, for example, liquid crystal polymer (LCP). Moreover, you may employ | adopt FEP (tetrafluoroethylene hexafluoropropylene copolymer), PFA (tetrafluoroethylene perfluoroalkyl vinyl ether copolymer), PPS (polyphenylene sulfide resin), etc.

In order to suppress local stress application to the semiconductor chip 50 in the pressurization and heating process, as the thermoplastic resin films 22a to 22d, inorganic materials used for substrates such as glass fibers and aramid fibers, melting points and coefficients of linear expansion Although the example using the film which does not have the inorganic filler added for the adjustment of was shown, the thermoplastic resin films 22a-22d containing these can also be employ | adopted. However, as described above, for the thermoplastic resin films (two thermoplastic resin films 22b and 22c in the present embodiment) used to seal the semiconductor chip 50, a local stress application to the semiconductor chip 50 is applied. In order to suppress, it is preferable to use the film which does not have the inorganic filler used for adjustment of the inorganic material used for base materials, such as glass fiber and aramid fiber, melting | fusing point and a linear expansion coefficient.

The structural material of a thermosetting resin film is not limited to the said example, either. For example, the film containing the inorganic material used for base materials, such as glass fiber and aramid fiber, can also be employ | adopted. Moreover, thermosetting resins other than a thermosetting polyimide can also be employ | adopted.

In addition, as several resin films, it is good also as a structure which does not contain a thermosetting resin film but contains only a thermoplastic resin film. In addition, the thermoplastic resin film has a longer life than that of the thermosetting resin film, and may be a structure in which the thermoplastic resin film is partially continued in the laminated state.

In this embodiment, an example of the thermosetting resin film 21b as a 1st film was shown as a board | substrate with which the semiconductor chip 50 is flip-chip mounted. However, you may employ | adopt a thermoplastic resin film as a 1st film. Moreover, you may comprise a board | substrate using the several sheets of resin film containing a 1st film.

In this embodiment, in order to improve heat dissipation, the example which fixed the heat dissipation member 60 to the one surface 20b of the insulating base material 20 was shown. In addition, similarly, in order to improve heat dissipation, the dummy electrode 51c is provided in the semiconductor chip 50, and the heat dissipation wiring part (the pad 33 and the interlayer connection part 42) is connected to the dummy electrode 51c. Indicated. However, it is good also as a structure which does not have at least one. If the heat dissipation member 60 and the heat dissipation wiring portion have only one structure, the heat dissipation property can be improved as compared with the structure without any of the structures shown in FIG. 1.

In addition, although the heat radiating member 60 is provided in the whole surface of the one surface 20b of the insulating base material 20, you may make it the structure which the heat radiating member 60 was fixed to a part of one surface 20b, and of the insulating base material 20 The heat dissipation member 60 may be fixed to both surfaces 20a and 20b, respectively.

In this embodiment, the semiconductor chip 50 has the electrodes 51 on both surfaces, and the AuAl alloy layer 521, the electrode 51b, and the dummy as electrodes for providing an electrical connection function. The example containing the electrode 51c was shown. However, it is good also as a structure which does not have the dummy electrode 51c with a heat radiation wiring part. In addition, the semiconductor chip 50 may be configured to have an electrode 51 (AuAl alloy layer 521) on only one surface thereof. The electrode 51 may include at least the electrode 51a on which the stud bumps 52a are provided.

For example, the semiconductor chip 50 may have an AuAl alloy layer 521 serving as an electrode on one surface thereof and a dummy electrode 51c only on the opposite side thereof. Also in this case, as described above, if the electrical connection between the dummy electrode 51c and the pad 33 is a liquid phase diffusion, the pressure (press pressure) applied to the semiconductor chip 50 in the pressing and heating step can be suppressed. have.

In addition, as in the modification shown in FIG. 17, in the semiconductor chip embedded wiring board 10a, the semiconductor chip 50 has an electrode 51 (AuAl alloy layer 521) on one surface side, and an electrode ( It is good also as a structure which does not have 51). In this case, since the wiring portion and the heat dissipation wiring portion are not connected to the surface on which the electrode 51 is not provided, the thermoplastic resin film 22c softens in the pressing and heating step, so that the electrodes 51 are formed on both surfaces thereof. The pressure (press pressure) applied to the semiconductor chip 50 can be suppressed.

In addition, the thickness of the resin film and the thickness of the conductor pattern 30 are not limited to the said example. However, in the lamination direction, for the thermoplastic resin films 22b and 22c adjacent to the semiconductor chip 50 and sealing the semiconductor chip 50, it is preferable to adopt a thickness of 5 μm or more as described above. Do.

Claims (21)

As a manufacturing method of a semiconductor chip embedded wiring board which embeds the semiconductor chip which has the 1st electrode which consists of Al type material in one surface,
A plurality of resin films including a resin film having a conductive pattern made of Cu on the surface and a resin film filled with a conductive paste in a via hole, and a thermoplastic resin film containing a thermoplastic resin are positioned at at least one interval of the semiconductor chip. A lamination step of laminating the electrode forming surface and the back surface of the electrode forming surface to form a laminate;
The thermoplastic resin is softened by pressurizing from above and below the stacking direction while heating the laminate, and the resin films of the plurality of sheets are integrally integrated, the semiconductor chip is sealed, and the conductive particles in the conductive paste are used as sintered bodies. A pressing and heating step of forming a sintered body and a wiring portion having the conductor pattern,
In the lamination step, the first film comprising the semiconductor chip and the resin film provided with the stud bump made of Au in the first electrode and the pad is formed as part of the conductor pattern through the second film as the thermoplastic resin film. The stud bumps and the pads face each other,
In the pressurizing and heating step, a CuAu alloy layer, which is an alloy layer of Cu constituting the pad and Au constituting the stud bump, is formed by joining the pad, the stud bump, and the first electrode and the stud bump by solid phase diffusion bonding. And Al in the thickness direction of the portion facing the stud bump in the first electrode are all AuAl alloyed, so that all the first electrodes are made of AuAl alloy layer.
Method for manufacturing a semiconductor chip embedded wiring board.
The method of claim 1,
In the pressurizing and heating step, the AuAl alloy layer containing Au ₄ Al alloy is formed.
Method for manufacturing a semiconductor chip embedded wiring board.
The method of claim 1,
In the pressurization and heating step, the CuAu alloy layer containing the CuAu ₃ alloy is formed.
Method for manufacturing a semiconductor chip embedded wiring board.
The method according to any one of claims 1 to 3, wherein
As a previous step of the lamination step,
An attaching step of attaching the second film to the pad forming surface of the substrate so as to cover the pad by pressurizing while heating the substrate including the first film;
Pressing the stud bump while pressing while heating to a temperature equal to or higher than the melting point of the thermoplastic resin constituting the second film while pressing the melted second film to the corresponding pad, the molten second film to the And a flip chip mounting step of sealing between the semiconductor chip and the substrate.
Method for manufacturing a semiconductor chip embedded wiring board.
The method according to any one of claims 1 to 3, wherein
As a previous step of the lamination step,
Above the glass transition point of the thermoplastic resin which comprises the said 2nd film in the state which attached the said 2nd film provided with the through hole to the pad formation surface in the position corresponding to the said pad with respect to the board | substrate containing the said 1st film. And pressing the stud bumps to the corresponding pads through the through holes by pressing while heating to a temperature, and a flip chip mounting step of sealing between the semiconductor chip and the substrate with the softened second film. Characterized by
Method for manufacturing a semiconductor chip embedded wiring board.
The method of claim 5, wherein
The through holes are provided for each of the pads.
Method for manufacturing a semiconductor chip embedded wiring board.
The method of claim 5, wherein
Characterized in that one through hole is provided for each of the plurality of pads.
Method for manufacturing a semiconductor chip embedded wiring board.
The method according to claim 6,
As the flip chip mounting process,
And attaching the second film provided with the through hole to the pad forming surface of the substrate by pressing while heating a position different from the position where the through hole is formed.
Method for manufacturing a semiconductor chip embedded wiring board. The method according to claim 6,
As the flip chip mounting process,
Attaching the second film to the pad forming surface of the substrate so as to cover the pad by pressurizing while heating, and forming a through hole at a position corresponding to the pad in the second film. Characterized
Method for manufacturing a semiconductor chip embedded wiring board.
The method of claim 1,
In the lamination step, the semiconductor chip and the first film are laminated in a state in which the stud bump and the pad are separated from each other through the second film,
In the pressurizing and heating step, a stud bump is pushed while melting the second film to join the pad, the stud bump, the first electrode, and the stud bump by solid phase diffusion bonding.
Method for manufacturing a semiconductor chip embedded wiring board.
The method according to any one of claims 1 to 3, wherein
The semiconductor chip has a second electrode on a back surface of the electrode formation surface on which the first electrode is formed.
Method for manufacturing a semiconductor chip embedded wiring board.
The method of claim 11,
In the lamination step, a heat dissipation member made of a metal material is disposed on the surface layer in a direction facing the second electrode of the semiconductor chip in the lamination, and in the pressing and heating step, the heat dissipation member and the resin film A conductive paste filled in the via hole is bonded.
Method for manufacturing a semiconductor chip embedded wiring board.
delete The method according to any one of claims 1 to 3, wherein
The thermoplastic resin film for sealing the semiconductor chip does not include a filler
Method for manufacturing a semiconductor chip embedded wiring board.
An insulating substrate comprising at least a thermoplastic resin,
The semiconductor chip which has a 1st electrode on one surface, is embedded in the said insulating base material, and is sealed by the thermoplastic resin of this insulating base material, with several elements comprised,
It is provided in the said insulating base material, and is electrically connected with the 1st electrode of the said semiconductor chip, and connects the conductor pattern which consists of Cu, the interlayer connection part provided in the via hole, and the pad as a part of the said 1st electrode and the said conductor pattern. And a connecting portion comprising Au,
At the interface of the said connection part and the said pad, it has a CuAu alloy layer which is an alloy layer of Au which comprises the said connection part, and Cu which comprises the said pad,
The site | parts which oppose the said connection part in a said 1st electrode are all comprised from AuAl alloy layer in the thickness direction, It is characterized by the above-mentioned.
Semiconductor chip embedded wiring board.
The method of claim 15,
The first electrode is characterized in that it comprises an Au ₄ Al alloy
Semiconductor chip embedded wiring board.
17. The method of claim 16,
An interface between the connection portion and the pad includes a CuAu ₃ alloy as the CuAu alloy layer.
Semiconductor chip embedded wiring board.
The method according to any one of claims 15 to 17, wherein
The insulating substrate is laminated with a plurality of resin films such that the thermoplastic resin film containing the thermoplastic resin is positioned at least one sheet apart and adjacent to the positive electrode forming surface of the semiconductor chip, and is bonded to each other using the thermoplastic resin film as an adhesive layer. Characterized in that
Semiconductor chip embedded wiring board.
The method according to any one of claims 15 to 17, wherein
The semiconductor chip has a second electrode on a back surface of the electrode formation surface on which the first electrode is formed, and the second electrode is electrically connected to the interlayer connection portion.
Semiconductor chip embedded wiring board.
The method of claim 19,
A heat dissipation member made of a metal material is disposed on the surface layer facing the second electrode of the semiconductor chip in the insulating substrate, and the heat dissipation member is connected to the second electrode via the wiring portion.
Semiconductor chip embedded wiring board.
The method according to any one of claims 15 to 17, wherein
The thermoplastic resin for sealing the semiconductor chip does not include a filler
Semiconductor chip embedded wiring board.

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