JP5343932B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a semiconductor chip mounted by flip chip bonding, the semiconductor chip being encapsulated by a resin, and a heat radiation member of a silicone material thermally connected to the semiconductor chip, and to provide a manufacturing method of the semiconductor device in simple manufacturing steps while suppressing damage of the heat radiation member. <P>SOLUTION: The semiconductor device manufacturing method comprises the steps of disposing semiconductor chips 50 in holes, disposing a heat radiation member 60 as a surface layer, disposing a resin film having a conductive paste between the individual semiconductor chips 50 and the heat radiation member 60, and laminating a plurality of resin films, a plurality of semiconductor chips 50 and the heat radiation member 60 by disposing thermoplastic resin films 22a-22c at least every one sheet so as to touch both faces of the semiconductor chips 50 and one face of the heat radiation member 60. This multilayer is pressed and heated from upside and downside, and subsequently diced together with the heat radiation member into individual semiconductor devices. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

In the present invention, a semiconductor chip is flip-chip mounted on a wiring board, the semiconductor chip is resin-sealed, and a heat dissipation member made of a silicon-based material is thermally connected to a surface opposite to the flip chip mounting surface of the semiconductor chip. The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a plurality of semiconductor chips mounted on a wiring board are placed in a mold cavity of a molding apparatus, a molding resin is introduced into the mold cavity, batch sealing molding is performed, and individual packages ( A manufacturing method called a MAP (Mold Array Package) method for obtaining a semiconductor device is known.

  As such a MAP method, for example, in Patent Document 1, a semiconductor chip is flip-chip mounted on a wiring board, a semiconductor chip is resin-sealed, and a surface of the semiconductor chip opposite to the flip chip mounting surface is made of a silicon-based material. The manufacturing method of the semiconductor device in which the heat radiating member which becomes is connected thermally is described.

  In Patent Document 1, after a plurality of semiconductor chips are flip-chip mounted on a substrate (wiring substrate), the semiconductor chips are sealed with a mold resin. Next, the mold resin and the semiconductor chip are ground from the surface side of the mold resin, and a heat sink (heat radiating member) is bonded onto the ground surface of the mold resin and the semiconductor chip. Then, the wiring board, the mold resin, and the heat dissipation member are diced to be separated into individual semiconductor devices.

JP 2003-60117 A

  In the manufacturing method described in Patent Document 1, in order to thermally connect the semiconductor chip and the heat dissipating member, the semiconductor chip is first sealed with a mold resin, and then the mold resin is ground to the substrate in the semiconductor chip. The surface opposite to the mounting surface is exposed from the mold resin, and the heat radiating member is joined to the exposed surface. As described above, after the semiconductor chip is sealed with the mold resin, grinding is required, so that the manufacturing process is complicated.

  On the other hand, as a manufacturing method that does not require grinding, after flip chip mounting a plurality of semiconductor chips on a wiring board, one large heat radiating member is joined to the plurality of semiconductor chips, and then the heat radiating member and the wiring board A mold resin is injected into a region facing the semiconductor chip to seal the semiconductor chip. A method of dicing the wiring board, the mold resin, and the heat dissipation member into individual semiconductor devices (hereinafter referred to as a second manufacturing method) is also conceivable.

  By the way, if a heat radiating member made of a metal material is employed, burrs are likely to occur during dicing. When burrs are generated in this way, rework steps are required and defective products increase, resulting in an increase in manufacturing costs. On the other hand, if a heat dissipation member made of a silicon-based material is used, burrs can be reduced as compared with a metal material.

  However, in the case of the above-described second manufacturing method, the heat dissipation member is supported by the wiring board via the semiconductor chip in a state before the semiconductor chip is sealed with the mold resin. The part where the semiconductor chip does not exist becomes a cavity. As described above, since the hollow portion has no support, if a heat radiating member made of a silicon-based material is used, the heat radiating member may be damaged at the time of clamping the transfer mold.

  In addition, since one large heat radiating member is bonded to a plurality of semiconductor chips, the thickness variation of the semiconductor chip, the height variation of the flip chip mounting portion, the height variation of the bonding portion between the heat radiation member and the semiconductor chip As a result, variations are likely to occur in the in-plane position of the heat dissipating member based on the surface opposite to the semiconductor chip mounting surface of the wiring board (the surface on which the mold hits the heat dissipating member during transfer molding). Therefore, non-uniform stress acts on the heat radiating member when the transfer mold is clamped, and the heat radiating member may be damaged.

  In view of the above problems, the present invention is such that a semiconductor chip is flip-chip mounted on a wiring substrate, the semiconductor chip is resin-sealed, and a heat dissipation member made of a silicon-based material is heated on the surface opposite to the flip chip mounting surface of the semiconductor chip. An object of the present invention is to provide a semiconductor device connected in a simple manner with a simple manufacturing process while suppressing breakage of a heat dissipation member.

In order to achieve the above object, the invention described in claim 1
Manufacture of a semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring substrate, the semiconductor chip is resin-sealed, and a heat dissipation member made of a silicon-based material is thermally connected to the surface opposite to the flip chip mounting surface of the semiconductor chip A method,
A plurality including a resin film having a conductor pattern formed on the surface, a resin film filled with a conductive paste in a via hole, and a resin film having a plurality of holes formed corresponding to each of a plurality of semiconductor chips A preparation step of preparing a sheet of resin film;
A plurality of semiconductor chips are arranged in the holes and are located at the same position in the stacking direction, and one heat radiating member is a surface layer in the stacking direction while facing the plurality of semiconductor chips, and the flip chip mounting surface of each semiconductor chip is A thermoplastic resin film containing a thermoplastic resin and a resin film having a conductive paste for thermally connecting each semiconductor chip and the heat radiating member is located between the opposite surface and one heat radiating member. Are located at least every other sheet, and are adjacent to the flip chip mounting surface of the semiconductor chip, the surface opposite to the flip chip mounting surface, and the surface facing the semiconductor chip in the heat radiating member. Lamination process of laminating together with a plurality of semiconductor chips and one heat dissipating member facing the plurality of semiconductor chips to form a laminate ,
By heating the laminated body while pressing from above and below in the laminating direction, the thermoplastic resin is softened, a plurality of resin films are integrated together, a semiconductor chip is sealed, and a heat dissipation member is integrated, and conductive Conductive particles in the conductive paste as a sintered body, the wiring section having the sintered body and the conductor pattern, and the heat transfer having the sintered body and thermally connecting each semiconductor chip and the heat dissipation member A pressurizing / heating process for forming a path part;
And a dicing step of dicing an insulating base material formed by integrating a plurality of resin films and a heat radiating member into individual semiconductor devices.

  In the present invention, at least every other thermoplastic resin film is positioned adjacent to the flip chip mounting surface of the semiconductor chip, the surface opposite to the flip chip mounting surface, and the surface facing the semiconductor chip in the heat dissipation member. A plurality of resin films are laminated together with a plurality of semiconductor chips and one heat radiating member to form a laminate. Accordingly, when the thermoplastic resin of the thermoplastic resin film is softened by pressurization and heating, 1) a plurality of resin films are integrated together, and 2) a thermoplastic resin film adjacent to the semiconductor chip at least in the stacking direction. The semiconductor chip can be sealed by 3) and the heat dissipating member can be integrated with the resin film. Moreover, since the electroconductive particle in an electroconductive paste becomes a sintered compact by the said pressurization and heating, the heat-transfer wiring part and wiring part which thermally connect a semiconductor chip and a heat radiating member can also be formed. . Each semiconductor device can be obtained by dicing after sealing a plurality of semiconductor chips together.

  In addition, as a plurality of resin film, you may have a thermosetting resin film containing a thermosetting resin other than a thermoplastic resin film. In the pressurizing and heating process, the thermoplastic resin constituting the thermoplastic resin film is softened, and thereby the resin films are bonded and integrated, so that at least every other thermoplastic resin film is positioned as a laminate. That's fine.

  As described above, according to the present invention, the semiconductor chip is flip-chip mounted on the wiring board, the semiconductor chip is resin-sealed, and the heat dissipation member made of a silicon-based material is heated on the surface opposite to the flip chip mounting surface of the semiconductor chip. The semiconductor devices connected to each other can be formed without going through a grinding step after collective sealing as in the prior art. Therefore, the manufacturing process can be simplified.

  Moreover, in this invention, the laminated body which has a heat radiating member which consists of a silicon-type material in a surface layer is heated, pressing from the upper and lower sides of a lamination direction. That is, a heat radiating member made of a silicon material is pressurized. However, a resin film having a plurality of holes formed corresponding to each of the plurality of semiconductor chips is prepared, and a semiconductor chip is arranged in each hole of the resin film in the laminating step. Thus, in the state of the laminate, the semiconductor chip is surrounded by the resin film, and when the heat dissipation member made of a silicon-based material is pressurized, the heat dissipation member is supported by the entire portion of the laminate excluding the heat dissipation member. Can do. Therefore, compared with the manufacturing method which pressurizes the heat radiating member supported only by the semiconductor chip like the past, damage to the heat radiating member made of a silicon-based material can be suppressed.

  In the present invention, the resin film includes at least a thermoplastic resin film, and the thermoplastic resin film is located between the semiconductor chip and the heat dissipation member. Accordingly, due to variations in the thickness of the semiconductor chip, variations in the height of the flip chip mounting portion, etc., in one stacked body including a plurality of semiconductor chips and one heat dissipation member, Even if the distance between the surface and the surface opposite to the heat radiating member varies, the variation in stress within the heat radiating member surface can be reduced by softening and flowing the thermoplastic resin during the pressurizing and heating process. Can do. This also makes it possible to suppress damage to the heat radiating member made of a silicon-based material, as compared with the conventional manufacturing method.

  As described above, according to the present invention, the semiconductor chip is flip-chip mounted on the wiring board, the semiconductor chip is resin-sealed, and the heat radiating member made of a silicon-based material is heated on the surface opposite to the flip chip mounting surface of the semiconductor chip. Connected semiconductor devices can be provided by a simple manufacturing process while suppressing damage to the heat dissipation member.

  According to a second aspect of the present invention, in the stacking step, via holes are formed corresponding to each semiconductor chip between the opposite surface of the flip chip mounting surface of each semiconductor chip and one heat dissipation member, The via holes may be laminated so that one thermoplastic resin film filled with a conductive paste is located.

  According to this, since the one thermoplastic resin film is adjacent to the surface opposite to the flip chip mounting surface of the semiconductor chip, the semiconductor chip is sealed with the thermoplastic resin of the thermoplastic resin film. Can do. Further, since the one thermoplastic resin film is adjacent to the surface of the heat radiating member facing the semiconductor chip, the heat radiating member can be bonded and integrated by the thermoplastic resin of the thermoplastic resin film. Furthermore, only one resin film is disposed between the semiconductor chip and the heat dissipation member, and a sintered body (derived from the conductive paste) in the via hole formed in this resin film forms a heat transfer path portion. Therefore, the heat dissipation to the heat radiating member via the heat transfer path part can be improved.

It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the preparatory process of a resin film among the manufacturing processes of the semiconductor device shown in FIG. FIG. 2 is a cross-sectional view showing a step of flip-chip mounting a semiconductor chip on a substrate in the manufacturing process of the semiconductor device shown in FIG. 1. In the process shown in FIG. 3, it is a top view which shows the state which affixed the 2nd film on the pad formation surface of a board | substrate. It is sectional drawing which shows a lamination process among the manufacturing processes of the semiconductor device shown in FIG. It is sectional drawing which shows a pressurization / heating process among the manufacturing processes of the semiconductor device shown in FIG. FIG. 2 is a cross-sectional view showing a post-dicing step in the semiconductor device manufacturing process shown in FIG. 1. It is a figure which shows the state which affixed the 2nd film on the pad formation surface of a board | substrate in the process of flip-chip mounting a semiconductor chip to a board | substrate among the manufacturing processes which concern on 2nd Embodiment, (a) is a top view, (B) is sectional drawing which follows the VIIIB-VIIIB line | wire of (a). It is a figure which shows the modification of the state which affixed the 2nd film, (a) is a top view, (b) is sectional drawing which follows the IXB-IXB line | wire of (a). It is sectional drawing which shows the other modification of a semiconductor device.

  The present invention is a semiconductor device (semiconductor chip built-in wiring board) formed by a batch lamination method known as PALAP. Therefore, as long as there is no notice in particular, the basic configuration and manufacturing method of the semiconductor device can appropriately adopt the configuration related to PALAP that has been filed by the present applicant. PALAP is a registered trademark of Denso Corporation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, common or related elements are given the same reference numerals.

(First embodiment)
Hereinafter, the thickness direction of the insulating base material 20 (in other words, the lamination direction of the plurality of resin films) is simply referred to as the thickness direction, and the direction perpendicular to the thickness direction is simply referred to as the vertical direction. Further, unless otherwise specified, the thickness means a thickness along the thickness direction.

  A semiconductor device 10 (also referred to as a semiconductor chip built-in wiring substrate) shown in FIG. 1 includes, as basic components, an insulating base 20, a conductor pattern 30 and an interlayer connection 40 provided on the insulating base 20, an insulating base. 20 includes a semiconductor chip 50 and a heat dissipation member 60 embedded, that is, built in.

  The insulating base material 20 is made of an electrically insulating material, and holds the constituent elements other than the base material 20, in the example shown in FIG. 1, the conductor pattern 30, the interlayer connection portion 40, the semiconductor chip 50, and the heat dissipation member 60 in place. In addition to functioning as a base material, the semiconductor chip 50 is held and protected inside.

  The insulating substrate 20 mainly includes a resin and at least a thermoplastic resin as the resin, and a plurality of resin films including a thermoplastic resin film are laminated, and are bonded and integrated by pressing and heating. It becomes. The reason for including the thermoplastic resin is that, when forming the insulating base material 20 in a batch in the pressurizing / heating process described later, it is resistant to high temperatures and uses the softened thermoplastic resin as an adhesive and a sealing material. is there.

  For this reason, the plurality of resin films may include a thermoplastic resin film so as to be positioned at least every other sheet in a laminated state. For example, it is good also as a structure containing only a thermoplastic resin film, and good also as a structure containing a thermosetting resin film with a thermoplastic resin film.

  As the thermoplastic resin film, at least one of a film containing an inorganic material such as glass fiber and aramid fiber and a film made of a thermoplastic resin not containing an inorganic material can be employed together with the thermoplastic resin. Similarly, as the thermosetting resin film, at least one of a film containing the inorganic material and a film made of a thermosetting resin not containing the inorganic material can be employed together with the thermosetting resin.

  As shown in FIG. 1, the insulating base material 20 according to the present embodiment has a thermosetting resin film 21a, a thermoplastic resin film 22a, a thermosetting resin film 21b, and a thermoplastic resin from the one surface 20a side in the thickness direction. A total of six resin films are laminated in the order of the film 22b, the thermosetting resin film 21c, and the thermoplastic resin film 22c. That is, the insulating base material 20 is configured by alternately laminating thermoplastic resin films and thermosetting resin films.

  Moreover, the film which consists of thermosetting polyimide (PI) which does not contain inorganic materials, such as glass fiber, is employ | adopted as the thermosetting resin films 21a-21c. On the other hand, as the thermoplastic resin films 22a to 22c, 30% by weight of polyetheretherketone (PEEK) and polyetherimide (PEI) not containing inorganic materials such as glass fibers and inorganic fillers for adjusting the linear expansion coefficient, etc. A resin film composed of 70% by weight is employed.

  Among the resin films described above, the thermosetting resin film 21b corresponds to the substrate (first film) on which the semiconductor chip 50 is mounted, and the thermoplastic resin film 22b is the thermosetting resin as the semiconductor chip 50 and the substrate. It corresponds to a second film that seals between the film 21b.

  The conductor pattern 30 is formed by patterning a conductor foil, and is used as a wiring portion that electrically connects the semiconductor chip 50 and the outside. Furthermore, it can be used not only as an electrical wiring part but also as a heat transfer path part for radiating heat generated by the operation of the elements formed in the semiconductor chip 50 to the outside.

  On the other hand, the interlayer connection part 40 is a resin film in which via holes (through holes) provided along the thickness direction are filled with a conductive paste, and the conductive particles in the conductive paste are sintered by pressing and heating. It is made. The interlayer connection portion 40 corresponds to the sintered body described in the claims. The interlayer connection portion 40 is also used as a wiring portion that electrically connects the semiconductor chip 50 and the outside together with the conductor pattern 30. Moreover, it can also be used as the heat transfer path part.

  In the present embodiment, the conductor pattern 30 and the first interlayer connection portion 41 constitute a wiring portion that electrically connects the electrode 51 a of the semiconductor chip 50 and the external connection electrode 33. Further, a heat transfer path portion that thermally connects the dummy electrode 51b of the semiconductor chip 50 and the heat radiating member 60 is constituted by the second interlayer connection portion 42 different from the first interlayer connection portion 41 that constitutes the wiring portion. Has been.

  Specifically, the conductor pattern 30 is formed by patterning a copper (Cu) foil. The conductor pattern 30 includes a pad 31 corresponding to the electrode 51a of the semiconductor chip 50 and a horizontal wiring portion 32 extending in the vertical direction. Further, an external connection electrode 33 provided for connection with an external device is also included as a part of the conductor pattern 30.

  The pads 31 are provided at a pitch that matches the pitch of the electrodes 51 a of the semiconductor chip 50. Although not shown in the drawings, in this embodiment, the electrodes 51a are arranged in a rectangular ring with one side of nine, and the pads 31 corresponding to the electrodes 51a also include a plurality of pads 31 corresponding to the arrangement of the electrodes 51a. As shown in FIG. 4, it is provided in a rectangular ring shape. Then, as shown in FIG. 1, each pad 31 is drawn (rewired) to the outside or inside of the rectangular annular ring by the horizontal wiring portion 32 provided in the same layer, and connected to the interlayer connection portion 40. Has been. In FIG. 4, the horizontal wiring portion 32 is omitted for convenience.

  Moreover, in this embodiment, the interlayer connection part 40 consists of Ag-Sn alloy. As described above, as the interlayer connection portion 40, the second interlayer for thermally connecting the first interlayer connection portion 41 constituting the vertical wiring portion of the wiring portions, the dummy electrode 51b, and the heat dissipation member 60. Interlayer connection 42 is included.

  A metal diffusion layer (Cu—Sn alloy) in which Cu and Sn diffuse to each other at the interface between the conductor pattern 30 made of Cu and the interlayer connection portion 40 (first interlayer connection portion 41) made of Ag—Sn alloy. As a result, the connection reliability between the conductor pattern 30 and the interlayer connection 40 is improved.

Further, Cu and Au diffuse to each other at the interface between the pad 31 as the conductor pattern 30 made of Cu and the connection portion 52 made of gold (Au) provided on the electrode 51 a of the semiconductor chip 50. Thus, a metal diffusion layer (Cu—Au alloy layer including CuAu ₃ alloy) is formed, whereby the connection reliability between the pad 31 and the connection portion 52 is improved.

  In the present embodiment, the external connection electrode 33 is formed as the conductor pattern 30 on the inner surface of the thermosetting resin film 21 a that forms the surface layer on the one surface 20 a side of the insulating substrate 20.

  The semiconductor chip 50 is an IC chip (bare chip) in which a circuit (large scale integrated circuit) is configured by integrating elements such as transistors, diodes, resistors, and capacitors on a semiconductor substrate such as silicon. An electrode 51 is formed on the surface of the semiconductor chip 50 for connection to the outside. The electrode 51 includes at least an electrode to which the wiring portion is connected. Further, the semiconductor chip 50 is sealed by the insulating base material 20 described above.

  In the present embodiment, as shown in FIG. 1, an electrode 51a electrically connected to the circuit and a dummy electrode 51b that is not connected to the circuit and does not provide an electrical connection function are formed. .

A plurality of electrodes 51a are formed on one surface side of the semiconductor chip 50, and connection portions 52 made of Au are connected to the electrodes 51a. All the thickness direction of the portion facing the connecting portion 52 of the electrode 51a is made of Au-Al alloy (mainly _Au 4 Al alloy), and aluminum (Al) so as not included in the metal itself. In other words, all the thickness directions of the portion of the electrode 51a facing the connecting portion 52 are all the portions of the electrode 51a in the thickness direction immediately below (or immediately above) the connecting portion 52 (the interface with the connecting portion 52 and the interface). (All parts in the thickness direction from the interface). It can also be said that the electrode 51 a is a portion sandwiched between the semiconductor chip 50 and the connection portion 52. Hereinafter, the electrode 51a is indicated as a portion immediately below the connection portion 52 made of Au.

  Further, a portion of the electrode 51a that is not a region directly below the connection portion 52 (for example, a portion covered with a protective film) is configured to contain Al alone.

In the electrode 51a, if Al remains alone in a portion immediately below the connection portion 52 made of Au, the Au in the connection portion 52 adjacent to the Al in the electrode 51a is solid-phase diffused in a high temperature use environment, and Au ₅ Al ₂ is generated. The growth rate of this Au ₅ Al ₂ is much faster than that of Au ₄ Al. Therefore, the diffusion of Au is not in time for the generation of Au ₅ Al ₂ , and a Kirkendall void is formed at the interface between the connection portion 52 and the electrode 51a. Arise. In addition, cracks occur starting from Kirkendall void.

On the other hand, in the present embodiment, in the electrode 51a, the portion immediately below the connection portion 52 made of Au does not contain Al as a single metal, but mainly contains Au ₄ Al alloy which is the final product of Au—Al alloy. It is out. Therefore, it is possible to suppress the occurrence of Kirkendall voids, and hence cracks, even in a high temperature use environment.

  The pitch (interval) between the electrodes 51a is narrower than the pitch of the electrodes (dummy electrodes 51b) formed on the opposite surface of the semiconductor chip 50. Specifically, the pitch is several tens of μm (for example, 60 μm pitch).

  On the other hand, a dummy electrode 51b made of a Ni-based material is formed on the surface of the semiconductor chip 50 opposite to the surface on which the electrode 51a is formed. A second interlayer connection 42 is connected to the dummy electrode 51b. At the interface between the dummy electrode 51b made of Ni and the second interlayer connection portion 42 made of Ag—Sn alloy, a metal diffusion layer (Ni—Sn alloy layer) formed by mutually diffusing Sn and Ni is formed, Thereby, the connection reliability of the dummy electrode 51b and the 2nd interlayer connection part 42 (heat-transfer path | route part) is improved. The dummy electrodes 51b are formed with a pitch of, for example, a unit of 100 μm.

  As described above, the semiconductor chip 50 includes the electrode 51a that provides an electrical connection function on one surface, and also includes a dummy electrode 51b for heat dissipation.

  The heat radiating member 60 is made of a silicon-based material (silicon, silicon carbide, etc.), and radiates heat generated by the operation of the elements formed on the semiconductor chip 50 to the outside. As such a heat radiating member 60, what is called a heat sink, a heat radiating fin, etc. are employable.

  In the present embodiment, a flat plate-like heat radiating member 60 made of silicon, having a size and shape substantially coincident with the one surface 20b of the insulating base material 20 and arranged so as to cover the entire surface 20b is employed. . The heat radiating member 60 is fixed to the one surface 20b of the insulating base material 20 by the thermoplastic resin film 22c being in close contact with the heat radiating member 60. In other words, the heat radiating member 60 is exposed to the outside on the surface portion excluding the adhesive surface with the insulating base material 20.

  In addition, one end of a second interlayer connection portion 42 formed on the thermoplastic resin film 22c is connected to the heat dissipation member 60. Therefore, the heat generated in the semiconductor chip 50 is transmitted from the dummy electrode 51b to the heat radiating member 60 through the heat transfer path portion formed by the second interlayer connection portion 42 formed in the thermoplastic resin film 22c. . For this reason, the heat dissipation is improved.

  In addition, a conductive member such as a plating film is disposed on the one surface 20a side of the insulating base material 20 in a hole formed with the external connection electrode 33 as a bottom surface from the one surface 20a side, and a solder ball 70 is placed on the conductive member. Is formed.

  Thus, in the present embodiment, the semiconductor chip 50 embedded in the insulating base material 20 is electrically connected to the external connection electrode 33 (solder ball 70) provided on the one surface 20a side of the insulating base material 20. ing. Further, the semiconductor chip 50 is thermally connected to the heat radiating member 60 made of a silicon-based material fixed to the one surface 20 b side of the insulating base material 20 by the second interlayer connection portion 42.

  Next, a method for manufacturing the semiconductor device 10 will be described. In this manufacturing method, a MAP (Mold Array Package) method, that is, a method in which a plurality of semiconductor chips 50 are collectively sealed and then diced to obtain individual semiconductor devices is applied. In addition, the code | symbol of the corresponding interlayer connection part is described in the parenthesis after the code | symbol 40a which shows an electrically conductive paste.

  First, in order to form the semiconductor device 10 by pressurizing and heating the stacked body, elements constituting the stacked body are prepared. That is, a plurality of resin films, a plurality of semiconductor chips 50, and a single heat dissipation member 60 are prepared.

  In the present embodiment, a substrate on which the semiconductor chip 50 is mounted (hereinafter referred to as a semiconductor unit 80), a plurality of resin films laminated on the semiconductor unit 80, and a heat dissipation member 60 are prepared. In addition, as the plurality of resin films, those having substantially the same outer contour as each other are adopted, and as the heat radiating member 60, those having substantially the same outer contour as the resin film are adopted.

  Moreover, the film which consists of thermosetting polyimide (PI) which does not contain inorganic materials, such as glass fiber, is employ | adopted as thermosetting resin films 21a-21c among several resin films. In the present embodiment, as an example, all the resin films 21a to 21d have the same thickness (for example, 50 μm).

  On the other hand, as the thermoplastic resin films 22a to 22c, 30% by weight of polyetheretherketone (PEEK) and polyetherimide (PEI) not containing inorganic materials such as glass fibers and inorganic fillers for adjusting the linear expansion coefficient, etc. A resin film composed of 70% by weight is employed. In this embodiment, as an example, the resin films 22a and 22c have the same thickness (for example, 80 μm), and the thermoplastic resin film 22b as the second film is thinner than the resin films 22a and 22c (for example, 50 μm). ).

  In this preparatory process, as is well known by the batch lamination method known as PALAP, the conductor pattern 30 is formed on the resin film constituting the insulating base material 20 before the lamination, or the interlayer connection portion is sintered. The via paste is filled with conductive paste 40a to be 40. The arrangement of the conductor pattern 30 and the via holes filled with the conductive paste 40a is appropriately determined according to the wiring part and the heat transfer path part described above.

  The conductor pattern 30 can be formed by patterning a conductor foil adhered to the surface of the resin film. The plurality of resin films constituting the insulating base material 20 may include a resin film having the conductor pattern 30. For example, a configuration in which all the resin films have the conductor pattern 30 or a part of the resin films are the conductor pattern 30. A configuration that does not include the can also be adopted. Moreover, as a resin film which has the conductor pattern 30, both the resin film which has the conductor pattern 30 only on one side, and the resin film which has the conductor pattern 30 on both surfaces in a lamination direction are employable.

  On the other hand, the conductive paste 40a can be obtained by adding ethyl cellulose resin, acrylic resin or the like to the conductive particles for imparting shape retention and kneading in an organic solvent such as terpineol. Then, a via hole penetrating the resin film is formed by a carbon dioxide laser or the like, and the conductive paste 40a is filled into the via hole by screen printing or the like. The via hole may be formed with the conductor pattern 30 as a bottom surface, or the via hole may be formed at a position where the conductor pattern 30 is not present.

  When the via hole is formed on the conductor pattern 30, the conductive pattern 40 becomes the bottom, so that the conductive paste 40a can be retained in the via hole. On the other hand, when a via hole is formed at a position different from the formation position of the conductor pattern 30 while having the resin film having the conductor pattern 30 or the conductor pattern 30, the conductive film is not conductive in the bottomless via hole. In order to fasten the paste 40a, the conductive paste 40a described in Japanese Patent Application No. 2008-296074 by the present applicant is used. Moreover, as an apparatus (method) for filling the conductive paste 40a, an apparatus (method) described in Japanese Patent Application No. 2009-75034 by the present applicant may be employed.

  The conductive paste 40a decomposes or volatilizes the conductive particles at a temperature lower than the sintering temperature of the conductive particles, becomes a molten state at a temperature lower than the temperature and higher than the room temperature, and is solid at room temperature. A low melting point room temperature solid resin that is in a state is added. An example of the low melting point room temperature solid resin is paraffin. According to this, by heating at the time of filling, the low melting point room temperature solid resin is melted into a paste, and in the cooling after filling, the low melting point room temperature solid resin is solidified to solidify the conductive paste 40a, It can be held in the via hole. When filling, one end of the via hole may be closed with a flat member.

  First, a process of preparing four resin films 21a, 21c, 22a, and 22c laminated on the semiconductor unit 80 will be described.

  In the present embodiment, as shown in FIG. 2, among the four resin films 21a, 21c, 22a, and 22c, only the thermosetting resin film 21a has a copper foil (for example, thickness 18 μm) attached to one side. A film is prepared and the copper foil is patterned to form the conductor patterns 30 respectively. As for the remaining two resin films 21b and 22b constituting the semiconductor unit 80, only a thermosetting resin film 21b is prepared with a film having a copper foil (also 18 μm in thickness) attached to one side. The conductor pattern 30 is formed by patterning.

  That is, among the resin films 21 a to 21 c and 22 a to 22 c, the thermosetting resin films 21 a and 21 b are configured to have the conductor pattern 30 on one side, and the thermoplastic resin films 22 a to 22 c do not include the conductor pattern 30. And

  Of the four resin films 21a, 21c, 22a, and 22c, the conductor pattern 30 has an external connection electrode 33 on one side (inner surface in a laminated state), and the thermoplastic resin films 22a and 22c have via holes (reference numerals). And a conductive paste 40a is filled in the via hole. And after filling, a solvent is volatilized in a drying process.

  Thus, in this embodiment, since the conductor pattern 30 is formed only on the thermosetting resin film 21a, the thermoplastic particles 22a and 22c not forming the conductor pattern 30 are made of Ag particles and Sn particles as conductive particles. The conductive paste 40a is used which is contained at a predetermined ratio and to which a low melting point room temperature solid resin such as paraffin is added as described above.

  Furthermore, in this preparatory process, in order to accommodate each of the plurality of semiconductor chips 50, the stacked body forms holes in some of the plurality of resin films in advance. Both the through hole and the non-through hole can be adopted as the hole. In the present embodiment, a plurality of cavities 23 (through holes) for accommodating the plurality of semiconductor chips 50 are formed as holes in the thermosetting resin film 21c. For this reason, the thermosetting resin film 21c which has the cavity part 23 exhibits a grid | lattice form.

  Each cavity 23 can be formed by mechanical processing such as punching or drilling or laser light irradiation, and the cavity is formed by the flow of the thermoplastic resin during pressurization and heating with respect to the physique of one semiconductor chip 50. It is formed with a predetermined margin for filling. The formation timing of the cavity portion 23 may be before or after the formation of the conductor pattern 30 and the interlayer connection portion 40.

  Moreover, the formation process of the semiconductor unit 80 is implemented in parallel with the preparation process of above-described resin film 21a, 21c, 22a, 22c. 3 and 4 showing the process of forming the semiconductor unit 80, the peripheral region of one semiconductor chip 50 among the plurality of semiconductor chips 50 is shown enlarged.

  First, a resin film including at least a first film and constituting a substrate for mounting a semiconductor chip 50 and a second film for sealing between the substrate and the semiconductor chip 50 are prepared.

  In this embodiment, as shown to Fig.3 (a), the thermosetting resin film 21b as a 1st film which makes a board | substrate, and the thermoplastic resin film 22b as a 2nd film are prepared. About the thermosetting resin film 21b, what the copper foil was affixed on one side is prepared, this copper foil is patterned, and the conductor pattern 30 is formed. At this time, the pad 31 and the horizontal wiring part 32 are formed as the conductor pattern 30.

  Next, by applying heat and pressure, the thermoplastic resin film 22b is attached to the pad forming surface of the substrate so as to cover the pad 31.

  In this embodiment, as shown in FIGS. 3B and 4, the thermoplastic resin film 22 b is thermocompression bonded to the pad forming surface of the thermosetting resin film 21 b as a substrate so as to cover the pad 31. Note that a region indicated by a two-dot chain line in FIG. 4 indicates the mounting region 24 of the semiconductor chip 50.

  Specifically, pressurizing the thermoplastic resin film 22b while heating the thermoplastic resin film 22b so that the temperature is not lower than the melting point and not higher than the glass transition point of the thermoplastic resin constituting the film 22b. Then, the softened thermoplastic resin is brought into close contact with the pad forming surface of the thermosetting resin film 21 b and the surface of the conductor pattern 30.

  After thermocompression bonding the thermoplastic resin film 22b to the thermosetting resin film 21b, via holes are formed in the thermosetting resin film 21b with the conductive pattern 30 as the bottom surface, and the via holes are as shown in FIG. Is filled with the conductive paste 40a. Here, since the conductive pattern 30 is the bottom surface, the conductive paste 40a may be a conductive paste that does not include a low melting point room temperature solid resin, or a conductive paste that includes a low melting point room temperature solid resin. May be.

  Next, the separately prepared semiconductor chip 50 is flip-chip mounted on the substrate.

  In the semiconductor chip 50, stud bumps 52a are formed on the electrodes 51a on the mounting surface with respect to the substrate. In the present embodiment, stud bumps 52a (bump-like bumps) made of Au are formed on an electrode 51a made of an Al-based material by a well-known method using, for example, a wire.

  Then, as shown in FIG. 3C, the semiconductor chip 50 is pressed toward the substrate while being heated from the back surface side of the substrate mounting surface by, for example, a pulse heat type thermocompression bonding tool 100. At this time, pressure is applied to the thermosetting resin film 21b side while heating at a temperature equal to or higher than the melting point of the thermoplastic resin constituting the thermoplastic resin film 22b (PEEK: PEI = 30: 70, 330 ° C.).

  When the heat from the thermocompression bonding tool 100 is transferred to the semiconductor chip 50 and the tip temperature of the stud bump 52a becomes equal to or higher than the melting point of the thermoplastic resin constituting the thermoplastic resin film 22b, the portion of the thermoplastic resin film 22b with which the stud bump 52a contacts. Softens and melts (melts). Therefore, the stud bump 52a can be pushed into the thermoplastic resin film 22b and brought into contact with the corresponding pad 31 while the thermoplastic resin film 22b is melted. Thereby, as shown in FIG.3 (d), the stud bump 52a and the pad 31 can be made into a press-contact state.

  The melted / softened thermoplastic resin flows under pressure and adheres to the substrate mounting surface of the semiconductor chip 50, the pad forming surface of the thermosetting resin film 21b, the conductor pattern 30, the electrode 51a, and the stud bump 52a. To do. Therefore, as shown in FIG. 3D, the space between the semiconductor chip 50 and the thermosetting resin film 21b (substrate) can be sealed with the thermoplastic resin film 22b. In this way, the semiconductor unit 80 is formed.

  In the present embodiment, the heating temperature at the time of flip chip mounting is set to about 350 ° C., which is slightly higher than the melting point, and a pressure is applied so that the load applied to one stud bump 52a is about 20 to 50 gf. Thereby, the stud bump 52a and the pad 31 can be brought into a pressure contact state in a short time.

  When heating and pressurization are continued even after the pressure contact state is reached, Au constituting the stud bump 52a and Cu constituting the pad 31 diffuse to each other (solid phase diffusion), and a metal diffusion layer (Cu— Au alloy layer) is formed. Further, Au constituting the stud bump 52a is solid-phase diffused with respect to Al constituting the electrode 51a to form a metal diffusion layer (Au—Al alloy layer). However, in order to form such a metal diffusion layer, it takes a longer time for heating and pressurization compared to the above-described press contact state. If it takes a long time to mount the semiconductor chip 50 on the substrate, the formation time of the semiconductor device 10 becomes long as a result, and the manufacturing cost also increases. In the meantime, unnecessary heat is applied to portions other than the electrical connection portions of the electrode 51a, the stud bump 52a, and the pad 31. For this reason, in this mounting process, the connection state between the stud bump 52a and the pad 31 is kept in the pressure contact state.

  Further, in the present embodiment, an example in which the via hole is formed after the thermoplastic resin film 22b is attached to the thermosetting resin film 21b and the conductive paste 40a is filled is shown. However, a via hole may be formed in the thermosetting resin film 21b and the conductive paste 40a may be filled in a state before being attached.

  For the conductive paste 40a, when the semiconductor chip 50 is formed by heating / pressing when flip-chip mounting on a substrate, or when the thermoplastic resin film 22b is formed before being applied, the pressure / heating at the time of application is applied. Thus, the conductive particles may be sintered to form the interlayer connection portion 40 (41), or the conductive paste 40a may be left as it is when the semiconductor unit 80 is formed without being sintered. Moreover, it is good also as a state which one part sintered. In this embodiment, it is set as the electrically conductive paste 40a in the state after flip chip mounting.

  Next, a stacking process for forming a stacked body is performed. In this laminating step, a resin film having a conductor pattern 30 formed on the surface, a resin film filled with a conductive paste 40a in a via hole, and a plurality of holes formed corresponding to each of a plurality of semiconductor chips 50 A plurality of resin films including a resin film having (cavity portion 23) are stacked together with a plurality of semiconductor chips 50 and heat dissipation member 60 to form a stacked body.

  At this time, 1) a plurality of semiconductor chips 50 are arranged in the cavity 23 (hole) and are located at the same position in the stacking direction. 2) one heat dissipation member 60 faces the plurality of semiconductor chips 50. 3) Conductivity for thermally connecting each semiconductor chip 50 and the heat radiating member 60 between the opposite surface of the flip chip mounting surface of each semiconductor chip 50 and the heat radiating member 60. The resin film having the paste 40a is located. 4) At least every other thermoplastic resin film is located, the flip chip mounting surface of the semiconductor chip 50, the surface opposite to the flip chip mounting surface, and the heat dissipation member 60. Are stacked so as to be adjacent to the surface facing the semiconductor chip 50.

  In this embodiment, as shown in FIG. 5, from one end side in the stacking direction, the thermosetting resin film 21a, the thermoplastic resin film 22a, the thermosetting resin film 21b, the thermoplastic resin film 22b, and the thermosetting resin film. A semiconductor unit 80 including a plurality of resin films 21a, 21c, 22a, 22c, resin films 21b, 22b, and a plurality of semiconductor chips 50 in the order of 21c, thermoplastic resin film 22c, and heat dissipation member 60; The heat radiating member 60 is laminated. Thus, in this embodiment, it laminates | stacks so that the thermoplastic resin films 22a-22c and the thermosetting resin films 21a-21c may be located alternately. In FIG. 5, for the sake of convenience, the elements constituting the laminated body are illustrated separately.

  Specifically, the thermoplastic resin film 22a is laminated on the conductor pattern forming surface of the thermosetting resin film 21a, and the semiconductor unit 80 is laminated on the thermoplastic resin film 22a using the thermosetting resin film 21b as a mounting surface. . On the thermoplastic resin film 22b in the semiconductor unit 80, the thermosetting resin film 21c is laminated so that the semiconductor chip 50 is positioned in the cavity 23. Moreover, the thermoplastic resin film 22c is laminated | stacked on the thermosetting resin film 21c and the semiconductor chip 50, and the thermal radiation member 60 is laminated | stacked on the thermoplastic resin film 22c, and one laminated body is formed.

  In this laminated body, the resin film adjacent to the semiconductor chip 50 in the lamination direction becomes the thermoplastic resin films 22b and 22c. At least these resin films 22b and 22c fulfill the function of sealing the periphery of the semiconductor chip 50 in the pressurizing / heating process. In this embodiment, since the resin film surrounding each semiconductor chip 50 in the vertical direction is the thermosetting resin film 21c, the two resin films 22b and 22c serve to seal the periphery of the semiconductor chip 50. .

  As described above, as the thermoplastic resin films 22b and 22c for sealing the semiconductor chip 50, the thermoplastic resin film does not contain an inorganic material such as glass fiber or aramid fiber, and the linear expansion coefficient and the melting point are adjusted. Therefore, it is preferable to employ a material that does not contain any inorganic filler. By doing so, it is possible to prevent the semiconductor chip 50 from being locally stressed in the pressurizing / heating step.

  However, when the thermoplastic resin films 22b and 22c that do not include an inorganic filler for adjusting the linear expansion coefficient and the melting point are employed, the difference in the linear expansion coefficient from the semiconductor chip 50 increases due to the absence of the inorganic filler. It is conceivable that the stress increases. Therefore, a resin film having a low elastic modulus (for example, 10 GPa or less) may be employed as the thermoplastic resin films 22b and 22c in order to reduce stress.

  Further, as the thermoplastic resin films 22b and 22c for sealing the semiconductor chip 50, those having a thickness of 5 μm or more are preferably employed. This is because if the thickness is less than 5 μm, the stress of the resin films 22b and 22c is increased in the pressurizing / heating step and may be peeled off from the surface of the semiconductor chip 50.

  Next, a pressurizing / heating step is performed in which the laminate is heated while being pressed from above and below in the stacking direction using a vacuum heat press. In this step, the thermoplastic resin is softened, 1) a plurality of resin films are integrated together to form the insulating substrate 20, 2) the semiconductor chip 50 is sealed, and 3) the heat dissipation member 60 is insulated from the insulating base 60. 4) integrating the conductive particles in the conductive paste 40a as a sintered body, the wiring part having the sintered body and the conductor pattern 30, and the heat dissipation member 60 and each semiconductor chip 50; A heat transfer path portion to be thermally connected is formed.

  In the pressurizing / heating step, in order to realize the above 1) to 4), the temperature of the glass transition point to the melting point of the thermoplastic resin constituting the resin film and the pressure of several MPa are maintained for a predetermined time. In the present embodiment, a press temperature of 280 ° C. to 330 ° C. and a pressure of 4 to 5 MPa are maintained for 5 minutes or longer (for example, 10 minutes).

  First, the connection of the resin film part in the pressurizing / heating step will be described.

  The thermoplastic resin films 22a to 22c arranged every other sheet are softened by the heating. Since the pressure is received at this time, the softened thermoplastic resin films 22a-22c closely_contact | adhere to the adjacent thermosetting resin films 21a-21c. As a result, the plurality of resin films 21 a to 21 c and 22 a to 22 c are integrated together to form the insulating base material 20. At this time, since the adjacent thermoplastic resin film 22 c is also in close contact with the heat radiating member 60, the heat radiating member 60 is also integrated with the insulating base material 20.

  In this embodiment, the laminated body in which the heat radiation member 60 made of a silicon-based material is arranged on the surface layer is heated while being pressed from above and below in the lamination direction. That is, the heat radiating member 60 made of a silicon material is pressurized. However, a thermosetting resin film 21c (resin film) having a plurality of cavities 23 (holes) formed corresponding to each of the plurality of semiconductor chips 50 is prepared, and the resin is used in the laminating step. A semiconductor chip 50 is disposed in each cavity 23 of the film 21c. That is, in the vertical direction, the semiconductor chip 50 is surrounded by a thermosetting resin film 21c (resin film) in a laminated state, and the heat dissipation member 60 made of a silicon-based material is not limited to the portion where the semiconductor chip 50 is disposed. It is supported by the whole part of the laminate excluding the heat dissipation member 60. Therefore, it is possible to pressurize and heat the heat radiating member 60 made of a silicon-based material without damaging it.

  In the present embodiment, the thermoplastic resin of the thermoplastic resin films 21a to 21c is softened among the resin films that support the heat dissipation member 60 in the pressurizing / heating step. Therefore, the heat radiation member 60 is configured in one stacked body including the plurality of semiconductor chips 50 and one heat radiation member 60 due to thickness variations in the plurality of semiconductor chips 50, height variations of the flip chip mounting portions, and the like. The distance between one surface of the laminated body and the surface opposite to the heat dissipation member 60 (the back surface of the conductor pattern forming surface in the thermosetting resin film 21a) varies, that is, the thermosetting resin film 21a. Even if the heat dissipating member 60 is inclined with respect to the back surface, the softened thermoplastic resin flows so as to suppress the inclination of the heat dissipating member 60 (to suppress variation in distance) in the pressurizing / heating process. . Therefore, variation in stress within the surface of the heat dissipation member 60 can be reduced. Also by this effect, it is possible to pressurize and heat the heat radiating member 60 made of a silicon-based material without damaging it.

  Further, the thermoplastic resin films 22b and 22c adjacent to the semiconductor chip 50 flow under pressure, and are placed on the flip chip mounting surface (electrode 51a forming surface) of the semiconductor chip 50 and the surface opposite to the flip chip mounting surface. In close contact. Further, it also enters the gap between the side surface of the semiconductor chip 50 and the thermosetting resin film 21c, fills the gap, and adheres closely to the side surface of the semiconductor chip 50. Therefore, each semiconductor chip 50 is sealed with the thermoplastic resin (thermoplastic resin films 22b and 22c).

  Next, the connection by the interlayer connection part 40 in the pressurizing / heating step will be described.

  By the above heating, Sn (melting point: 232 ° C.) in the conductive paste 40a is melted and diffused to Ag particles in the conductive paste 40a to form an Ag—Sn alloy (melting point: 480 ° C.). Further, since pressure is applied to the conductive paste 40a, interlayer connection portions 40 (41, 42) made of an alloy integrated by sintering are formed in the via holes. The second interlayer connection portion 42 constitutes a heat transfer path portion that thermally connects each semiconductor chip 50 and the heat dissipation member 60.

  The melted Sn also interdiffuses with Cu forming the conductor pattern 30 (lateral wiring portion 32). Thereby, a metal diffusion layer (Cu—Sn alloy layer) is formed at the interface between the first interlayer connection portion 41 and the lateral wiring portion 32.

  The molten Sn also diffuses with Ni constituting the dummy electrode 51b of the semiconductor chip 50. As a result, a metal diffusion layer (Ni—Sn alloy layer) is formed at the interface between the second interlayer connection portion 42 and the dummy electrode 51b.

Further, Au constituting the stud bump 52 a is solid-phase diffused into Al constituting the electrode 51 a of the semiconductor chip 50. Since the electrode 51a is a fine pitch compatible electrode, the amount of Al constituting the electrode 51a is smaller than the amount of Au constituting the stud bump 52a, and the thickness of the portion of the electrode 51a facing the stud bump 52a. All of the Al in the direction is consumed for alloying with Au, and after the pressurizing / heating step, Al is not contained as a single metal in the above-mentioned part. Moreover, the electrode 51a after pressurization and heating mainly contains an Au ₄ Al alloy as an Au—Al alloy.

In addition, even if Au ₅ Al ₂ having a high growth rate is produced before the Au ₄ Al alloy is produced in the pressurizing / heating step, since the pressure is applied, the above-mentioned Kirkendall void is produced. Can be suppressed.

Further, Au constituting the stud bump 52a and Cu constituting the conductor pattern 30 (pad 31) diffuse mutually. Thereby, a Cu—Au alloy layer containing a CuAu ₃ alloy is formed at the interface between the connection portion 52 derived from the stud bump and the pad 31. The Cu—Au alloy can be generated if it is heated to about 250 ° C. or more, and the CuAu ₃ alloy layer can be formed according to the above-described pressurizing / heating conditions.

  In addition, the stud bump 52a includes an electrode 51a including a portion made of an Au—Al alloy and a pad 31 made of Cu and having a Cu—Au alloy layer at the interface due to the remainder of Au consumed in the solid phase diffusion bonding. It becomes the connection part 52 connected electrically. Thus, in the pressurizing / heating process, the connection state between the stud bump 52a and the pad 31 is set to a direct bonding state.

  As described above, as shown in FIG. 6, the semiconductor chip 50 is built in the insulating base material 20, the semiconductor chip 50 is sealed with the thermoplastic resin, and the semiconductor chip 50 and the external connection electrode 33 are electrically connected by the wiring portion. Thus, it is possible to obtain a wiring substrate in which the semiconductor chip 50 and the heat dissipation member 60 are thermally connected by the heat transfer path portion (second interlayer connection portion 42).

  Next, a dicing process is performed in which the wiring substrate in which the plurality of semiconductor chips 50 are embedded, which is obtained through the pressurizing / heating process, is diced and separated into individual semiconductor devices 10. In this dicing process, the heat radiating member 60 and the insulating base material 20 made of a silicon-based material are diced along a dicing line 101 shown by a broken line in FIG. 6 so that each semiconductor device 10 includes one semiconductor chip 50. As shown in FIG. 7, the wiring substrate is divided into pieces for each semiconductor chip 50.

  And in this embodiment, about the wiring board separated into pieces after dicing, the hole which uses the electrode 33 for external connection as a bottom face from the one surface 20a side of the insulating base material 20 is formed, and conductive members, such as a plating film, in the hole Then, solder balls 70 are formed on the conductive member. Thus, the semiconductor device 10 shown in FIG. 1 can be obtained.

  Next, effects of characteristic portions in the semiconductor device 10 and the manufacturing method thereof shown in the above embodiment will be described. First, the effects of the main features will be described.

  In the present embodiment, when the semiconductor device 10 is formed, the thermoplastic resin films 22a to 22c are positioned at least every other piece, and the flip chip mounting surface of the semiconductor chip 50, the surface opposite to the flip chip mounting surface, and A plurality of resin films 21 a to 21 c and 22 a to 22 c are adjacent to the surface of the heat dissipation member 60 facing the semiconductor chip 50 so as to be adjacent to the electrode 51 a formation surface of the semiconductor chip 50 and the back surface of the electrode formation surface. Are laminated to form a laminate.

  Therefore, by applying pressure and heating, the plurality of resin films 21a to 21c and 22a to 22c are integrated together to form the insulating base material 20 by using the thermoplastic resin constituting the thermoplastic resin films 22a to 22c as an adhesive. be able to. In addition, the semiconductor chip 50 can be sealed by at least the thermoplastic resin films 22b and 22c adjacent to the semiconductor chip 50. Moreover, the heat radiating member 60 can be integrated with the insulating base material 20 by using the thermoplastic resin film 22c as an adhesive. Furthermore, the conductive particles in the conductive paste 40a are made into a sintered body by the pressurization and heating, and a wiring portion is formed together with the conductor pattern 30, and the semiconductor chip 50 and the heat dissipation member 60 are thermally connected. A heat transfer path portion can be formed. And after sealing the several semiconductor chip 50 collectively, it can dice and can obtain each semiconductor device 10. FIG.

  As described above, according to this embodiment, the semiconductor chip 50 is flip-chip mounted on the wiring substrate, the semiconductor chip 50 is resin-sealed, and the surface of the semiconductor chip 50 opposite to the flip chip mounting surface is made of a silicon-based material. The semiconductor device 10 to which the heat dissipating member 60 is thermally connected can be formed without going through a grinding step after collective sealing as in the prior art. Therefore, the manufacturing process can be simplified.

  Moreover, since the heat dissipation member 60 made of a silicon-based material is adopted, even if the MAP method is applied and the heat dissipation member 60 is diced together, burrs generated in the heat dissipation member are suppressed compared to the heat dissipation member made of a metal material. be able to.

  In the present embodiment, a thermosetting resin film 21c (resin film) having a plurality of cavities 23 (holes) formed corresponding to each of the plurality of semiconductor chips 50 is prepared and laminated. In the process, the semiconductor chip 50 is disposed in each cavity 23 of the resin film 21c. For this reason, the heat radiating member 60 made of a silicon-based material is supported not only on the portion where the semiconductor chip 50 is disposed but also on the entire portion of the stacked body excluding the heat radiating member 60. Therefore, it is possible to pressurize and heat without damaging the heat radiating member 60 while pressurizing the heat radiating member 60 made of a silicon-based material.

  In the present embodiment, the thermoplastic resin of the thermoplastic resin films 22a to 22c is softened among the resin films that support the heat dissipation member 60 in the pressurizing / heating step. Therefore, the heat radiation member 60 is inclined with the back surface of the thermosetting resin film 21a forming one surface of the laminate as a reference surface due to thickness variations in the plurality of semiconductor chips 50, height variations of the flip chip mounting portions, and the like. Even if it arrange | positions, in the pressurization and a heating process, the softened thermoplastic resin flows so that the inclination of the thermal radiation member 60 may be suppressed (distance dispersion | variation is suppressed). Thus, since the position is corrected so that the heat radiating member 60 is parallel to the reference surface, the pressing member of the vacuum heat press machine is prevented from being biased in the surface of the heat radiating member 60, and thus the heat radiating member 60. In-plane stress variation can be reduced. Therefore, it is possible to pressurize and heat the heat radiating member 60 made of a silicon-based material without damaging it.

  As described above, according to the manufacturing method according to the present embodiment, the semiconductor chip 50 is flip-chip mounted on the wiring substrate, the semiconductor chip 50 is resin-sealed, and the silicon chip 50 is formed on the surface opposite to the flip chip mounting surface. The semiconductor device 10 to which the heat radiating member 60 made of a system material is thermally connected can be provided by a simple manufacturing process while suppressing damage to the heat radiating member 60.

  In particular, in the present embodiment, via holes are formed corresponding to each semiconductor chip 50 between the opposite surface of the flip chip mounting surface of each semiconductor chip 50 and the heat radiating member 60, and the conductive paste 40a is formed in the via hole. Only one thermoplastic resin film 22c filled with is interposed to form a laminate. Therefore, in the semiconductor device 10, the heat transfer path portion that thermally connects the semiconductor chip 50 and the heat dissipation member 60 is only the second interlayer connection portion 42 derived from the conductive paste 40 a of the thermoplastic resin film 22 c, that is, the stacking direction. The second layer connection portion 42 for only one layer is configured. Thereby, the heat dissipation from the semiconductor chip 50 to the heat dissipation member 60 via the heat transfer path part can be improved.

  Next, effects of other characteristic portions will be described.

  In the present embodiment, the thermoplastic resin film 22b is disposed between the semiconductor chip 50 and the substrate (thermosetting resin film 21b) before the lamination step for forming the laminate, and the melting point of the thermoplastic resin or higher is reached. Pressurize while heating at temperature. Therefore, while the temperature is raised to the melting point or higher of the thermoplastic resin, the thermoplastic resin can be made fluid, and the thermoplastic resin located between the stud bump 52a and the pad 31 is moved by pressurization. Thus, the stud bump 52a can be brought into direct contact with the pad 31 to bring the stud bump 52a and the pad 31 into a pressure contact state.

  At this time, the molten thermoplastic resin flows under pressure and seals between the semiconductor chip 50 and the substrate (thermosetting resin film 21b) including the periphery of the connection portion between the stud bump 52a and the pad 31. . Therefore, electrical insulation between each connection part can be ensured. Moreover, the connection reliability in a connection part can be improved.

  Further, when the stud bump 52a and the pad 31 are brought into the pressure contact state, the flip chip mounting process is finished, and the stud bump 52a and the pad 31 are brought into a joined state by the pressurization / heating received in the pressurization / heating process. . In this manner, the stud bump 52a (connection portion 52) and the pad 31 are brought into a joined state by utilizing the heat and pressure of the pressurizing / heating process, and therefore, the electrode 51a of the semiconductor chip 50 is compared with the pressed state. The reliability of electrical connection between the pad 31 and the pad 31 can be improved.

  Further, in the flip chip mounting process, the stud bump 52a and the pad 31 are brought into a pressure contact state, and the stud bump 52a and the pad 31 are brought into a joined state by utilizing heat and pressure in the pressurizing / heating process. Therefore, in the flip chip mounting process, the manufacturing time can be shortened as compared with a method in which the stud bump 52a and the pad 31 are brought into a bonded state and then the pressurizing / heating process is performed.

  If the stud bump 52a is not brought into contact with the pad 31 before the lamination process, and the stud bump 52a is brought into contact with the pad 31 and brought into a joined state in the pressurizing / heating process, the softened thermoplasticity is obtained. Due to the buffering effect of the resin, the stud bump 52a is less likely to be pushed into the thermoplastic resin film 22b as the second film. As a result, the thermoplastic resin may remain between the stud bump 52a and the pad 31.

  On the other hand, in the present embodiment, the stud bump 52a and the pad 31 are brought into a pressure contact state before the stacking step. It can be set as a joining state.

  As described above, according to the manufacturing method of the present embodiment, the manufacturing process of the semiconductor device 10 can be simplified and the manufacturing time (cycle time) can be shortened.

  In the present embodiment, the conductor pattern 30 is formed only on the thermosetting resin films 21a and 21b, and the conductor pattern 30 is not formed on the thermoplastic resin films 22a to 22c. Therefore, even if the thermoplastic resin is softened during the pressurizing / heating process and flows due to pressure, the conductor pattern 30 is fixed to the thermosetting resin films 21a and 21b. Can be suppressed. For this reason, it is suitable for the semiconductor device 10 incorporating the semiconductor chip 50 corresponding to the fine pitch.

  In the present embodiment, in the pressurizing / heating process, Au constituting the stud bump 52a is solid-phase diffused in the Al of the electrode 51a in contact with one end side of the stud bump 52a, and on the other end side of the stud bump 52a. Solid phase diffusion with Cu of the pad 31 in contact therewith. Therefore, the electrical connection reliability between the electrode 51a and the pad 31 through the stud bump 52a (connection portion 52) can be further improved, and the Au—Al alloy and the Cu—Au alloy are formed in the same process. The manufacturing process can also be simplified.

  By the way, in the semiconductor chip 50 having the electrodes 51 on both sides, when the electrodes 51 provided on both sides are solid-phase diffusion bonded together, the solid is in contact with both sides of the semiconductor chip 50 during the pressurizing / heating process. The pressure (pressing pressure) applied to the semiconductor chip 50 increases. On the other hand, in the present embodiment, the electrode 51a and the pad 31 are electrically connected to each other by the solid phase diffusion of Au on one surface side of the semiconductor chip 50, while the melt is generated on the opposite surface side of the semiconductor chip 50. The dummy electrode 51b is connected by the liquid phase diffusion of Sn. Therefore, the pressure applied to the semiconductor chip 50 on the liquid phase side can be buffered. For this reason, the pressure applied to the semiconductor chip 50 in the pressurizing / heating process is reduced and the reliability of the semiconductor chip 50 is improved while the fine pitch is handled as a solid phase diffusion using the stud bump 52a and one of them is applied. Can do.

  Moreover, in this embodiment, since the thermoplastic resin films 22b and 22c employ an inorganic material such as glass fiber or a resin film that does not contain an inorganic filler, this also applies to the semiconductor chip 50 in the pressurizing / heating process. The applied pressure can be reduced.

  In the present embodiment, in the pressurization / heating step, due to the solid phase diffusion of Au from the stud bump 52a, the portion immediately below the stud bump 52a in the electrode 51a is free of Al as a single metal, Au- It shall consist of Al alloy. As a result, since all the portions of the electrode 51a in contact with the connection portion 52 made of Au are alloyed, generation of Kirkendall void due to diffusion of Au from the connection portion 52 can be suppressed even in a high temperature use environment. .

(Second Embodiment)
In the first embodiment, when the semiconductor chip 50 is flip-chip mounted on the thermosetting resin film 21b as a substrate, the stud bump 52a is affixed on the pad forming surface of the thermosetting resin film 21b. An example is shown in which the pressure contact state with the pad 31 is ensured by pressing into the resin film 22b.

  On the other hand, in this embodiment, as shown in FIGS. 8A and 8B, heat is provided in which a through hole 25 is provided at a position corresponding to the pad 31 on the pad forming surface of the thermosetting resin film 21 b. It is characterized in that the plastic resin film 22b is pasted so that the through hole 25 covers the pad 31.

  In the example shown in FIGS. 8A and 8B, a through hole 25 is provided for each pad 31. According to this, since the thermoplastic resin film 22b is positioned between each connection portion between the stud bump 52a and the pad 31, the softened thermoplastic resin easily covers the connection portion in the flip chip mounting process. That is, while providing the through-hole 25, it is easy to ensure electrical insulation between the connection portions, and the connection reliability at the connection portions is easily improved.

  When the electrodes 51a of the semiconductor chip 50 have a fine pitch, the pads 31 also have a fine pitch. Therefore, it is difficult to form the through hole 25 smaller than the pad 31 (for example, 30 μm in diameter). However, unlike the via hole (through hole) for forming the interlayer connection portion 40, the through hole 25 is not filled with the conductive paste 40a, and the electrode 51a and the pad 31 of the semiconductor chip 50 are electrically connected. It does not prescribe the physique of the connecting portion 52 connected to the. Therefore, since the through hole 25 may be larger than the pad 31, the degree of freedom of forming the through hole is higher than that of the via hole, and can be provided for each pad 31.

  And it heats and pressurizes at the temperature more than the glass transition point of the thermoplastic resin which comprises the thermoplastic resin film 22b (in other words, the softening point which a thermoplastic resin softens), and the semiconductor chip 50 is thermosetting resin. Flip chip mounting is performed on the film 21b. Thereby, the stud bumps 52a of the semiconductor chip 50 are pressed against the corresponding pads 31 through the through holes 25, and the space between the semiconductor chip 50 and the thermosetting resin film 21b is sealed with a softened thermoplastic resin.

  Even if such a method is used, the same effect as the manufacturing method shown in the first embodiment can be obtained.

  Further, according to the manufacturing method shown in the present embodiment, the thermoplastic resin film 22b need not be melted in forming the pressure contact state between the stud bump 52a and the pad 31. The gap between the semiconductor chip 50 and the thermosetting resin film 21b is sealed with a softened thermoplastic resin by applying pressure while heating at a temperature equal to or higher than the glass transition point of the thermoplastic resin constituting the thermoplastic resin film 22b. I can do it. In other words, it is only necessary that the semiconductor chip 50 can be thermocompression bonded to the thermoplastic resin film 22b. Since the through hole 25 is provided in advance in the thermoplastic resin film 22b before flip chip mounting, a press-contact state can be easily formed as compared with the method shown in the first embodiment.

  Therefore, if the amount of heat is the same, it is possible to form the pressure contact state between the stud bump 52a and the pad 31 and the sealing structure by the thermoplastic resin film 22b in a shorter time than the method shown in the first embodiment. That is, the heating / pressurizing time in the flip chip mounting process, and hence the manufacturing time of the semiconductor device 10 can be further shortened.

  Further, if the heating / pressurizing time and the pressurizing condition are the same, it is possible to ensure the press contact state between the stud bump 52a and the pad 31 with a smaller amount of heat than the method shown in the first embodiment.

  The through-hole 25 may be formed before the thermoplastic resin film 22b is attached to the thermosetting resin film 21b, or may be formed after the attachment. In the present embodiment, after pasting, the through hole 25 is formed by a carbon dioxide laser or the like at a position corresponding to the pad 31 in the thermoplastic resin film 22b. When such a method is employed, the through hole 25 can be formed with high positional accuracy.

  On the other hand, when the through hole 25 is formed by laser beam irradiation or the like before being attached, when the thermoplastic resin film 22b is attached, a position different from the formation position of the through hole 25 in the resin film 22b is heated. It is good to apply pressure. Since a position different from the formation position of the through hole 25 is applied by heating and pressing, the through hole 25 can be prevented from being crushed (blocked). Therefore, when the semiconductor chip 50 is mounted on the substrate, the stud bump 52a and the pad 31 can be brought into a pressure contact state in a short time.

  In the present embodiment, an example in which the through hole 25 is provided for each pad 31 has been described, but one through hole 25 may be provided for each of the plurality of pads 31. For example, in the example shown in FIGS. 9A and 9B, the plurality of pads 31 are arranged in a rectangular ring with one side having nine sides, and the through holes 25 are provided for each side, that is, nine pads. One through hole 25 is provided for 31. That is, the through hole 25 is long in one of the vertical directions.

  According to this, compared to the configuration in which one through hole 25 is provided for each pad 31 shown in FIGS. 8A and 8B, the through hole 25 is independent of the interval (pitch) between the pads 31. Can be formed. That is, the degree of freedom of formation of the through holes 25 is high and suitable for fine pitch.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  The structure of the several resin film which comprises the insulating base material 20 is not limited to the said example. The number of resin films is not limited to the above example (six). Any number of semiconductor chips 50 can be used.

  The constituent material of the thermoplastic resin film is not limited to the above example. For example, even if it consists of PEEK / PEI, you may employ | adopt the thing from which a ratio differs from the said example. In addition, constituent materials other than PEEK / PEI, such as liquid crystal polymer (LCP), polyphenylene sulfide (PPS), tetrafluoroethylene / hexafluoropropylene copolymer (FEP), tetrafluoroethylene / perfluoroalkyl vinyl ether copolymer (PFA) ) Etc. may be adopted.

  In order to suppress local stress application to the semiconductor chip 50 in the pressurizing / heating process, as the thermoplastic resin films 22a to 22c, inorganic materials used for base materials such as glass fibers and aramid fibers, melting points and linear expansions. Although the example using the film which does not have the inorganic filler added for adjustment of a coefficient was shown, thermoplastic resin films 22a-22c containing these can also be adopted. However, as described above, with respect to the thermoplastic resin film (two thermoplastic resin films 22b and 22c in this embodiment) used for sealing the semiconductor chip 50, local stress application to the semiconductor chip 50 is performed. In order to suppress this, it is preferable to use an inorganic material used for a substrate such as glass fiber or aramid fiber, or a film having no inorganic filler added for adjusting the melting point or the linear expansion coefficient.

  The constituent material of the thermosetting resin film is not limited to the above example. For example, a film containing an inorganic material used for a substrate such as glass fiber or aramid fiber can also be employed. Also, a thermosetting resin other than the thermosetting polyimide can be employed.

  Moreover, it is good also as a structure which does not contain a thermosetting resin film but contains only a thermoplastic resin film as a several resin film. Alternatively, the number of thermoplastic resin films may be larger than that of the thermosetting resin film, and the thermoplastic resin film may be partially continuous in the laminated state.

  In this embodiment, the example of the thermosetting resin film 21b as a 1st film was shown as a board | substrate with which the semiconductor chip 50 is flip-chip mounted. However, a thermoplastic resin film may be employed as the first film. Moreover, you may comprise a board | substrate using the several resin film containing a 1st film.

  In the present embodiment, stud bumps 52a are provided on the electrodes 51a of the semiconductor chip 50, and the pads 31 corresponding to the electrodes 51a are electrically connected by the connection portions 52 derived from the stud bumps 52a. That is, the semiconductor chip 50 is a substrate. An example of flip chip mounting on the (thermosetting resin film 21b) is shown. However, the configuration in which the semiconductor chip 50 is flip-chip mounted on the substrate (thermosetting resin film 21b) is not limited to the stud bump 52a.

  Further, the thickness of the resin film and the thickness of the conductor pattern 30 are not limited to the above examples. However, as described above, the thermoplastic resin films 22b and 22c that are adjacent to the semiconductor chip 50 and seal the semiconductor chip 50 in the stacking direction preferably have a thickness of 5 μm or more.

  Moreover, the wiring part and heat-transfer path | route part comprised in the insulating base material 20 are not limited to the said example.

  In the present embodiment, in order to improve heat dissipation, an example in which the dummy electrode 51b is provided on the semiconductor chip 50 and the second interlayer connection portion 42 as the heat transfer path portion is connected to the dummy electrode 51b is shown. However, the second interlayer connection portion 42 may be in contact with the surface of the semiconductor chip 50 without the dummy electrode 51b.

  In the present embodiment, an example in which the electrode 51a that provides an electrical connection function is formed only on one surface (flip chip mounting surface) of the semiconductor chip 50 has been described. However, for example, as shown in FIG. 10, it is also possible to employ a semiconductor chip 50 in which an electrode 51c that provides an electrical connection function is formed on the surface opposite to the flip chip mounting surface. As a configuration having the electrodes 51a and 51c on both surfaces, a device in which a current flows in the thickness direction, for example, a semiconductor chip 50 including a vertical MOSFET, IGBT, resistor, or the like, can be considered.

  In FIG. 10, dummy electrodes 51b and electrodes 51c made of a Ni-based material are formed on the surface of the semiconductor chip 50 opposite to the surface on which the electrodes 51a are formed. Interlayer connection portions 41 and 42 are connected to these electrodes 51b and 51c as connection portions to the corresponding pads 34 and 35, respectively. Specifically, the dummy electrode 51 b and the pad 34 are connected by the second interlayer connection portion 42. Further, the electrode 51 c and the pad 35 are connected by the first interlayer connection portion 41. A metal diffusion layer (Ni—Sn alloy layer) in which Sn and Ni are diffused mutually is formed at the interface between the electrodes 51b and 51c made of Ni and the interlayer connection portions 41 and 42 made of Ag—Sn alloy. Thereby, the connection reliability between the electrodes 51b and 51c and the interlayer connection 40 is improved. The electrodes 51b and 51c are formed at a pitch of, for example, 100 μm.

  Further, the pad 35 connected to the electrode 51c via the first interlayer connection portion 41 is drawn out (rewired) to the outside of the semiconductor chip 50 in the vertical direction by the horizontal wiring portion 32 connected to the pad 35. The horizontal wiring portion 32 is connected to the external connection electrode 33 via the first interlayer connection portion 41 connected to the end opposite to the pad 35.

  In the semiconductor device 10 having such a configuration, a plurality of resin films are required between the semiconductor chip 50 and the heat dissipation member 60 in order to rewiring the electrodes 51c. As an example, in FIG. 10, three sheets of a thermoplastic resin film 22c, a thermosetting resin film 21d, and a thermoplastic resin film 22d are arranged from the semiconductor chip 50 side. And the pad 35 and the horizontal wiring part 32 corresponding to the electrode 51c are formed on the surface at the side of the thermoplastic resin film 22c in the thermosetting resin film 21d. The second interlayer connection portion 42 is formed on each of the three resin films 21d, 22c, and 22d.

  In the example shown in FIG. 10, the example in which the three resin films 21d, 22c, and 22d are disposed between the semiconductor chip 50 and the heat radiating member 60 is shown. However, the two thermoplastic resin films 22c and 22d are Arranged configurations can also be employed.

  In the present embodiment, an example is shown in which the semiconductor chip 50 is sealed with the thermoplastic resin film 22b while being flip-chip mounted on the substrate (thermosetting resin film 21b) before the lamination step. However, all the resin films 21a to 21c, 22a to 22c, the plurality of semiconductor chips 50, and the heat dissipation member 60 may be laminated to form a laminated body without being flip-chip mounted in advance. In this case, as shown in the second embodiment, if the through-hole 25 corresponding to the pad 31 is provided, the stud bump 52a (electrode 51a) corresponding to the pad 31 is electrically connected in the pressurizing / heating process. Easy to connect to.

  In the present embodiment, an example in which the electrode 51a of the semiconductor chip 50 and the pad 31 are connected using the stud bump 52a has been shown. However, what constitutes the connection portion 52 is not limited to the stud bump 52a. . In other words, the electrode 51a is not limited to a fine pitch. The semiconductor chip 50 may be flip-chip connected. For example, the electrode 51a and the pad 31 may be connected by a solder paste.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 20 ... Insulation base material 21a-21c ... Thermosetting resin film 22a-22c ... Thermoplastic resin film 30 ... Conductive pattern 31 ... Pad 40 ... Interlayer Connection part 42 ... second interlayer connection part (heat transfer path part)
50 ... Semiconductor chip 60 ... Heat dissipation member 101 ... Dicing line

Claims (2)

A semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring board, the semiconductor chip is resin-sealed, and a heat dissipation member made of a silicon-based material is thermally connected to a surface opposite to the flip chip mounting surface of the semiconductor chip A manufacturing method of
A resin film having a conductive pattern formed on the surface, a resin film filled with a conductive paste in a via hole, and a resin film having a plurality of holes formed corresponding to each of the plurality of semiconductor chips. A preparation step of preparing a plurality of resin films;
The plurality of semiconductor chips are arranged in the hole portions and are located at the same position in the stacking direction, and one heat dissipation member is a surface layer in the stacking direction while facing the plurality of semiconductor chips, and flips in each semiconductor chip A resin film having the conductive paste for thermally connecting each semiconductor chip and the heat dissipating member is located between the opposite surface of the chip mounting surface and the one heat dissipating member, and is thermoplastic. At least every other thermoplastic resin film containing resin is positioned adjacent to the flip chip mounting surface of the semiconductor chip, the surface opposite to the flip chip mounting surface, and the surface of the heat dissipation member facing the semiconductor chip. As described above, the plurality of resin films are divided into a plurality of the semiconductor chips and one sheet of the plurality of semiconductor chips facing the plurality of semiconductor chips. A laminating step of laminating with heat member, to form a laminate,
By heating the laminated body while pressing from above and below in the laminating direction, the thermoplastic resin is softened, the plurality of resin films are integrated together, the semiconductor chip is sealed, and the heat dissipation member is integrated. And using the conductive particles in the conductive paste as a sintered body, the wiring body having the sintered body and the conductor pattern, and the sintered body, each semiconductor chip and the heat dissipation member A pressurizing / heating process for forming a heat transfer path portion that thermally connects the
A dicing step of dicing the insulating base material formed by integrating the plurality of resin films and the heat radiating member into individual semiconductor devices, and a method for manufacturing a semiconductor device.   In the laminating step, via holes are formed corresponding to each semiconductor chip between the opposite surface of the flip chip mounting surface of each semiconductor chip and the one heat dissipation member, and a conductive paste is formed in the via hole. The method of manufacturing a semiconductor device according to claim 1, wherein lamination is performed so that one filled thermoplastic resin film is positioned.

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