JP2010272609A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- JP2010272609A JP2010272609A JP2009121577A JP2009121577A JP2010272609A JP 2010272609 A JP2010272609 A JP 2010272609A JP 2009121577 A JP2009121577 A JP 2009121577A JP 2009121577 A JP2009121577 A JP 2009121577A JP 2010272609 A JP2010272609 A JP 2010272609A
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- substrate
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- semiconductor device
- sealing film
- electronic component
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Abstract
Description
本発明は半導体装置及びその製造方法に関し、半導体素子等の電子部品が実装された基板を有する半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and relates to a semiconductor device having a substrate on which an electronic component such as a semiconductor element is mounted and a manufacturing method thereof.
近年、半導体素子に設けられた回路が高密度化されるに従い、電極端子の数を多くすると共に電極端子のピッチを狭くすることが進められている。電極端子の狭ピッチ化に伴い、半導体素子を実装基板にフリップチップ実装する際に半導体素子と実装基板との間に注入する封止樹脂に対する要求が厳しくなってきている。 In recent years, as the density of circuits provided in semiconductor elements has been increased, it has been promoted to increase the number of electrode terminals and reduce the pitch of electrode terminals. With the narrowing of the pitch of the electrode terminals, there is an increasing demand for a sealing resin that is injected between the semiconductor element and the mounting substrate when the semiconductor element is flip-chip mounted on the mounting substrate.
通常、フリップチップ実装においては、集積回路等の半導体素子の電極端子上にはんだバンプ等の突起電極を形成し、形成した突起電極を実装基板の接続端子に対して圧接して加熱することによりバンプ接続を形成する。 Usually, in flip chip mounting, bump electrodes are formed by forming bump electrodes such as solder bumps on the electrode terminals of semiconductor elements such as integrated circuits, and pressing the formed bump electrodes against the connection terminals of the mounting substrate and heating them. Form a connection.
はんだバンプを用いたフリップチップ接合では、はんだ接合後にフラックスを洗浄し、封止樹脂の注入を行い、注入した封止樹脂を熱硬化する方法が知られている。この方法では、実装基板の電極上にフラックスを供給した後、はんだバンプが形成された半導体素子を位置合わせし、実装基板上に搭載する。その後リフロー炉等の加熱手段によりはんだを溶融接合した後、洗浄液に浸漬しフラックス成分を溶解洗浄する。その後、はんだ接合部の耐落下及び曲げ信頼性を強化する目的で、半導体素子と実装基板との間の空隙に、ディスペンサー等を用いて封止樹脂を注入した後、注入した封止樹脂を熱硬化させる。 In flip chip bonding using solder bumps, a method is known in which flux is washed after solder bonding, sealing resin is injected, and the injected sealing resin is thermally cured. In this method, after supplying flux onto the electrodes of the mounting substrate, the semiconductor element on which the solder bumps are formed is aligned and mounted on the mounting substrate. Thereafter, the solder is melted and joined by a heating means such as a reflow furnace, and then immersed in a cleaning solution to dissolve and clean the flux component. Thereafter, for the purpose of enhancing the drop resistance and bending reliability of the solder joint, the sealing resin is injected into the gap between the semiconductor element and the mounting substrate using a dispenser or the like, and then the injected sealing resin is heated. Harden.
しかし、電極端子の狭ピッチ化が進展し、半導体素子と実装基板の電極と間の隙間も小さくなってきている。このため、洗浄液の循環が悪くなりフラックスが実装基板上に残り、使用環境下においてオープン不良や剥離が発生するおそれが増大している。また、空隙が狭いために毛細管現象の効果を発揮できず、封止樹脂の注入に時間を要し、生産性が低下するという問題が生じている。 However, the pitch between electrode terminals has been reduced, and the gap between the semiconductor element and the electrode of the mounting substrate has also been reduced. For this reason, the circulation of the cleaning liquid is deteriorated, and the flux remains on the mounting substrate, and there is an increased possibility that an open defect or peeling will occur in the use environment. Further, since the gap is narrow, the effect of the capillary phenomenon cannot be exhibited, and it takes time to inject the sealing resin, resulting in a problem that productivity is lowered.
このような不具合への対策として、フラックスを含有した封止接着材を基板上に供給した後、はんだバンプを形成した半導体素子をマウントし、加熱及び加圧手段によって、はんだ接合と同時に封止接着材を熱硬化する方法がある(例えば、特許文献1を参照。)。例えば、金属パターンを有する基板の上にフラックスを含有した封止接着材を供給する。この後、はんだバンプを有する半導体素子をバンプと金属パターンとが対向するように位置合わせをして加圧及び加熱する。これにより、はんだバンプと基板上に設けられた金属パターンとを接続すると同時に接着材を熱硬化させる。 As countermeasures against such problems, after supplying a sealing adhesive containing flux onto the substrate, the semiconductor element on which the solder bumps are formed is mounted, and sealing and bonding are performed simultaneously with soldering by heating and pressing means. There is a method of thermosetting the material (see, for example, Patent Document 1). For example, a sealing adhesive containing flux is supplied on a substrate having a metal pattern. Thereafter, the semiconductor element having solder bumps is positioned, pressed and heated so that the bumps and the metal pattern face each other. As a result, the solder bump and the metal pattern provided on the substrate are connected, and at the same time, the adhesive is thermally cured.
しかし、近年特にモバイル機器に代表される電子機器において、半導体装置の薄型化及び高機能化への要求が高まり、それに追従するため半導体素子及び回路基板の薄型化や回路基板の大型化が進められている。先に述べた方法を薄い半導体素子に適用した場合、加圧によりはみ出した封止接着材が半導体素子の裏面に回り込むおそれがある。半導体基板の熱膨張係数と封止接着剤の線膨張係数との間には差がある。このため、半導体素子の裏面に回り込んだ封止接着材が熱硬化により硬化した後、リフロー炉等により熱が加えられると半導体素子が割れるおそれがある。 However, in recent years, particularly in electronic devices such as mobile devices, there has been an increasing demand for thinning and high functionality of semiconductor devices, and in order to follow this, thinning of semiconductor elements and circuit boards and enlargement of circuit boards have been promoted. ing. When the above-described method is applied to a thin semiconductor element, there is a possibility that the sealing adhesive that protrudes due to pressurization may wrap around the back surface of the semiconductor element. There is a difference between the thermal expansion coefficient of the semiconductor substrate and the linear expansion coefficient of the sealing adhesive. For this reason, there is a possibility that the semiconductor element may be cracked when heat is applied by a reflow furnace or the like after the sealing adhesive material that has wrapped around the back surface of the semiconductor element is cured by thermosetting.
そこで、フラックスを含有した封止フィルムを基板上に載置することにより、封止接着材の量を制御しやすくし、半導体素子裏面への封止接着材の回り込みを防止する方法が提案されている(例えば、特許文献2を参照。)。 Therefore, a method has been proposed in which a sealing film containing a flux is placed on a substrate so that the amount of the sealing adhesive can be easily controlled and the sealing adhesive is prevented from wrapping around the back surface of the semiconductor element. (For example, refer to Patent Document 2).
しかしながら、半導体素子等の電子部品が剥き出しの状態では、リフロー炉等の熱のかかる工程後に、半導体素子の線膨張係数と回路基板の線膨張係数との差による影響を大きく受ける。このため、半導体装置の反りが大きくなり、半導体装置をマザーボードへ実装する際に、電極端子のオープン不良が発生するおそれがある。さらに、高温の使用環境と低温の使用環境とを繰り返すと、半導体素子と回路基板の線膨張係数及び弾性率の差から、接続部に大きな熱応力負荷がかかり、接続部が破断し、オープン不良が発生するおそれがある。このように、従来の半導体装置には、半導体素子と基板との接続信頼性が低いという問題があった。 However, when an electronic component such as a semiconductor element is exposed, it is greatly affected by the difference between the linear expansion coefficient of the semiconductor element and the linear expansion coefficient of the circuit board after a heat-applied process such as a reflow furnace. For this reason, the warp of the semiconductor device is increased, and there is a possibility that an open failure of the electrode terminal may occur when the semiconductor device is mounted on the mother board. In addition, if high temperature usage environment and low temperature usage environment are repeated, a large thermal stress load is applied to the connection part due to the difference in coefficient of linear expansion and elastic modulus between the semiconductor element and the circuit board. May occur. As described above, the conventional semiconductor device has a problem that the connection reliability between the semiconductor element and the substrate is low.
本発明は、前記の問題を解決し、半導体素子等の電子部品と基板との接続信頼性を向上させた半導体装置を実現できるようにすることを目的とする。 An object of the present invention is to solve the above problems and to realize a semiconductor device in which the connection reliability between an electronic component such as a semiconductor element and a substrate is improved.
前記の目的を達成するため、本発明は半導体装置を、封止フィルムが基板上の全面を覆い且つ半導体素子を覆う構成とする。 In order to achieve the above object, the present invention has a semiconductor device in which a sealing film covers the entire surface of a substrate and covers a semiconductor element.
具体的に、本発明に係る半導体装置は、第1の基板電極を有する第1の基板と、第1の部品電極を有し、第1の基板電極と第1の部品電極とを対向させて第1の基板の上に搭載された第1の電子部品と、第1の基板電極と第1の部品電極とを電気的に接続する第1の接続部材と、第1の基板上の全面を覆い、フラックス成分を含有する封止フィルムとを備え、第1の電子部品は側面全体が封止フィルムに覆われていることを特徴とする。 Specifically, a semiconductor device according to the present invention includes a first substrate having a first substrate electrode, a first component electrode, and the first substrate electrode and the first component electrode facing each other. A first electronic component mounted on the first substrate; a first connecting member for electrically connecting the first substrate electrode and the first component electrode; and an entire surface on the first substrate. And a sealing film containing a flux component. The first electronic component is characterized in that the entire side surface is covered with the sealing film.
本発明の半導体装置は、第1の基板上の全面を覆う封止フィルムを備えている。このため、封止フィルムが部分的に形成されている場合と比べて半導体装置全体の反りが低減される。また、第1の電子部品は側面全体が封止フィルムに覆われている。このため、リフロー等の熱がかかる工程及び冷熱サイクルの繰り返し等において、半導体素子等の電子部品が剥き出しの場合と比べて、封止フィルムと基板との厚さ方向の膨張の差が小さくなる。また、厚さ方向に加わる応力の差も小さくなる。このため、半導体装置全体としての反りがさらに低減でき、半導体素子等の電子部品と基板との接続信頼性を向上させることができる。 The semiconductor device of the present invention includes a sealing film that covers the entire surface of the first substrate. For this reason, the curvature of the whole semiconductor device is reduced compared with the case where the sealing film is partially formed. Further, the entire side surface of the first electronic component is covered with a sealing film. For this reason, the difference in expansion in the thickness direction between the sealing film and the substrate is smaller than in the case where an electronic component such as a semiconductor element is exposed in a process where heat is applied, such as reflow, and repetition of a cooling cycle. Also, the difference in stress applied in the thickness direction is reduced. For this reason, the warpage of the entire semiconductor device can be further reduced, and the connection reliability between the electronic component such as a semiconductor element and the substrate can be improved.
本発明の半導体装置において、第1の電子部品は、半導体素子であればよい。また、第1の電子部品は複数であり、少なくとも1つは半導体素子である構成としてもよい。 In the semiconductor device of the present invention, the first electronic component may be a semiconductor element. The first electronic component may be a plurality, and at least one may be a semiconductor element.
本発明の半導体装置は、封止フィルムの上に搭載された第2の基板をさらに備え、第1の基板は第1の基板接続電極を有し、第2の基板は第2の基板接続電極を有し、第1の基板接続電極と第2の基板接続電極とは、互いに対向し且つ第2の接続部材を介して電気的に接続されている構成としてもよい。この場合、第1の基板と第2の基板とが封止フィルムを介して隙間なく接着された構造となるため、熱が加えられた際の厚さ方向の伸縮量が隙間がある場合よりも小さくなる。このため、半導体装置の反りが小さくなり、接続信頼性が向上する。また、水分の侵入を低減できるという効果も得られる。 The semiconductor device of the present invention further includes a second substrate mounted on the sealing film, the first substrate has a first substrate connection electrode, and the second substrate is a second substrate connection electrode. The first substrate connection electrode and the second substrate connection electrode may be configured to face each other and be electrically connected via the second connection member. In this case, since the first substrate and the second substrate have a structure in which the first substrate and the second substrate are bonded via the sealing film without a gap, the amount of expansion and contraction in the thickness direction when heat is applied is larger than when there is a gap. Get smaller. For this reason, the warp of the semiconductor device is reduced and the connection reliability is improved. Moreover, the effect that the penetration | invasion of a water | moisture content can be reduced is also acquired.
本発明の半導体装置において、封止フィルムの上に搭載された放熱板をさらに備えていることが好ましい。このような構成とすることにより、発熱量が大きい半導体装置の場合にも適用することができる。この場合において、放熱板は第1の電子部品における第1の部品電極と反対側の面と接している構成とすればよい。 In the semiconductor device of the present invention, it is preferable to further include a heat sink mounted on the sealing film. By adopting such a configuration, the present invention can be applied to a semiconductor device that generates a large amount of heat. In this case, the heat radiating plate may be configured to be in contact with the surface of the first electronic component opposite to the first component electrode.
本発明の半導体装置において、第1の接続部材は、はんだであっても、はんだ及び第1の部品電極の上に形成された突起電極としてもよい。 In the semiconductor device of the present invention, the first connecting member may be a solder or a protruding electrode formed on the solder and the first component electrode.
本発明に係る半導体装置の製造方法は、第1の基板電極を有する第1の基板の上にフラックスを含有する封止フィルムを貼り付ける工程(a)と、第1の電子部品に形成された第1の部品電極の上に第1の接続部材を接続する工程(b)と、工程(b)よりも後に、第1の電子部品を封止フィルム中に埋設すると共に、第1の基板電極と第1の接続部材とを電気的に接続する工程(c)と、工程(c)よりも後に、封止フィルムを加熱して硬化する工程(d)とを備え、工程(b)では第1の電子部品の側面全体が封止フィルムに覆われるようにすることを特徴とする。本発明の半導体装置の製造方法によれば、半導体素子と基板の間を封止する封止樹脂と、半導体素子を覆う封止樹脂とを同一材料で且つ一工程で形成できる。このため、複数の封止フィルムを用いる場合に比べ空隙がなく密着性が向上するので、接続信頼性を向上する半導体装置を容易に製造することが可能となる。 The method of manufacturing a semiconductor device according to the present invention includes a step (a) of attaching a sealing film containing a flux on a first substrate having a first substrate electrode, and the first electronic component. The step (b) of connecting the first connecting member on the first component electrode, and the first electronic component is embedded in the sealing film after the step (b), and the first substrate electrode A step (c) of electrically connecting the first connecting member and the first connecting member, and a step (d) of heating and curing the sealing film after the step (c). The entire side surface of one electronic component is covered with a sealing film. According to the method for manufacturing a semiconductor device of the present invention, the sealing resin that seals between the semiconductor element and the substrate and the sealing resin that covers the semiconductor element can be formed of the same material and in one step. For this reason, since there is no space and adhesion is improved as compared with the case of using a plurality of sealing films, it is possible to easily manufacture a semiconductor device that improves connection reliability.
本発明の半導体装置の製造方法は、第2の基板に形成された第2の基板接続電極の上に第2の接続部材を接続する工程(e)と、工程(c)よりも後で且つ工程(d)よりも前に、第2の基板接続電極と接続された第2の接続部材を封止フィルム中に埋設すると共に、第1の基板に形成された第1の基板接続電極と第2の接続部材とを電気的に接続する工程(f)とをさらに備えていてもよい。 The method for manufacturing a semiconductor device according to the present invention includes a step (e) of connecting a second connection member on a second substrate connection electrode formed on a second substrate, a step after the step (c), and Before the step (d), the second connection member connected to the second substrate connection electrode is embedded in the sealing film, and the first substrate connection electrode formed on the first substrate and the first substrate connection electrode And a step (f) of electrically connecting the two connecting members.
本発明の半導体装置の製造方法において、第1の電子部品は複数であり、少なくとも1つは半導体素子としてもよい。 In the method for manufacturing a semiconductor device of the present invention, the first electronic component may be a plurality, and at least one may be a semiconductor element.
本発明の半導体装置の製造方法において、第1の電子部品は複数であり、工程(d)よりも後に、第1の基板を少なくとも1つの第1の電子部品が搭載された複数のブロックに分割する構成としてもよい。 In the method of manufacturing a semiconductor device according to the present invention, the first electronic component is plural, and after the step (d), the first substrate is divided into a plurality of blocks on which at least one first electronic component is mounted. It is good also as composition to do.
本発明に係る半導体装置及びその製造方法によれば、半導体素子等の電子部品と基板との接続信頼性を向上させた半導体装置を実現できる。 According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to realize a semiconductor device with improved connection reliability between an electronic component such as a semiconductor element and a substrate.
(一実施形態)
図1は、本発明の一実施形態に係る半導体装置の断面構成を示している。図1に示すように本実施形態の半導体装置は、回路基板である第1の基板12の上に、半導体素子である第1の電子部品13が搭載されている。第1の基板12の上には封止フィルム14が形成され、第1の電子部品13は封止フィルム14に埋め込まれている。
(One embodiment)
FIG. 1 shows a cross-sectional configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, in the semiconductor device of this embodiment, a first
第1の基板12は、例えば、ガラスエポキシ多層基板又はアラミド多層基板等の回路基板とすればよい。また、回路基板に代えてシリコン基板等であってもよい。第1の基板12の部品搭載面には、第1の基板電極21が形成されている。第1の基板12の部品搭載面と反対側の面(裏面)には、外部接続電極22が形成されている。外部接続電極22には、はんだボール23が形成されている。はんだボール23はなくてもかまわない。
The
第1の電子部品13は半導体素子であり、一の面に第1の部品電極31が形成されている。第1の部品電極31は、第1の接続部材32を介して第1の基板電極21と電気的に接続されている。第1の接続部材32は、はんだバンプ等の突起電極である。第1の電子部品13は、封止フィルム14中に埋設されており、第1の電子部品13の側面全体が封止フィルム14により覆われている。このため、リフロー等の熱がかかる工程及び冷熱サイクルの繰り返しにおいて、半導体素子が剥き出しの場合と比較し、封止樹脂と基板で厚み方向にかかる応力差、膨張差が少なくなる。従って、半導体装置としての反りが低減でき、半導体素子などの電子部品と基板との接続信頼性を向上させることができる。
The first
封止フィルム14は、ベース樹脂、硬化剤、添加剤、無機フィラー及びフラックス成分を含む。フラックス成分を含むため、加熱加圧した状態で第1の接続部材32を溶融して第1の基板電極21と第1の部品電極31とをはんだ接合する際に、フラックスとして作用する。また、加熱することにより三次元架橋し、第1の基板12と第1の電子部品13とを接着封止することができる。
The sealing
ベース樹脂は、例えば、エポキシ樹脂、アクリル樹脂、フェノール樹脂、シリコーン樹脂又はウレタン樹脂等とすればよい。また、フラックス成分は、例えば、フェノール性水酸基を有する樹脂、環状オレフィン系樹脂、リンゴ酸、アビエチン酸、アジピン酸、アスコルビン酸、アクリル酸、クエン酸、2−フロイック酸(2-furoic acid)又はポリアクリル酸等とすればよい。フィラーには、例えばアルミナ若しくはシリカ等の無機フィラー又はアクリル等の有機フィラーを用いればよく、含有率は40質量%〜70質量%とすればよい。 The base resin may be, for example, an epoxy resin, an acrylic resin, a phenol resin, a silicone resin, or a urethane resin. The flux component may be, for example, a resin having a phenolic hydroxyl group, a cyclic olefin resin, malic acid, abietic acid, adipic acid, ascorbic acid, acrylic acid, citric acid, 2-furoic acid, or poly Acrylic acid or the like may be used. As the filler, for example, an inorganic filler such as alumina or silica or an organic filler such as acrylic may be used, and the content may be 40% by mass to 70% by mass.
封止フィルム14は、第1の基板12及び第1の電子部品13の材質及び大きさ等に応じて最適な特性となるように選択すればよい。具体的な一例を挙げると、第1の基板12の線膨張係数が10ppm〜20ppmで、弾性率が10GPa〜30GPaの場合、封止フィルム14のガラス転位温度以下の線膨張係数α1を20ppm〜40ppmとし、ガラス転位温度以上の線膨張係数α2を70ppm〜120ppmとし、弾性率を5GPa〜10GPaとすることが望ましい。封止フィルムの厚さの具体的な一例を挙げると、第1の基板12のサイズが15mm×15mmで、厚さが0.3mmであり、第1の電子部品13のサイズが8mm×8mmで、厚さが0.10mmmであり、第1の接続部材32の高さが0.05mmの場合、封止フィルム14の厚さを0.10mm〜0.18mmとすればよい。この構成により、−50℃〜150℃までの温度範囲において、はんだボールからなる第1の接続部材32の平坦度を0.15mm以内に抑えることができた。
What is necessary is just to select the sealing
未硬化状態のシート性、溶融粘度、酸化皮膜除去性及び硬化性のバランスがとれれば、封止フィルム14はどのようなものであってもよい。封止フィルム14に、硬化触媒、着色料、消泡剤、難燃剤、カップリング剤等の各種添加剤及び溶剤を添加してもかまわない。また、熱可塑性樹脂であってもよい。
As long as the uncured sheet properties, melt viscosity, oxide film removability, and curability are balanced, the sealing
図2は、本実施形態に係る半導体装置の製造方法を工程順に示している。まず、図2(a)に示すように、第1の基板12の搭載面の上に封止フィルム14を貼り付けた後、封止フィルム14の上に第1の電子部品13を載置する。
FIG. 2 shows a method of manufacturing the semiconductor device according to this embodiment in the order of steps. First, as shown in FIG. 2A, after the sealing
第1の基板12は、搭載面に第1の基板電極21を有し、裏面に外部接続電極22を有する。第1の基板電極21は、金とニッケルと銅との合金(AuNiCu)又は銅等により形成すればよい。外部接続電極22には、はんだボール23を接続すればよいが、なくてもよい。封止フィルム14の貼り付けは、ローラー又は加圧装置等を用いて行えばよい。常温加圧、真空加圧又は加熱加圧等貼り付け条件は適宜選択すればよい。
The
第1の電子部品13は、例えば半導体基板に形成された半導体素子とすればよい。半導体基板の素子形成面の上に第1の部品電極31が形成されている。第1の部品電極31の上には、はんだバンプ等からなる第1の接続部材32が形成されている。はんだバンプはどのような方法で形成してもよい。例えば、スクリーン印刷により形成してもよく、めっき法により形成してもよく、フラックスを第1の部品電極31の上に供給した状態ではんだボールを搭載し、リフロー炉に投入する方法により形成してもよい。なお、はんだバンプの材質は、SnAg、SnAgCu、SnZn、SnZnBi、SnPb、SnBi又はSnAgBiIn等とすればよい。また、第1の部品電極31は、Au又はCu等とすればよく、スパッタリング法又はめっき法等を用いて形成すればよい。なお、第1の部品電極31の上に、金、銅又はインジウム等からなる突起電極(バンプ)をあらかじめ形成した後、その上にはんだバンプを形成してもよい。
The first
次に、図2(b)に示すように、第1の電子部品13を加熱した状態で押圧し、熱圧接を行う。この場合の加熱温度は、第1の接続部材32が溶融する温度以下とする。また、第1の電子部品13における第1の部品電極31が形成された面が、封止フィルム14の上面よりも沈み込み、第1の部品電極31の上に形成された第1の接続部材32の頭頂部が封止フィルム14を突き破って第1の基板電極21に届くまで加圧することが好ましい。このようにすれば、後の工程において第1の接続部材32のはんだ接合が容易となる。次に、はんだの融点以上まで昇温加熱を行い、封止フィルム14中に含まれるフラックス成分を活性化させると共に、第1の接続部材32を溶融させて第1の基板電極21と拡散接合する。第1の基板電極21の表面にあらかじめはんだをプリコートしてもよい。プリコートにより、大型基板又は反りが大きい薄型半導体素子の場合にもはんだ接合が容易となる。続いて、昇温加熱を継続することにより、封止フィルム14の硬化を行う。その後、はんだの凝固点以下になるまで冷却を行う。これにより、第1の基板電極21と第1の部品電極31とを第1の接続部材32を介して電気的に接続できる。なお、接続が形成された後もさらにはんだの融点以下の加熱を行うことが望ましい。この加熱処理により、第1の電子部品13の直下だけでなく封止フィルム14全体の硬化反応が促進され、より高い信頼性が得られるようになる。
Next, as shown in FIG. 2B, the first
次に、第1の基板12に複数個の機能ブロックを形成した場合には、図2(c)に示すように、ダイシング装置、打ち抜き金型装置又はレーザ切断装置等を用いて複数の機能ブロックに分割する。この製造方法によれば、封止フィルム14と第1の基板12の平面寸法が同一で端面精度に優れた半導体装置を得られる。
Next, when a plurality of functional blocks are formed on the
なお、第1の基板12を分割した後に、はんだの溶融及び封止フィルムの硬化を行ってもよい。この場合には、封止フィルム14が平面方向に熱収縮するため、第1の基板12の内部に納まり、半導体装置の外形寸法は第1の基板12の外形寸法と同一となる。
Note that after the
本実施形態の半導体装置は、シート状の封止フィルム14を用いている。このため、封止樹脂の厚さが制御しやすく、封止樹脂の厚さのばらつきによる反りの発生を防ぐことができる。従って、微細化が進んだ場合でも高い接続信頼性を実現することができる。
The semiconductor device of this embodiment uses a sheet-
以上の製造方法により製造した半導体装置を、断面研磨により断面解析した結果、はんだ接合部と封止フィルム14との密着性、第1の電子部品13における第1の部品電極31の形成面と封止フィルム14との密着性及び第1の基板12における第1の基板電極21の形成面と封止フィルム14との密着性はいずれも良好であった。また、温度85℃、湿度85%の条件下でストレス試験を行ったところ、1000サイクルにおいても安定した接続抵抗を確保することができた。このように、本実施形態の半導体装置は、フラックスを含む封止フィルムを用いることにより、均一な厚さの封止樹脂層を第1の基板12上の全面に形成することが容易にでき、半導体装置全体の反りを低減でき、高い接続信頼性を確保できる。
As a result of cross-sectional analysis of the semiconductor device manufactured by the above manufacturing method by cross-sectional polishing, the adhesion between the solder joint and the sealing
なお、本実施形態の半導体装置において、第1の電子部品13における第1の部品電極が形成された面と反対側の面(裏面)を封止フィルム14から露出するようにした方が、薄型化でき製造工程も少なくなり生産性を向上させることができる。但し、第1の電子部品13の全体が封止フィルム14に覆われるようにした方が、より接続信頼性が向上するという利点がある。第1の電子部品13の全体を樹脂封止する場合には、第1の電子部品13の裏面が封止フィルム14から露出する状態とした後、封止フィルム14の上に第2の封止フィルムを貼り付けて硬化させればよい。
In the semiconductor device of this embodiment, it is thinner if the surface (back surface) opposite to the surface on which the first component electrode is formed in the first
図1においては、第1の基板12の上に、1つの素子が搭載されている例を示している。しかし、図3に示すように、第1の基板12の上に複数の素子が搭載されていてもよい。図3は、第1の電子部品13が半導体素子13Aと、ウェハレベルチップサイズパッケージ13Bと、チップコンデンサー13Cとを含む例を示している。この他、抵抗素子、コイル及び発光ダイオード等のどのような素子を搭載することも可能である。
FIG. 1 shows an example in which one element is mounted on the
このように複数の素子を搭載する場合には、第1の基板12が大型化する場合がある。第1の基板12が大型化した場合には、封止フィルム14の線膨張係数と第1の基板12の線膨張係数を合わせるようにすることが好ましい。封止フィルム14の線膨張係数を調整するためには、フィラーの充填量を変化させればよい。フィラーの充填量が少ないと封止フィルム14の線膨張係数が大きくなり半導体装置の反りが大きくなる。一方、フィラーの充填量が多すぎると封止フィルム14がもろくなり、熱硬化後の引っ張り応力により割れが発生する。このため、フィラーの充填量は適切な範囲に設定する必要がある。例えば、第1の基板12のサイズが20mm×20mmの場合に、封止フィルム14のフィラー充填量を50質量%〜60質量%とすると、半導体装置の反り量は約0.09mmとなった。反り量が小さいため、マザーボードへ実装した後に、オープン不良等の不具合は認められなかった。
Thus, when mounting a some element, the 1st board |
また、第1の電子部品13が高速演算処理チップのような発熱量が大きい素子の場合には、図4に示すように放熱板15を設けてもよい。放熱板15は、ステンレス、銅、アルミニウム又は金等の熱伝導率の高い材料により形成すればよい。また、放熱板15は図4(a)に示すように平板としてもよいが、図4(b)に示すような柱状の放熱フィン有する放熱板15Bとしたり、図4(c)に示すように、針状の放熱フィンを有する放熱板15Cとしたりすれば、さらに放熱性を高くすることができ好ましい。放熱フィンは放熱板本体と一体に形成しても、放熱板本体に貼り付けてもよい。
Further, when the first
放熱性を要求される場合には、封止フィルム14に充填するフィラーを、熱伝導性が高いアルミナ、窒化珪素又は炭化珪素等の無機フィラーとすることが好ましい。
When heat dissipation is required, it is preferable that the filler filled in the sealing
このような構成とすれば、フラックスを含む樹脂が均一な膜厚で第1の基板12上の全面に接着され、第1の電子部品13を覆うことができる。さらに、線膨張係数が低い放熱板15と第1の基板12とにより封止フィルム14及び第1の電子部品13を挟み込むので、半導体装置全体の反りをさらに低減でき、高い接続信頼性を確保すると共に放熱性も向上させることができる。
With such a configuration, the resin containing the flux is adhered to the entire surface of the
(一実施形態の一変形例)
図5は一実施形態の一変形例に係る半導体装置の断面構成を示している。図5において図1と同一の構成要素には同一の符号を附すことにより説明を省略する。本変形例の半導体装置は、封止フィルム14の上に第2の基板16が搭載されている。第2の基板16の搭載面には第2の電子部品17が搭載されている。第2の電子部品17は、例えば半導体素子であり、第2の部品電極71を有し、第2の部品電極71が形成された面を上にして第2の基板16の上にダイボンディングされている。第2の基板16の搭載面には、第2の基板電極61が形成され、第2の基板電極61と第2の部品電極71とは、ワイヤ72により電気的に接続されている。第2の基板16の搭載面の上には、第2の電子部品17及びワイヤ72を覆うように封止樹脂18が形成されている。
(One Modification of One Embodiment)
FIG. 5 shows a cross-sectional configuration of a semiconductor device according to a modification of the embodiment. In FIG. 5, the same components as those of FIG. In the semiconductor device of this modification, the
第2の基板16の搭載面と反対側の面(裏面)には、第2の基板接続電極65が形成されている。第1の基板12の搭載面には、第1の基板接続電極25が形成されており、第1の基板接続電極25と第2の基板接続電極65とは対向し、第2の接続部材66を介して電気的に接続されている。第2の接続部材66は、例えば、銅ボールとはんだとにより形成されている。
A second
本変形例の半導体装置は、第1の基板12と第2の基板16との間に隙間なく封止フィルム14が充填されている。このため、半導体装置に熱が加わった際の膨張及び収縮量並びに熱応力が小さくなり、半導体装置の反りを低減できる。従って、高い接続信頼性を確保することが可能となる。また、水蒸気等の水分の侵入を防ぐことができるので、電極部の腐食及びマイグレーション等の不具合の発生を抑えることができる。従って、高温高湿下においても、高い接続信頼性を確保できるという効果も得られる。
In the semiconductor device of this modification, the sealing
次に、本変形例の半導体装置の製造方法について説明する。図6は、本変形例に係る半導体装置の製造方法を工程順に示している。まず、先に図2(a)及び(b)に示したようにして、第1の基板12の上に第1の電子部品13を載置し、第1の基板電極21と第1の部品電極31とを第1の接続部材32を介して接続する。
Next, a method for manufacturing the semiconductor device according to this modification will be described. FIG. 6 shows a method of manufacturing a semiconductor device according to this modification in the order of steps. First, as shown in FIGS. 2A and 2B, the first
次に、図6(a)に示すように、まず、第2の基板16の搭載面の上に第2の電子部品17を搭載する。第2の電子部品17はどのようなものでもよいが、例えばメモリ等とすればよい。第2の電子部品17の第2の基板16への搭載は通常のダイボンディングにより行えばよい。続いて、第2の電子部品17及びワイヤ72を覆うように、第2の基板16の搭載面の上に封止樹脂18を形成する。次に、第2の基板16の裏面にバンプからなる第2の接続部材66を形成する。第2の接続部材66は、例えば、第2の基板16に形成された第2の基板接続電極65にスクリーン印刷によりはんだを供給した後、銅ボールを搭載し、リフロー炉等を用いて加熱して形成すればよい。なお、第2の接続部材66は銅ボールからなるバンプに限らず、金又はアルミニウム等からなるスタッドバンプ、はんだ、金、金―ニッケル、銅又はインジウム等からなるめっきバンプとしてもよい。この後、第2の基板接続電極65と、第1の基板12に形成された第1の基板接続電極25とが対向するように、第2の基板16を封止フィルム14の上に搭載する。
Next, as shown in FIG. 6A, first, the second
次に、図6(b)に示すように、加熱により封止フィルム14を軟化させ、第2の接続部材66が封止フィルム14を押しのけながら、第1の基板接続電極25と接触するまで第2の基板16を加圧して押し込む。なお、第1の基板接続電極25にはあらかじめはんだをプリコートしておくことが好ましい。続いて、加熱を行い、封止フィルム14に含まれるフラックス成分を活性化し、電極表面の酸化皮膜を除去する。さらにはんだの融点以上まで加熱すると、銅とはんだが拡散接合されると共に、封止フィルム14の硬化反応が始まる。さらに、加熱し封止フィルム14の硬化反応を完了させる。
Next, as shown in FIG. 6B, the sealing
次に、図6(c)に示すように、ブロック毎にダイシングブレード等により分割する。 Next, as shown in FIG. 6C, each block is divided by a dicing blade or the like.
なお、封止フィルム14を第1の基板上の全面に貼り付ける場合について説明したが、必要な部分のみに局所的に貼り付けてもかまわない。このように、本変形例の製造方法によれば、第1の基板12と第2の基板16とが容易に隙間なく接着できるので、半導体装置全体の反りが低減でき、高い接続信頼性を確保できる。
In addition, although the case where the sealing
また、第1の基板12の上に第2の基板16を搭載した後、分割を行ったが、図7に示すように、先に分割を行ってもよい。図7(a)に示すように、第1の基板12の上に第1の電子部品を搭載した後、金型を用いて打ち抜きを行うことにより、第1の基板12を複数の部分に分割する。
Further, the division is performed after the
次に、図7(b)に示すように、各部分に対して、第2の基板16を位置合わせする。次に、図7(c)に示すように、第2の基板16を加熱加圧することにより、第2の接続部材66を封止フィルム14中に押し込んだ後、はんだを接合すると共に、封止フィルム14の硬化を行う。これにより、封止フィルムは硬化収縮し、基板12の外形寸法内に収まる。
Next, as shown in FIG.7 (b), the 2nd board |
本変形例の場合においても、第1の基板12の上に第1の電子部品13として複数の素子が搭載されていてもよい。また、第2の電子部品17は、半導体素子以外の電子部品であってもよく、さらに複数の素子を含む構成としてもよい。第2の電子部品17をワイヤボンディングにより第2の基板16に搭載する例を示したが、フリップチップ実装等により搭載してもよい。
Also in the case of this modification, a plurality of elements may be mounted on the
本発明に係る半導体装置及びその製造方法は、半導体素子等の電子部品と基板との接続信頼性を向上させた半導体装置を実現でき、特に狭ピッチ化された半導体素子等を搭載した半導体装置及びその製造方法等として有用である。 A semiconductor device and a manufacturing method thereof according to the present invention can realize a semiconductor device with improved connection reliability between an electronic component such as a semiconductor element and a substrate, and in particular, a semiconductor device equipped with a semiconductor element or the like having a narrow pitch, and It is useful as a manufacturing method thereof.
12 第1の基板
13 第1の電子部品
13A 半導体素子
13B ウェハレベルチップサイズパッケージ
13C チップコンデンサー
14 封止フィルム
15 放熱板
16 第2の基板
17 第2の電子部品
18 封止樹脂
21 第1の基板電極
22 外部接続電極
23 ボール
25 第1の基板接続電極
31 第1の部品電極
32 第1の接続部材
61 第2の基板電極
65 第2の基板接続電極
66 第2の接続部材
71 第2の部品電極
72 ワイヤ
12
Claims (12)
第1の部品電極を有し、前記第1の基板電極と前記第1の部品電極とを対向させて前記第1の基板の上に搭載された第1の電子部品と、
前記第1の基板電極と前記第1の部品電極とを電気的に接続する第1の接続部材と、
前記第1の基板上の全面を覆い、フラックス成分を含有する封止フィルムとを備え、
前記第1の電子部品は、側面全体が前記封止フィルムに覆われていることを特徴とする半導体装置。 A first substrate having a first substrate electrode;
A first electronic component having a first component electrode and mounted on the first substrate with the first substrate electrode and the first component electrode facing each other;
A first connecting member for electrically connecting the first substrate electrode and the first component electrode;
Covering the entire surface of the first substrate, comprising a sealing film containing a flux component,
The first electronic component is a semiconductor device characterized in that the entire side surface is covered with the sealing film.
前記第1の基板は第1の基板接続電極を有し、
前記第2の基板は第2の基板接続電極を有し、
前記第1の基板接続電極と前記第2の基板接続電極とは、互いに対向し且つ第2の接続部材を介して電気的に接続されていることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。 A second substrate mounted on the sealing film;
The first substrate has a first substrate connection electrode;
The second substrate has a second substrate connection electrode;
The first substrate connection electrode and the second substrate connection electrode face each other and are electrically connected via a second connection member. 2. A semiconductor device according to item 1.
第1の電子部品に形成された第1の部品電極の上に第1の接続部材を接続する工程(b)と、
前記工程(b)よりも後に、前記第1の電子部品を前記封止フィルム中に埋設すると共に、前記第1の基板電極と前記第1の接続部材とを電気的に接続する工程(c)と、
前記工程(c)よりも後に、前記封止フィルムを加熱して硬化する工程(d)とを備え、
前記工程(c)では、前記第1の電子部品の側面全体が前記封止フィルムに覆われるようにすることを特徴とする半導体装置の製造方法。 A step (a) of attaching a sealing film containing a flux on a first substrate having a first substrate electrode;
Connecting the first connecting member on the first component electrode formed on the first electronic component (b);
Step (c) of embedding the first electronic component in the sealing film and electrically connecting the first substrate electrode and the first connecting member after the step (b). When,
A step (d) of heating and curing the sealing film after the step (c);
In the step (c), the entire side surface of the first electronic component is covered with the sealing film.
前記工程(c)よりも後で且つ前記工程(d)よりも前に、前記第2の基板接続電極と接続された前記第2の接続部材を前記封止フィルム中に埋設すると共に、前記第1の基板に形成された第1の基板接続電極と前記第2の接続部材とを電気的に接続する工程(f)とをさらに備えていることを特徴とする請求項9に記載の半導体装置の製造方法。 A step (e) of connecting a second connection member on the second substrate connection electrode formed on the second substrate;
The second connection member connected to the second substrate connection electrode is embedded in the sealing film after the step (c) and before the step (d), and the first 10. The semiconductor device according to claim 9, further comprising a step (f) of electrically connecting a first substrate connection electrode formed on one substrate and the second connection member. Manufacturing method.
前記工程(d)よりも後に、前記第1の基板を少なくとも1つの第1の電子部品が搭載された複数のブロックに分割することを特徴とする請求項9〜11のいずれか1項に記載の半導体装置の製造方法。 A plurality of the first electronic components;
12. The method according to claim 9, wherein after the step (d), the first substrate is divided into a plurality of blocks on which at least one first electronic component is mounted. Semiconductor device manufacturing method.
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JP2012204631A (en) * | 2011-03-25 | 2012-10-22 | Fujitsu Semiconductor Ltd | Semiconductor device, semiconductor device manufacturing method and electronic apparatus |
US9263426B2 (en) | 2012-09-26 | 2016-02-16 | Apple Inc. | PoP structure with electrically insulating material between packages |
JP2018525807A (en) * | 2015-07-22 | 2018-09-06 | インテル・コーポレーション | Multi-layer package |
KR20220036724A (en) * | 2020-09-16 | 2022-03-23 | (주)파트론 | Package module |
WO2024203581A1 (en) * | 2023-03-31 | 2024-10-03 | ソニーセミコンダクタソリューションズ株式会社 | Display body and electronic apparatus |
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JP2003197680A (en) * | 2001-12-25 | 2003-07-11 | Matsushita Electric Works Ltd | Method of manufacturing semiconductor device |
JP2003347722A (en) * | 2002-05-23 | 2003-12-05 | Ibiden Co Ltd | Multilayer electronic parts mounting substrate and its fabricating method |
JP2004327556A (en) * | 2003-04-22 | 2004-11-18 | Matsushita Electric Works Ltd | Semiconductor device and its manufacturing process |
KR100887475B1 (en) * | 2007-02-26 | 2009-03-10 | 주식회사 네패스 | Semiconductor package and fabrication method thereof |
WO2008120564A1 (en) * | 2007-03-28 | 2008-10-09 | Nec Corporation | Mounting structure of electronic component and method for mounting electronic component |
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JP2012204631A (en) * | 2011-03-25 | 2012-10-22 | Fujitsu Semiconductor Ltd | Semiconductor device, semiconductor device manufacturing method and electronic apparatus |
US9263426B2 (en) | 2012-09-26 | 2016-02-16 | Apple Inc. | PoP structure with electrically insulating material between packages |
JP2018525807A (en) * | 2015-07-22 | 2018-09-06 | インテル・コーポレーション | Multi-layer package |
KR20220036724A (en) * | 2020-09-16 | 2022-03-23 | (주)파트론 | Package module |
KR102423619B1 (en) * | 2020-09-16 | 2022-07-22 | (주)파트론 | Package module |
WO2024203581A1 (en) * | 2023-03-31 | 2024-10-03 | ソニーセミコンダクタソリューションズ株式会社 | Display body and electronic apparatus |
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