JP2012074497A - Circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board which can reduce local stress applied to a circuit chip.SOLUTION: A circuit board 10 in which a wiring part including a conductor pattern 30 and an interlayer connection veer 41 is provided on an insulation substrate 20, comprises a heat sink 60 provided on one face of the insulation substrate 20 perpendicular to a thickness direction of the insulation substrate 20, a semiconductor chip 50 embedded in the insulation substrate 20 and having a dummy electrode 51b disposed on one face on the heat sink 60 side and an electrode 51a disposed on a rear face and electrically connected to the wiring part, heat radiation connection veer 42 thermally connecting the dummy electrode 51b of the semiconductor chip 50 with the heat sink 60, and a plate-like member 90 disposed between the semiconductor chip 50 and the heat sink 60 and connected to the semiconductor chip 50 and the heat sink 60 via the heat radiation connection veer 42 and having heat conductivity higher than that of the insulation substrate 20 and thicker than the conductor pattern 30.

Description

  The present invention relates to a circuit board in which a circuit chip is embedded in an insulating base material containing a thermoplastic resin.

  Conventionally, as an example of a circuit board in which a circuit chip is embedded in an insulating base material containing a thermoplastic resin, for example, a multilayer board described in Patent Document 1 is known.

  In this multilayer substrate, an electrical element (circuit chip) is disposed in a thermoplastic resin (insulating base material), and an electrode of the electrical element is connected to a thermoplastic resin via a connection member in which a via hole is filled with a connection material. The conductor pattern is electrically connected to the conductor pattern.

JP 2006-93439 A

  Incidentally, some electric elements embedded in a multilayer substrate generate heat during use. In order to dissipate the heat generated by the electric element, it is conceivable to provide a heat dissipating member that is thermally connected to the electric element via a connecting member. In addition, the connection material for thermally connecting the electric element and the heat radiating member may be connected to a part of the surface of the electric element facing the heat radiating member.

  However, in the case of such a structure, there is a problem that a stress is locally applied to the electric element due to a difference in linear expansion coefficient between the insulating base and the connecting member.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce local stress on a circuit chip in a circuit board in which the circuit chip is embedded in an insulating base material including a thermoplastic resin.

In order to achieve the above object, the circuit board according to claim 1,
A circuit board in which an insulating base material containing a thermoplastic resin is provided with a wiring portion including a conductor pattern and an interlayer connection via,
A heat dissipating member disposed on one surface of the insulating substrate perpendicular to the thickness direction of the insulating substrate;
Including at least one circuit element, having a heat radiation electrode on one surface of the heat radiation member side, and having an electrical connection electrode electrically connected to the wiring portion on at least one of the one surface and the back surface of the one surface; A circuit chip embedded in an insulating substrate and sealed with a thermoplastic resin of the insulating substrate;
A heat dissipating connection via provided on the insulating substrate and thermally connecting the heat dissipating electrode of the circuit chip and the heat dissipating member;
The circuit chip is connected to the circuit chip and the heat dissipating member via the heat dissipation connecting via, and has a higher thermal conductivity than the insulating base material, thicker than the conductor pattern in the thickness direction, and embedded in the insulating base material. And a flat plate-like member arranged between the heat dissipation member,
The flat plate member is characterized by having a size equal to or larger than the circuit element formation region in the direction perpendicular to the thickness direction so as to face at least the entire circuit element formation region on one surface of the circuit chip.

  By doing so, the total amount of displacement between the circuit chip and the heat radiating member that occurs during a temperature change is reduced as compared with the case where a heat radiating connection member is provided instead of a flat plate-like member at a position facing the circuit element. be able to. Therefore, it is possible to reduce local stress on at least a portion where the circuit element is arranged in the circuit chip.

  In addition, as shown in claim 2, the flat plate member may have a linear expansion coefficient in the thickness direction smaller than the linear expansion coefficient in the thickness direction of the insulating base material. By doing so, the stress can be further reduced.

As shown in claim 3,
On one surface of the circuit chip, an electrode for electrical connection is provided together with an electrode for heat dissipation,
A conductor pattern as an external connection electrode is provided on the surface opposite to the heat dissipating member placement surface of the insulating base,
The electrode for electrical connection provided on one surface of the circuit chip and the electrode for external connection may be electrically connected by the wiring portion.

  By doing in this way, a circuit chip is preferable since an electrical connection can be made even on one surface facing the heat dissipation member. Further, when an electrical connection electrode is provided together with a heat dissipation electrode on one surface of the circuit chip, it is necessary to stack the heat dissipation connection via in the thickness direction. Stress increases. However, by providing a flat plate-like member, even if the electrode for electrical connection is provided along with the heat radiation electrode on one surface of the circuit chip, local stress on at least the part where the circuit element is arranged in the circuit chip is reduced. can do. That is, the flat plate member of the present invention is particularly effective in such a structure.

For example, as shown in claim 4,
An electrical connection electrode is provided in the peripheral region on one surface of the circuit chip, and a heat dissipation electrode is provided in a region surrounded by the electrical connection electrode,
The flat plate member may have the same size as the heat radiation electrode forming region in the direction perpendicular to the thickness direction so as to face the heat radiation electrode forming region.

  By doing so, it is possible to employ a circuit chip in which an electrical connection electrode is provided in a peripheral region on one surface of the circuit chip.

  According to a fifth aspect of the present invention, the flat plate member may have a size equal to or larger than the one surface in a direction perpendicular to the thickness direction so as to face the entire surface of the circuit chip.

  By doing in this way, a local stress can be reduced in the whole one surface facing the heat radiating member of a circuit chip.

  According to a sixth aspect of the present invention, an electrical connection electrode and a heat dissipation electrode may be provided in a region facing the flat plate member on one surface of the circuit chip.

  By doing so, the circuit chip is preferable because electrical connection can be made even at a position facing the flat plate member. Further, when an electrical connection electrode is provided together with a heat dissipation electrode on one surface of the circuit chip, it is necessary to stack the heat dissipation connection via in the thickness direction. Stress increases. However, by providing a flat plate-like member, even if the electrode for electrical connection is provided along with the heat radiation electrode on one surface of the circuit chip, local stress on at least the part where the circuit element is arranged in the circuit chip is reduced. can do. That is, the flat plate member of the present invention is particularly effective in such a structure.

  According to another aspect of the present invention, an electrical connection electrode is provided on the back surface of the circuit chip, and the electrical connection electrode and the external connection electrode provided on the back surface of the circuit chip are electrically connected by the wiring portion. You may be made to do.

  By doing so, even a double-sided electrode type circuit chip can be adopted as the circuit chip.

  In addition, depending on the material of a flat member, it is also considered that heat dissipation falls. Therefore, as shown in claim 8, the thermal conductivity of the flat plate member may be equal to or higher than the thermal conductivity of the heat radiating connection via.

  By doing in this way, the local stress with respect to a circuit chip can be reduced, suppressing the fall of heat dissipation.

  According to a ninth aspect of the present invention, the linear expansion coefficient in the direction perpendicular to the thickness direction may be equal between the flat plate member and the circuit chip.

  By doing so, it is possible to reduce the lateral stress on the circuit chip due to a thermal load such as a cooling / heating cycle. The lateral direction is a direction perpendicular to the thickness direction of the circuit chip.

It is sectional drawing which shows schematic structure of the circuit board in embodiment of this invention. It is a top view which shows schematic structure of the circuit board shown in FIG. It is sectional drawing which shows the preparatory process of the resin film laminated | stacked on the board | substrate with which the semiconductor chip was mounted among the manufacturing processes of the circuit board shown in FIG. FIG. 2 is a cross-sectional view showing a step of flip-chip mounting a semiconductor chip on a substrate in the circuit board manufacturing process shown in FIG. 1. In the process shown in FIG. 4, it is a top view which shows the state which affixed the 2nd film on the pad formation surface of a board | substrate. It is sectional drawing which shows a lamination process among the manufacturing processes of the circuit board shown in FIG. It is sectional drawing which shows a pressurization / heating process among the manufacturing processes of the circuit board shown in FIG. FIG. 9 is a cross-sectional view illustrating a schematic configuration of a circuit board in Modification 1; It is a top view which shows schematic structure of the circuit board shown in FIG. FIG. 10 is a cross-sectional view illustrating a schematic configuration of a circuit board in Modification 2.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention. In addition, the thickness direction of the insulating base material 20 (in other words, the lamination direction of a plurality of resin films) is simply referred to as the thickness direction, and the direction perpendicular to the thickness direction is simply referred to as the vertical direction.

  As shown in FIG. 1, the circuit board 10 according to the present embodiment is embedded in the insulating base material 20, that is, embedded in the insulating base material 20 as a basic constituent element containing a semiconductor chip (circuit chip) 50. The semiconductor chip 50, the wiring portion (conductor pattern 30, interlayer connection via 41) provided on the insulating base 20, the heat sink (heat radiation member) 60, the heat radiation connection via 42, and the flat plate member 90 are provided.

  The insulating base material 20 is made of an electrically insulating material. In the example shown in FIG. 1, the conductive pattern 30, the interlayer connection via 41, the semiconductor chip 50, the heat sink 60, the heat dissipation connection via 42, In addition to serving as a base material for holding the flat plate member 90 in a predetermined position, the semiconductor chip 50 is held and protected therein.

  The insulating base material 20 mainly contains a resin, and at least a thermoplastic resin as the resin. A plurality of resin films including a thermoplastic resin film are laminated, and are bonded and integrated by pressing and heating. Being done. The reason for including the thermoplastic resin is that, when forming the insulating base material 20 in a batch in the pressurizing / heating process described later, it is resistant to high temperatures and uses the softened thermoplastic resin as an adhesive and a sealing material. is there.

  For this reason, the plurality of resin films may include a thermoplastic resin film so as to be positioned at least every other sheet in a laminated state. For example, it is good also as a structure containing only a thermoplastic resin film, and good also as a structure containing a thermosetting resin film with a thermoplastic resin film.

  As the thermoplastic resin film, at least one of a film containing an inorganic material such as glass fiber and aramid fiber and a film made of a thermoplastic resin not containing an inorganic material can be employed together with the thermoplastic resin. Similarly, as the thermosetting resin film, at least one of a film containing the inorganic material and a film made of a thermosetting resin not containing the inorganic material can be employed together with the thermosetting resin.

  As shown in FIG. 1, the insulating base material 20 according to the present embodiment has a thermosetting resin film 21a, a thermoplastic resin film 22a, a thermosetting resin film 21b, and a thermoplastic resin from the one surface 20a side in the thickness direction. A total of eight resin films are laminated in the order of the film 22b, the thermosetting resin film 21c, the thermoplastic resin film 22c, the thermosetting resin film 21d, and the thermoplastic resin film 22d. That is, the insulating base material 20 is configured by alternately laminating thermoplastic resin films and thermosetting resin films.

  Moreover, the film which consists of thermosetting polyimide (PI) which does not contain inorganic materials, such as glass fiber, is employ | adopted as the thermosetting resin films 21a-21d. On the other hand, as the thermoplastic resin films 22a to 22d, 30% by weight of polyetheretherketone (PEEK) and polyetherimide (PEI) not containing inorganic materials such as glass fibers and inorganic fillers for adjusting the linear expansion coefficient. A resin film composed of 70% by weight is employed. The thermoplastic resin films 22a to 22d have a linear expansion coefficient in the vertical direction of several tens to two hundred and several tens of degrees of about several tens to one hundred and several tens [ppm / ° C.], and several tens to two and several tens The linear expansion coefficient in the thickness direction at a temperature is about several tens to two hundreds [ppm / ° C.].

  Among the resin films described above, the thermosetting resin film 21b corresponds to a substrate on which the semiconductor chip 50 is mounted, and the thermoplastic resin films 22b and 22c are provided between the semiconductor chip 50 and the thermosetting resin film 21b. It corresponds to what is sealed.

  The conductor pattern 30 is formed by patterning a conductor foil, and is used as a wiring portion that electrically connects the semiconductor chip 50 and the outside.

  On the other hand, the interlayer connection via 41 is a resin film in which via holes (through holes) provided along the thickness direction are filled with a conductive paste, and the conductive particles in the conductive paste are sintered by pressing and heating. It is made. That is, the interlayer connection via 41 can be restated as a sintered body for interlayer connection. The interlayer connection via 41 is also used as a wiring portion that electrically connects the semiconductor chip 50 and the outside together with the conductor pattern 30.

  In the present embodiment, the conductor pattern 30 and the interlayer connection via 41 constitute a wiring portion that electrically connects the electrode (electric connection electrode) 51 a of the semiconductor chip 50 and the external connection electrode 33. Further, the dummy electrode (heat radiating electrode) 51b of the semiconductor chip 50 and the heat sink 60 are thermally connected by the heat radiating connection via 42 which is an interlayer connection via different from the interlayer connection via 41 constituting the wiring portion. A heat dissipating wiring portion is configured. That is, the heat radiating connection via 42 is provided in the insulating base material 20 and thermally connects the dummy electrode 51 b of the semiconductor chip 50 and the heat sink 60. The interlayer connection via 41 and the heat dissipation connection via 42 have a linear expansion coefficient in the vertical direction of about 20 [ppm / ° C.].

  Specifically, the conductor pattern 30 is formed by patterning a copper (Cu) foil. The conductor pattern 30 includes a pad 31 corresponding to the electrode 51a of the semiconductor chip 50, a horizontal wiring portion 32 extending in the vertical direction, and the like. Further, an external connection electrode 33 provided for connection with an external device is also included as a part of the conductor pattern 30. In addition, the conductor pattern formed by patterning this copper foil has a linear expansion coefficient of about a dozen [ppm / ° C.] in the vertical direction.

  The pads 31 are provided at a pitch that matches the pitch of the corresponding electrodes 51 a of the semiconductor chip 50. Although not shown, in the present embodiment, the electrodes 51a are arranged in a row of rectangular rings with 10 sides, and the pads 31 corresponding to the electrodes 51a include a plurality of pads 31 corresponding to the arrangement of the electrodes 51a. As shown in FIG. 5, it is provided in a rectangular ring shape. Then, as shown in FIG. 1, each pad 31 is drawn out (re-wired) to the outside or inside of the rectangular ring (the outside is illustrated in FIG. 1) by the horizontal wiring portion 32 provided in the same layer. Thus, the interlayer connection via 41 is connected. In FIG. 5, the horizontal wiring portion 32 is omitted for convenience. The conductor pattern 30 is externally provided for connection between a circuit element (not shown) embedded in the insulating base material 20 together with the semiconductor chip 50 and an external device, as shown on the left and right sides in FIG. A conductor pattern 30 that electrically connects the connection electrode 33 via the interlayer connection via 41 may also be included.

  In the present embodiment, the interlayer connection via 41 constituting the wiring portion is made of an Ag—Sn alloy. A wiring portion is configured including the interlayer connection via 41, the horizontal wiring portion 32, and the pad 31. Similarly, the heat radiating connection via 42 for thermally connecting the dummy electrode 51b and the heat sink 60 is also made of an Ag—Sn alloy. A heat radiation wiring portion is configured including the heat radiation connection via 42 and a flat plate member 90 which will be described later. Note that the heat dissipation wiring portion may include a conductor pattern that is not electrically connected to the semiconductor chip 50.

  At the interface between the conductor pattern 30 made of Cu and the interlayer connection via 41 made of an Ag—Sn alloy, a metal diffusion layer (Cu—Sn alloy layer) formed by mutual diffusion of Cu and Sn is formed. The connection reliability between the conductor pattern 30 and the interlayer connection via 41 is improved.

  Further, Cu and Au diffuse to each other at the interface between the pad 31 as the conductor pattern 30 made of Cu and the connection portion 52 made of gold (Au) provided on the electrode 51 a of the semiconductor chip 50. A metal diffusion layer (Cu—Au alloy layer including a CuAu 3 alloy) is formed, whereby the connection reliability between the pad 31 and the connection portion 52 is improved.

  In the present embodiment, the external connection electrode 33 is formed as the conductor pattern 30 on the inner surface of the thermosetting resin film 21 a that forms the surface layer on the one surface 20 a side of the insulating substrate 20.

  The semiconductor chip 50 is an IC chip in which circuit elements such as transistors, diodes, band gap circuits, high-precision resistors (thin film resistors) and capacitors are integrated on a semiconductor substrate such as silicon to form a circuit (large scale integrated circuit). (Bare chip). As described above, the semiconductor chip 50 is also integrated with circuit elements whose characteristics fluctuate due to stress such as a band gap circuit and a high-precision resistor (thin film resistor). An electrode is formed on the surface of the semiconductor chip 50. In the present embodiment, as shown in FIG. 1, a dummy electrode 51 b that is not connected to the above-described circuit on one surface of the semiconductor chip 50 and does not provide an electrical connection function, and the back surface (opposite surface on one surface) of the semiconductor chip 50. And an electrode 51a electrically connected to the circuit. Further, the semiconductor chip 50 is sealed by the insulating base material 20 described above.

  That is, the semiconductor chip 50 includes at least one circuit element, has a dummy electrode 51b on one surface on the heat sink 60 side, has an electrode 51a electrically connected to the wiring portion on the back surface, and has an insulating substrate. It is embedded in the material 20 and sealed with the thermoplastic resins 21b and 21c of the insulating base material 20.

  Thus, the electrode 51a may be provided on the back surface of the semiconductor chip 50, and the electrode 51a provided on the back surface of the semiconductor chip 50 and the external connection electrode 33 may be electrically connected by the wiring portion. . By doing in this way, even if it is a double-sided electrode type semiconductor chip 50 as the semiconductor chip 50, it is employable.

A plurality of electrodes 51a are formed on the back surface side of the semiconductor chip 50, and connection portions 52 made of Au are connected to the electrodes 51a. All the thickness direction of the portion facing the connecting portion 52 of the electrode 51a is made of Au-Al alloy (mainly _Au 4 Al alloy), and aluminum (Al) so as not included in the metal itself. In other words, all the thickness directions of the portion of the electrode 51a facing the connecting portion 52 are all the portions of the electrode 51a in the thickness direction immediately below (or immediately above) the connecting portion 52 (the interface with the connecting portion 52 and the interface). (All parts in the thickness direction from the interface). It can also be said that the electrode 51 a is a portion sandwiched between the semiconductor chip 50 and the connection portion 52. Hereinafter, the electrode 51a is indicated as a portion immediately below the connection portion 52 made of Au.

  Further, a portion of the electrode 51a that is not a region directly below the connection portion 52 (for example, a portion covered with a protective film) is configured to contain Al alone.

In the electrode 51a, if Al remains alone in a portion immediately below the connection portion 52 made of Au, the Au in the connection portion 52 adjacent to the Al in the electrode 51a is solid-phase diffused in a high temperature use environment, and Au ₅ Al ₂ is generated. The growth rate of the _Au 5 Al2 is much faster than the _Au 4 Al, Accordingly, without diffusion of Au is in time for the generation of _Au 5 Al _2, resulting in Kirkendall voids at the interface of the connecting portion 52 and the electrode 51a . In addition, cracks occur starting from Kirkendall void.

On the other hand, in the present embodiment, in the electrode 51a, the portion immediately below the connection portion 52 made of Au does not contain Al as a single metal, but mainly contains Au ₄ Al alloy which is the final product of Au—Al alloy. It is out. Therefore, it is possible to suppress the occurrence of Kirkendall voids and, in turn, cracks even in a high temperature use environment.

  In addition, the pitch (interval) between the electrodes 51 a is narrower than the pitch of the electrodes (51 b) formed on the opposite surface of the semiconductor chip 50. Specifically, the pitch is several tens of μm (for example, 60 μm pitch).

  On the other hand, a dummy electrode 51b made of a Ni-based material is formed on the surface of the semiconductor chip 50 opposite to the surface on which the electrode 51a is formed. A corresponding heat radiation connection via 42 is connected to the dummy electrode 51b. At the interface between the dummy electrode 51b made of Ni and the heat radiating connection via 42 made of an Ag—Sn alloy, a metal diffusion layer (Ni—Sn alloy layer) formed by mutually diffusing Sn and Ni is formed. As a result, the connection reliability between the dummy electrode 51b and the heat radiation connection via 42 is improved. The dummy electrodes 51b are formed with a pitch of, for example, a unit of 100 μm.

  As described above, the semiconductor chip 50 includes the electrode 51a that provides an electrical connection function, and also includes a dummy electrode 51b that does not provide an electrical connection function.

  The heat sink 60 is made of a metal material such as Cu, and is used to radiate heat generated by the operation of the elements formed on the semiconductor chip 50 to the outside. As such a heat sink 60, a heat radiating fin or the like may be employed. In the present embodiment, a flat heat sink 60 made of Cu is employed. The heat sink 60 is fixed to the one surface 20b of the insulating substrate 20 by the thermoplastic resin film 22d being in close contact with the heat sink 60.

  The heat sink 60 is connected to one end of a heat radiating connection via 42 formed in the thermoplastic resin film 22d. In the present embodiment, a metal diffusion layer (C-Sn alloy layer) in which Cu and Sn are diffused mutually is formed at the interface between the heat sink 60 made of Cu and the heat radiation connecting via 42 made of an Ag-Sn alloy. Thus, the connection reliability between the heat dissipation connection via 42 (heat dissipation wiring portion) and the heat sink 60 is improved.

  In the present embodiment, the heat generated in the semiconductor chip 50 is transmitted from the dummy electrode 51 c to the heat sink 60 through the heat radiation wiring portion including the heat radiation connection via 42 and the flat plate member 90. For this reason, the heat dissipation is improved.

  In addition, a conductive member such as a plating film is disposed on the one surface 20a side of the insulating base material 20 in a hole formed with the external connection electrode 33 as a bottom surface from the one surface 20a side, and a solder ball 70 is placed on the conductive member. Is formed.

  Here, the flat plate member 90 which is a characteristic part of the present invention will be described.

  The flat plate member 90 is a flat plate member made of metal (Cu, Cu alloy, etc.), semiconductor (Si, etc.), resin, or the like. Further, the flat plate member 90 is higher in thermal conductivity than the insulating base material 20 and thicker in the thickness direction than the conductor pattern 30. Here, Cu is adopted as the material of the flat plate member 90.

  The flat plate member 90 is connected to the semiconductor chip 50 and the heat sink 60 through the heat radiation connection via 42. Specifically, as shown in FIG. 1, the flat plate member 90 is connected to the semiconductor chip 50 via the heat dissipation connection via 42 and also connected to the heat sink 60 via the heat dissipation connection via 42. . Further, the flat plate member 90 is disposed between the semiconductor chip 50 and the heat sink 60 while being embedded in the insulating base material 20. That is, the flat plate member 90 has a flat surface on both sides, and one flat surface faces one surface of the semiconductor chip 50 (surface on the heat sink 60 side), and the other flat surface faces one surface (insulation). It is a surface on the side of the base material 20 and is disposed in the insulating base material 20 so as to oppose the connecting surface with the insulating base material 20.

  Further, as shown in FIG. 2, the flat plate member 90 has a size (area) of one surface or more of the semiconductor chip 50 in the vertical direction so as to face the entire surface of the semiconductor chip 50.

  By doing in this way, the entire area between the semiconductor chip 50 and the heat sink 60 generated during the temperature change is larger than when the heat radiation connection via 42 is provided instead of the flat plate member 90 at a position facing the semiconductor chip 50. The amount of displacement can be reduced. Therefore, local stress can be reduced on the entire surface of the semiconductor chip 50 facing the heat sink 60. Further, by reducing the local stress on the semiconductor chip 50 in this way, the reliability as the circuit board 10 can be improved.

  The flat plate member 90 has a size (area) larger than the circuit element formation region in the vertical direction so as to face the entire circuit element formation region on at least one surface of the semiconductor chip 50 (surface on the heat sink 60 side). If it can be adopted. The circuit element formation region in the present invention is a region where a circuit element whose characteristics fluctuate due to stress such as a band gap circuit or a high-precision resistor (thin film resistor) is formed.

  Even when facing only the circuit element formation region on one surface of the semiconductor chip 50, the local stress on at least the part where the circuit element is arranged in the semiconductor chip 50 can be reduced.

  Thus, the flat plate member 90 functions as a heat radiation wiring portion together with the heat radiation connection via 42 and also functions as a stress absorption portion that absorbs stress on the semiconductor chip 50. Therefore, the flat plate member 90 can also be referred to as a stress absorbing member.

  In addition, it is preferable that the flat plate member 90 has a linear expansion coefficient in the thickness direction smaller than the linear expansion coefficient in the thickness direction of the insulating base material 20. By doing so, the stress can be further reduced.

  Also, depending on the material of the flat plate member 90, the heat dissipation may be reduced. Therefore, the thermal conductivity of the flat plate member 90 may be set to be equal to or higher than the thermal conductivity of the heat radiating connection via 42. By doing in this way, the local stress with respect to the semiconductor chip 50 can be reduced, suppressing the fall of heat dissipation.

  Further, the linear expansion coefficient in the vertical direction may be equal between the flat plate member and the circuit chip. By doing in this way, the stress of the perpendicular direction with respect to the semiconductor chip 50 by heat loads, such as a thermal cycle, can be reduced.

  Next, a method for manufacturing the circuit board 10 will be described. In addition, the code | symbol of the corresponding interlayer connection via and the radiation | emission connection via is described in the parenthesis after the code | symbol 40a which shows an electrically conductive paste. Moreover, as long as there is no notice in particular, the structure regarding the PALAP which the present applicant applied for so far can be suitably employ | adopted for the fundamental structure and manufacturing method of the circuit board 10. PALAP is a registered trademark of Denso Corporation.

  First, in order to form the circuit board 10 by pressurizing and heating the laminated body, elements constituting the laminated body are prepared. A substrate (hereinafter also referred to as a semiconductor unit) on which the semiconductor chip 50 is mounted and a plurality of resin films laminated on the semiconductor unit are prepared.

  In the present embodiment, as described above, as the thermosetting resin films 21a to 21d, films made of thermosetting polyimide (PI) that does not include an inorganic material such as glass fiber are employed. In the present embodiment, as an example, all the resin films 21a to 21d have the same thickness (for example, 50 μm).

  On the other hand, as the thermoplastic resin films 22a to 22d, 30% by weight of polyetheretherketone (PEEK) and polyetherimide (PEI) not containing inorganic materials such as glass fibers and inorganic fillers for adjusting the linear expansion coefficient. A resin film composed of 70% by weight is employed. In this embodiment, as an example, the resin films 22a, 22c, and 22d have the same thickness (for example, 80 μm), and the thermoplastic resin film 22b as the second film is thinner than the resin films 22a, 22c, and 22d. (For example, 50 μm).

  In this preparatory step, as is well known by the batch lamination method known as PALAP, the conductor pattern 30 is formed on the resin film constituting the insulating base material 20 before the lamination, or the interlayer connection via is sintered. A conductive paste 40a to be 41 is filled in the via hole. The arrangement of the conductor pattern 30 and the via holes filled with the conductive paste 40a is appropriately determined according to the wiring part and the heat dissipation wiring part described above.

  The conductor pattern 30 can be formed by patterning a conductor foil adhered to the surface of the resin film. The plurality of resin films constituting the insulating base material 20 may include a resin film having the conductor pattern 30. For example, a configuration in which all the resin films have the conductor pattern 30, or a part of the resin film is the conductor pattern 30. A configuration that does not include the can also be adopted. Moreover, as a resin film which has the conductor pattern 30, both the resin film which has the conductor pattern 30 only on one side, and the resin film which has the conductor pattern 30 on both surfaces in a lamination direction are employable.

  On the other hand, the conductive paste 40a can be obtained by adding ethyl cellulose resin, acrylic resin or the like to the conductive particles for imparting shape retention and kneading in an organic solvent such as terpineol. Then, a via hole penetrating the resin film is formed by a carbon dioxide laser or the like, and the conductive paste 40a is filled into the via hole by screen printing or the like. The via hole may be formed with the conductor pattern 30 as a bottom surface, or the via hole may be formed at a position where the conductor pattern 30 is not present.

  When the via hole is formed on the conductor pattern 30, the conductive pattern 40 becomes the bottom, so that the conductive paste 40a can be retained in the via hole. On the other hand, when a via hole is formed at a position different from the formation position of the conductor pattern 30 while having the resin film having the conductor pattern 30 or the conductor pattern 30, the conductive film is not conductive in the bottomless via hole. In order to fasten the paste 40a, the conductive paste 40a described in Japanese Patent Application No. 2008-296074 by the present applicant is used. Moreover, as an apparatus (method) for filling the conductive paste 40a, an apparatus (method) described in Japanese Patent Application No. 2009-75034 by the present applicant may be employed.

  The conductive paste 40a decomposes or volatilizes the conductive particles at a temperature lower than the sintering temperature of the conductive particles, becomes a molten state at a temperature lower than the temperature and higher than the room temperature, and is solid at room temperature. A low melting point room temperature solid resin that is in a state is added. An example of the low melting point room temperature solid resin is paraffin. According to this, by heating at the time of filling, the low melting point room temperature solid resin is melted into a paste, and in the cooling after filling, the low melting point room temperature solid resin is solidified to solidify the conductive paste 40a, It can be held in the via hole. When filling, one end of the via hole may be closed with a flat member.

  First, a process of preparing six resin films 21a, 21c, 21d, 22a, 22c, and 22d to be laminated on the semiconductor unit will be described.

  In this embodiment, as shown in FIG. 3, among the six resin films 21a, 21c, 21d, 22a, 22c, and 22d, only the thermosetting resin films 21a, 21c, and 21d have a copper foil (for example, thick) And a conductor pattern 30 is formed by patterning the copper foil. For the remaining two resin films 21b and 22b constituting the semiconductor unit, only a thermosetting resin film 21b is prepared with a film having a copper foil (also 18 μm in thickness) attached to one side. The conductor pattern 30 is formed by patterning.

  That is, the thermosetting resin films 21 a to 21 d are configured to have the conductor pattern 30 on one side, and the thermoplastic resin films 22 a to 22 d are configured not to have the conductor pattern 30.

  Further, of the six resin films 21a, 21c, 21d, 22a, 22c, and 22d, the conductor pattern 30 has the external connection electrode 33 on one side (inner surface in the laminated state), and the one surface 20a side of the insulating base material 20 Via holes (not shown) are formed in the five resin films 21c, 21d, 22a, 22c, and 22d except the thermosetting resin film 21a constituting the surface layer, and the conductive paste 40a is filled in the via holes. . And after filling, a solvent is volatilized in a drying process.

  In this embodiment, since the conductor pattern 30 is formed only on the thermosetting resin films 21a, 21c, and 21d, the thermoplastic resin films 22a, 22c, and 22d that do not form the conductor pattern 30 are Ag particles as conductive particles. A conductive paste 40a containing Sn particles at a predetermined ratio and having a low melting point room temperature solid resin such as paraffin added thereto as described above is used.

  For the thermosetting resin films 21a, 21c, and 21d, the same conductive paste 40a as the thermoplastic resin films 22a, 22c, and 22d may be used, and Ag particles and Sn particles are included as conductive particles in a predetermined ratio. Alternatively, the conductive paste 40a that does not include the low melting point room temperature solid resin may be employed.

  Furthermore, in this preparation step, since the stacked body has a cavity for accommodating the semiconductor chip 50, a cavity is formed in advance in a part of the plurality of resin films. In this embodiment, the cavity 23 for accommodating the semiconductor chip 50 is formed in the thermosetting resin film 21c. For this reason, the thermosetting resin film 21c having the cavity 23 has a rectangular frame shape.

  Similarly, since the laminate has a cavity (through hole) for accommodating the flat plate member 90, a cavity (through hole) is formed in advance in a part of the plurality of resin films. In the present embodiment, a cavity (through hole) 25 for accommodating the flat plate member 90 is formed in the thermosetting resin film 21d. For this reason, the thermosetting resin film 21c having the cavity 25 has a rectangular frame shape.

  The cavities 23 and 25 can be formed by mechanical processing such as punching or drilling or laser light irradiation, and are formed with a predetermined margin with respect to the physique of the semiconductor chip 50 or the flat plate member 90. The formation timing of the cavities 23 and 25 may be before or after the formation of the conductor pattern 30 and the interlayer connection via 41.

  In addition, a semiconductor unit forming step is performed in parallel with the above-described preparation steps of the resin films 21a, 21c, 21d, 22a, 22c, and 22d.

  In this embodiment, as shown to Fig.4 (a), the thermosetting resin film 21b and the thermoplastic resin film 22b which make a board | substrate are prepared. About the thermosetting resin film 21b, what the copper foil was affixed on one side is prepared, this copper foil is patterned, and the conductor pattern 30 is formed. At this time, a pad 31 and a horizontal wiring portion 32 are also formed as the conductor pattern 30.

  Next, by applying heat and pressure, the thermoplastic resin film 22b is attached to the pad forming surface of the substrate so as to cover the pad 31 and the lateral wiring portion 32.

  In this embodiment, as shown in FIG.4 (b), the thermoplastic resin film 22b is thermocompression-bonded to the pad formation surface of the thermosetting resin film 21b as a board | substrate so that the pad 31 and the horizontal wiring part 32 may be covered. To do.

  Specifically, pressurizing the thermoplastic resin film 22b while heating the thermoplastic resin film 22b so that the temperature is not lower than the melting point and not higher than the glass transition point of the thermoplastic resin constituting the film 22b. Then, the softened thermoplastic resin is brought into close contact with the land forming surface of the thermosetting resin film 21 b and the surface of the conductor pattern 30.

  After thermocompression bonding the thermoplastic resin film 22b to the thermosetting resin film 21b, via holes are formed in the resin films 21b and 22b with the conductive pattern 30 as the bottom surface, and the via holes are formed as shown in FIG. The conductive paste 40a is filled. In this case, since the conductive pattern 30 is the bottom surface, the conductive paste 40a may be a conductive paste that does not include a low-melting room temperature solid resin, or a conductive paste that includes a low-melting room temperature solid resin. It may be adopted.

  Next, the separately prepared semiconductor chip 50 is flip-chip mounted on the substrate.

  In the semiconductor chip 50, stud bumps 52a are formed on the electrodes 51a on the mounting surface with respect to the substrate. In the present embodiment, stud bumps 52a (bump-like bumps) made of Au are formed on an electrode 51a made of an Al-based material by a well-known method using, for example, a wire.

  Then, as shown in FIG. 4C, the semiconductor chip 50 is pressed toward the substrate while being heated from the back side of the substrate mounting surface by, for example, a pulse heat type thermocompression bonding tool 100. At this time, pressure is applied to the thermosetting resin film 21b side while heating at a temperature equal to or higher than the melting point of the thermoplastic resin constituting the thermoplastic resin film 22b (PEEK: PEI = 30: 70, 330 ° C.).

  When the heat from the thermocompression bonding tool 100 is transferred to the semiconductor chip 50 and the tip temperature of the stud bump 52a becomes equal to or higher than the melting point of the thermoplastic resin constituting the thermoplastic resin film 22b, the portion of the thermoplastic resin film 22b with which the stud bump 52a contacts. Softens and melts (melts). Therefore, the stud bump 52a can be pushed into the thermoplastic resin film 22b and brought into contact with the corresponding pad 31 while the thermoplastic resin film 22b is melted. Thereby, as shown in FIG.4 (d), the stud bump 52a and the pad 31 can be made into a press-contact state.

  The melted / softened thermoplastic resin flows under pressure and adheres to the substrate mounting surface of the semiconductor chip 50, the pad forming surface of the thermosetting resin film 21b, the conductor pattern 30, the electrode 51a, and the stud bump 52a. To do. Therefore, as shown in FIG.4 (d), between the semiconductor chip 50 and the thermosetting resin film 21b (board | substrate) can be sealed with the thermoplastic resin film 22b. In this way, a semiconductor unit is formed.

  In the present embodiment, the heating temperature at the time of flip chip mounting is set to about 350 ° C., which is slightly higher than the melting point, and a pressure is applied so that the load applied to one stud bump 52a is about 20 to 50 gf. Thereby, the stud bump 52a and the pad 31 can be brought into a pressure contact state in a short time.

  When heating and pressurization are continued even after the pressure contact state is reached, Au constituting the stud bump 52a and Cu constituting the pad 31 diffuse to each other (solid phase diffusion), and a metal diffusion layer (Cu— Au alloy layer) is formed. Further, Au constituting the stud bump 52a is solid-phase diffused with respect to Al constituting the electrode 51a to form a metal diffusion layer (Au—Al alloy layer). However, in order to form such a metal diffusion layer, it takes a longer time for heating and pressurization compared to the above-described press contact state. If it takes a long time to mount one semiconductor chip 50 on a substrate, the formation time of the circuit board 10 incorporating the semiconductor chip 50 becomes long as a result, and the manufacturing cost also increases. In the meantime, unnecessary heat is applied to portions other than the electrical connection portions of the electrode 51a, the stud bump 52a, and the pad 31. For this reason, in this mounting process, the connection state between the stud bump 52a and the pad 31 is kept in the pressure contact state.

  Further, in the present embodiment, an example in which the via hole is formed after the thermoplastic resin film 22b is attached to the thermosetting resin film 21b and the conductive paste 40a is filled is shown. However, a via hole may be formed in each of the resin films 21b and 22b before being attached, and the conductive paste 40a may be filled.

  For the conductive paste 40a, when the semiconductor chip 50 is formed by heating / pressing when flip-chip mounting on a substrate, or when the thermoplastic resin film 22b is formed before being applied, the pressure / heating at the time of application is applied. Accordingly, the conductive particles may be sintered to form the interlayer connection via 41, or the conductive paste 40a may be left as it is when the semiconductor unit is formed without being sintered. Moreover, it is good also as a state which one part sintered. In this embodiment, it is set as the electrically conductive paste 40a in the state after flip chip mounting.

  Next, a stacking process for forming a stacked body is performed. In this step, a plurality of resin films including a resin film having a conductor pattern 30 formed on the surface and a resin film filled with a conductive paste 40a in a via hole, and at least every other thermoplastic resin film, While being positioned, the semiconductor chip 50 is laminated so as to be adjacent to the electrode forming surface and the back surface of the electrode forming surface.

  In this embodiment, as shown in FIG. 6, from one end side in the stacking direction, the thermosetting resin film 21a, the thermoplastic resin film 22a, the thermosetting resin film 21b, the thermoplastic resin film 22b, and the thermosetting resin film. 21c, a plurality of resin films 21a, 21c, 21d, 22a, 22c, 22d, a semiconductor unit, and a flat plate member so as to be in the order of 21c, thermoplastic resin film 22c, thermosetting resin film 21d, and thermoplastic resin film 22d. 90 is laminated. Thus, in this embodiment, it laminates | stacks so that the thermoplastic resin films 22a-22d and the thermosetting resin films 21a-21d may be located alternately.

  Further, the heat sink 60 is laminated on the thermoplastic resin film 22d. In FIG. 6, for the sake of convenience, the elements constituting the laminated body are illustrated separately.

  Specifically, the thermoplastic resin film 22a is laminated on the conductor pattern forming surface of the thermosetting resin film 21a, and the semiconductor unit is laminated on the thermoplastic resin film 22a with the thermosetting resin film 21b as a mounting surface. On the thermoplastic resin film 22b in the semiconductor unit, around the semiconductor chip 50, a thermosetting resin film 21c is laminated with the surface opposite to the conductor pattern forming surface as a mounting surface. Further, the thermoplastic resin film 22c is laminated on the thermosetting resin film 21c and the semiconductor chip 50, and the thermosetting resin film 21d and the flat plate member 90 are formed on the thermoplastic resin film 22c with the conductor pattern forming surface as a mounting surface. Are laminated. And the thermoplastic resin film 22d is laminated | stacked on the thermosetting resin film 21d, and also the heat sink 60 is laminated | stacked, and one laminated body is formed.

  In this laminated body, the resin film adjacent to the semiconductor chip 50 in the lamination direction becomes the thermoplastic resin films 22b and 22c. At least these resin films 22b and 22c fulfill the function of sealing the periphery of the semiconductor chip 50 in the pressurizing / heating process. In this embodiment, since the resin film surrounding the semiconductor chip 50 in the vertical direction is the thermosetting resin film 21c, the two resin films 22b and 22c serve to seal the periphery of the semiconductor chip 50.

  Moreover, in this laminated body, the resin film adjacent to the flat member 90 becomes the thermoplastic resin films 22c and 22d in the lamination direction. At least these resin films 22c and 22d fulfill the function of sealing the periphery of the flat plate member 90 in the pressurizing / heating process. In the present embodiment, since the resin film surrounding the flat plate member 90 in the vertical direction is the thermosetting resin film 21d, the two resin films 22c and 22d have a function of sealing the periphery of the flat plate member 90. Fulfill.

  As described above, as the thermoplastic resin films 22b and 22c for sealing the semiconductor chip 50, the thermoplastic resin film does not contain an inorganic material such as glass fiber or aramid fiber, and the linear expansion coefficient and the melting point are adjusted. Therefore, it is preferable to employ a material that does not contain any inorganic filler. By doing so, it is possible to prevent the semiconductor chip 50 from being locally stressed in the pressurizing / heating step.

However, when the thermoplastic resin films 22b and 22c that do not include an inorganic filler for adjusting the linear expansion coefficient and the melting point are employed, the difference in the linear expansion coefficient from the semiconductor chip 50 increases due to the absence of the inorganic filler. It is conceivable that the stress increases. Therefore, a resin film having a low elastic modulus (for example, 10 GPa or less) may be employed as the thermoplastic resin films 22b and 22c in order to reduce stress.

  Further, as the thermoplastic resin films 22b and 22c for sealing the semiconductor chip 50, those having a thickness of 5 μm or more are preferably employed. This is because if the thickness is less than 5 μm, the stress of the resin films 22b and 22c is increased in the pressurizing / heating step and may be peeled off from the surface of the semiconductor chip 50.

Next, a pressurizing / heating process is performed in which the laminate is heated from above and below while heating the laminate using a vacuum heat press. In this step, the thermoplastic resin is softened and the plurality of resin films are integrated together, the semiconductor chip 50 and the flat plate member 90 are sealed, and the conductive particles in the conductive paste 40a are used as a sintered body. Then, a wiring portion having the sintered body and the conductor pattern 30 is formed.

  In the pressurizing / heating step, the resin films are integrated together to form the insulating base material 20 and the conductive particles in the conductive paste 40a are made into a sintered body. A temperature not lower than the glass transition point and not higher than the melting point and a pressure of several MPa are maintained for a predetermined time. In the present embodiment, a press temperature of 280 ° C. to 330 ° C. and a pressure of 4 to 5 MPa are maintained for 5 minutes or longer (for example, 10 minutes).

  First, the connection of the resin film part in the pressurizing / heating step will be described.

  The thermoplastic resin films 22a to 22d arranged every other sheet are softened by the heating. Since the pressure is received at this time, the softened thermoplastic resin films 22a to 22d are in close contact with the adjacent thermosetting resin films 21a to 21d. Thereby, several resin film 21a-21d, 22a-22d integrates collectively, and the insulation base material 20 is formed. At this time, since the adjacent thermoplastic resin film 22 d is also in close contact with the heat sink 60, the heat sink 60 is also integrated with the insulating base material 20.

  Further, the thermoplastic resin films 22b and 22c adjacent to the semiconductor chip 50 flow under pressure, and are in close contact with the electrode 51a formation surface of the semiconductor chip 50 and the dummy electrode 51b formation surface which is the back surface thereof. Further, it also enters the gap between the side surface of the semiconductor chip 50 and the thermosetting resin film 21c, fills the gap, and adheres closely to the side surface of the semiconductor chip 50. Therefore, the semiconductor chip 50 is sealed with the thermoplastic resin (thermoplastic resin films 22b and 22c).

  Further, the thermoplastic resin films 22 c and 22 d adjacent to the flat plate member 90 flow under pressure and adhere to the flat plate member 90. Further, it also enters the gap between the side surface of the flat plate member 90 and the thermosetting resin film 21d, fills the gap, and closely contacts the side surface of the flat plate member 90. Accordingly, the flat plate member 90 is sealed with the thermoplastic resin (thermoplastic resin films 22c and 22d).

  Next, in the pressurizing / heating process, connection of the electrode 51a, the dummy electrode 51b, the conductor pattern 30, the interlayer connection via 41, the heat radiation connection via 42, the heat sink 60, and the flat plate member 90 of the semiconductor chip 50 will be described.

  By the above heating, Sn (melting point: 232 ° C.) in the conductive paste 40a is melted and diffused to Ag particles in the conductive paste 40a to form an Ag—Sn alloy (melting point: 480 ° C.). Further, since pressure is applied to the conductive paste 40a, the interlayer connection via 41 and the heat dissipation connection via 42 made of an alloy integrated by sintering are formed in the via hole.

  The melted Sn also interdiffuses with the conductor pattern 30, the heat sink 60, and Cu constituting the flat plate member 90. Thereby, a metal diffusion layer (Cu—Sn alloy layer) is formed at the interface between the interlayer connection via 41 and the conductor pattern 30, the interface between the heat dissipation connection via 42 and the heat sink 60, and the interface between the heat dissipation connection via 42 and the flat plate member 90. It is formed.

  The molten Sn also diffuses with Ni constituting the dummy electrode 51b of the semiconductor chip 50. As a result, a metal diffusion layer (Ni—Sn alloy layer) is formed at the interface between the heat dissipation connection via 42 and the dummy electrode 51b.

Further, Au constituting the stud bump 52 a is solid-phase diffused into Al constituting the electrode 51 a of the semiconductor chip 50. Since the electrode 51a is a fine pitch compatible electrode, the amount of Al constituting the electrode 51a is smaller than the amount of Au constituting the stud bump 52a, and the thickness of the portion of the electrode 51a facing the stud bump 52a. All of the Al in the direction is consumed for alloying with Au, and after the pressurizing / heating step, Al is not contained as a single metal in the above-mentioned part. Moreover, the electrode 51a after pressurization and heating mainly contains an Au ₄ Al alloy as an Au—Al alloy.

In addition, even if Au ₅ Al ₂ having a high growth rate is produced before the Au ₄ Al alloy is produced in the pressurizing / heating step, since the pressure is applied, the above-mentioned Kirkendall void is produced. Can be suppressed.

Further, Au constituting the stud bump 52a and Cu constituting the conductor pattern 30 (pad 31) diffuse mutually. Thereby, a Cu—Au alloy layer containing a CuAu ₃ alloy is formed at the interface between the connection portion 52 derived from the stud bump and the pad 31. The Cu—Au alloy can be generated if it is heated to about 250 ° C. or more, and the CuAu ₃ alloy layer can be formed according to the above-described pressurizing / heating conditions.

  In addition, the stud bump 52a includes an electrode 51a including a portion made of an Au—Al alloy and a pad 31 made of Cu and having a Cu—Au alloy layer at the interface due to the remainder of Au consumed in the solid phase diffusion bonding. It becomes the connection part 52 connected electrically. Thus, in the pressurizing / heating process, the connection state between the stud bump 52a and the pad 31 is set to a direct bonding state.

  As described above, as shown in FIG. 7, the semiconductor chip 50 is built in the insulating base material 20, the semiconductor chip 50 is sealed with the thermoplastic resin, and the semiconductor chip 50 and the external connection electrode 33 are electrically connected by the wiring portion. Thus, it is possible to obtain a substrate in which the semiconductor chip 50 and the heat sink 60 are thermally connected by the heat radiation wiring portion including the flat plate member 90.

  A hole with the external connection electrode 33 as a bottom surface is formed from the one surface 20a side of the insulating base material 20 on the substrate, and a conductive member such as a plating film is disposed in the hole, and then a solder ball is formed on the conductive member. By forming 70, the circuit board 10 shown in FIG. 1 can be obtained.

  By doing in this way, the entire area between the semiconductor chip 50 and the heat sink 60 generated during the temperature change is larger than when the heat radiation connection via 42 is provided instead of the flat plate member 90 at a position facing the semiconductor chip 50. The amount of displacement can be reduced. Therefore, it is possible to manufacture the circuit board 10 in which the local stress on the entire surface of the semiconductor chip 50 facing the heat sink 60 is reduced. In addition, since the local stress on the semiconductor chip 50 can be reduced as described above, the circuit board 10 with high reliability can be manufactured.

Further, in the circuit board 10 according to the present embodiment, since the flat plate member 90 connected to the semiconductor chip 50 and the heat sink 60 via the heat radiating connection via 42 is provided, the semiconductor chip 50 is applied during the pressurizing / heating process. Next, effects of other characteristic portions in the circuit board 10 and the manufacturing method thereof shown in the above embodiment will be described.

  In the present embodiment, when forming the circuit board 10, the thermoplastic resin films 22 a to 22 d are adjacent to the electrode 51 a formation surface of the semiconductor chip 50 and the back surface of the electrode formation surface while being positioned at least every other sheet. A plurality of resin films 21a to 21d and 22a to 22d are laminated to form a laminate.

  Therefore, the plurality of resin films 21a to 21d and 22a to 22d can be integrated together by pressing and heating using the thermoplastic resin constituting the thermoplastic resin films 22a to 22d as an adhesive. In addition, the semiconductor chip 50 can be sealed by at least the thermoplastic resin films 22b and 22c adjacent to the semiconductor chip 50. Furthermore, the wiring part can be formed together with the conductor pattern 30 by using the conductive particles in the conductive paste 40a as a sintered body by the pressurization and heating. For this reason, the manufacturing process of the circuit board 10 can be simplified.

  Further, before the lamination step for forming the laminate, the thermoplastic resin film 22b is disposed between the semiconductor chip 50 and the substrate (thermosetting resin film 21b), and is heated at a temperature equal to or higher than the melting point of the thermoplastic resin. While applying pressure. Therefore, while the temperature is raised to the melting point or higher of the thermoplastic resin, the thermoplastic resin can be made fluid, and the thermoplastic resin located between the stud bump 52a and the pad 31 is moved by pressurization. Thus, the stud bump 52a can be brought into direct contact with the pad 31 to bring the stud bump 52a and the pad 31 into a pressure contact state.

  At this time, the molten thermoplastic resin flows under pressure and seals between the semiconductor chip 50 and the substrate (thermosetting resin film 21b) including the periphery of the connection portion between the stud bump 52a and the pad 31. . Therefore, electrical insulation between each connection part can be ensured. Moreover, the connection reliability in a connection part can be improved.

  Further, when the stud bump 52a and the pad 31 are brought into the pressure contact state, the flip chip mounting process (heating / pressing) is finished, and the stud bump 52a and the pad 31 are subjected to the pressing / heating received in the pressing / heating process. And a joined state. In this manner, the stud bump 52a (connection portion 52) and the pad 31 are brought into a joined state by utilizing the heat and pressure of the pressurizing / heating process, and therefore, the electrode 51a of the semiconductor chip 50 is compared with the pressed state. The reliability of electrical connection between the pad 31 and the pad 31 can be improved.

  Further, in the flip chip mounting process, the stud bump 52a and the pad 31 are brought into a pressure contact state, and the stud bump 52a and the pad 31 are brought into a joined state by utilizing heat and pressure in the pressurizing / heating process. Therefore, in the flip chip mounting process, the manufacturing time can be shortened as compared with a method in which the stud bump 52a and the pad 31 are brought into a bonded state and then the pressurizing / heating process is performed.

  If the stud bump 52a is not brought into contact with the pad 31 before the lamination process, and the stud bump 52a is brought into contact with the pad 31 and brought into a joined state in the pressurizing / heating process, the softened thermoplasticity is obtained. Due to the buffering effect of the resin, the stud bump 52a is less likely to be pushed into the thermoplastic resin film 22b as the second film. As a result, the thermoplastic resin may remain between the stud bump 52a and the pad 31.

  On the other hand, in the present embodiment, the stud bump 52a and the pad 31 are brought into a pressure contact state before the stacking process, so that the stud bump 52a and the pad 31 can be securely connected by pressurization / heating in the pressurization / heating process. It can be set as a joining state.

  Moreover, in this embodiment, the conductor pattern 30 is formed only in the thermosetting resin films 21a-21d, and the conductor pattern 30 is not formed in the thermoplastic resin films 22a-22d. Therefore, even if the thermoplastic resin is softened by a pressurizing / heating process or the like and flows under pressure, the conductor pattern 30 is fixed to the thermosetting resin films 21a to 21d. Can be suppressed. For this reason, it is suitable for the circuit board 10 incorporating the semiconductor chip 50 corresponding to the fine pitch.

  In the present embodiment, in the pressurizing / heating process, Au constituting the stud bump 52a is solid-phase diffused in the Al of the electrode 51a in contact with one end side of the stud bump 52a, and on the other end side of the stud bump 52a. Solid phase diffusion with Cu of the pad 31 in contact therewith. Therefore, the electrical connection reliability between the electrode 51a and the pad 31 through the stud bump 52a (connection portion 52) can be further improved, and the Au—Al alloy and the Cu—Au alloy are formed in the same process. The manufacturing process can also be simplified.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  The structure of the several resin film which comprises the insulating base material 20 is not limited to the said example. The number of resin films is not limited to the above example (eight). Any number of semiconductor chips 50 can be used.

  The constituent material of the thermoplastic resin film is not limited to the above example. For example, even if it consists of PEEK / PEI, you may employ | adopt the thing from which a ratio differs from the said example. In addition, constituent materials other than PEEK / PEI, such as liquid crystal polymer (LCP), polyphenylene sulfide (PPS), tetrafluoroethylene / hexafluoropropylene copolymer (FEP), tetrafluoroethylene / perfluoroalkyl vinyl ether copolymer (PFA) ) Etc. may be adopted.

  In order to suppress local stress application to the semiconductor chip 50 in the pressurizing / heating process, as the thermoplastic resin films 22a to 22d, inorganic materials used for base materials such as glass fibers and aramid fibers, melting points and linear expansions. Although the example using the film which does not have the inorganic filler added for adjustment of a coefficient was shown, thermoplastic resin films 22a-22d containing these can also be adopted. However, as described above, with respect to the thermoplastic resin film (two thermoplastic resin films 22b and 22c in this embodiment) used for sealing the semiconductor chip 50, local stress application to the semiconductor chip 50 is performed. In order to suppress this, it is preferable to use an inorganic material used for a substrate such as glass fiber or aramid fiber, or a film having no inorganic filler added for adjusting the melting point or the linear expansion coefficient.

  The constituent material of the thermosetting resin film is not limited to the above example. For example, a film containing an inorganic material used for a substrate such as glass fiber or aramid fiber can also be employed. Also, a thermosetting resin other than the thermosetting polyimide can be employed.

  Moreover, it is good also as a structure which does not contain a thermosetting resin film but contains only a thermoplastic resin film as a several resin film. Alternatively, the number of thermoplastic resin films may be larger than that of the thermosetting resin film, and the thermoplastic resin film may be partially continuous in the laminated state.

  In this embodiment, the example of the thermosetting resin film 21b as a 1st film was shown as a board | substrate with which the semiconductor chip 50 is flip-chip mounted. However, a thermoplastic resin film may be employed as the first film. Moreover, you may comprise a board | substrate using the several resin film containing a 1st film.

  Further, the thickness of the resin film and the thickness of the conductor pattern 30 are not limited to the above examples. However, as described above, the thermoplastic resin films 22b and 22c that are adjacent to the semiconductor chip 50 and seal the semiconductor chip 50 in the stacking direction preferably have a thickness of 5 μm or more.

(Modification 1)
In the above-described embodiment, an example in which the flat plate member 90 has a size (area) of one surface or more of the semiconductor chip 50 in the vertical direction so as to face the entire surface of the semiconductor chip 50 is employed. Is not limited to this.

  As shown in FIG. 8, in the circuit board 10 of the first modification, an electrode 51c that provides an electrical connection function is provided on one surface of the semiconductor chip 50 together with the dummy electrode 51b. The electrode 51c is electrically connected to a circuit provided in the semiconductor chip 50 and is electrically connected to the external connection electrode 33 by a wiring portion. The reason why the electrodes 51a and 51c are provided on both surfaces is that the element includes an element through which a current flows in the thickness direction, such as a vertical MOSFET, IGBT, or resistor.

  For example, as shown in FIG. 9, in the circuit board 10 of the first modification, an electrode 51c is provided in a peripheral region (for example, one row of outer periphery) on one surface of the semiconductor chip 50, and a dummy electrode is formed in a region surrounded by the electrode 51c. 51b is provided. Further, the flat plate member 90 has the same size as the dummy electrode formation region in the direction perpendicular to the thickness direction so as to face the dummy electrode (heat radiation electrode) formation region. It is assumed that the circuit element whose characteristics fluctuate due to stress is disposed only in a region facing the flat plate member 90 in the semiconductor chip 50.

  By doing in this way, since the semiconductor chip 50 can electrically connect also in the one surface facing the heat sink 60, it is preferable.

  In addition, when the electrode 51c that provides an electrical connection function together with the dummy electrode 51b is provided on one surface of the semiconductor chip 50, it is necessary to increase the number of laminated resin films disposed between the semiconductor chip 50 and the heat sink 60. . Accordingly, it is necessary to stack the heat dissipation connection vias 42 in the thickness direction. In this case, the local stress on the semiconductor chip 50 is larger than when only one layer of the heat radiation connection via 42 is provided.

  However, by providing the flat plate member 90, at least the circuit elements in the semiconductor chip 50 are arranged even when the electrode 51c that provides an electrical connection function together with the dummy electrode 51b is provided on one surface of the semiconductor chip 50. The local stress on the damaged part can be reduced. That is, the flat plate member 90 of the present invention is particularly effective in such a structure.

(Modification 2)
Further, as shown in FIG. 10, in the circuit board 10 of the second modification, an electrode 51c that provides an electrical connection function together with the dummy electrode 51b is provided in a region facing the flat plate member 90 on one surface of the semiconductor chip 50. It may be provided. That is, a wiring portion that is electrically connected to the electrode 51c may be provided in a region where the one surface of the semiconductor chip 50 and the flat plate member 90 are opposed to each other. The reason why the electrodes 51a and 51c are provided on both surfaces is that the element includes an element through which a current flows in the thickness direction, such as a vertical MOSFET, IGBT, or resistor.

  By doing in this way, since the semiconductor chip 50 can perform an electrical connection also in the position facing the flat member 90, it is preferable.

  Further, when an electrode 51 c that provides an electrical connection function together with the dummy electrode 51 b is provided in a region facing the flat plate member 90 on one surface of the semiconductor chip 50, the electrode 51 c is disposed between the semiconductor chip 50 and the heat sink 60. It is necessary to increase the number of laminated resin films. Accordingly, it is necessary to stack the heat dissipation connection vias 42 in the thickness direction. In this case, the local stress on the semiconductor chip 50 is larger than when only one layer of the heat radiation connection via 42 is provided.

  However, by providing the flat plate member 90, the semiconductor 51 can be provided with an electrode 51c that provides an electrical connection function together with the dummy electrode 51b in a region facing the flat plate member 90 on one surface of the semiconductor chip 50. It is possible to reduce local stress on at least a portion where the circuit element is arranged in the chip 50. That is, the flat plate member 90 of the present invention is particularly effective in such a structure.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not restrict | limited to the embodiment mentioned above at all, and various deformation | transformation are possible in the range which does not deviate from the meaning of this invention.

DESCRIPTION OF SYMBOLS 10 ... Circuit board 20 ... Insulation base material 21a-21d ... Thermosetting resin film 22a-22d ... Thermoplastic resin film 30 ... Conductor pattern 41 ... Interlayer connection via 42 ... · Heat dissipation connection via 50 ··· Semiconductor chip 51a ··· Electrode 51b ··· Dummy electrode 60 · · · Heat sink 90 ··· Flat plate member

Claims (9)

A circuit board in which an insulating base material containing a thermoplastic resin is provided with a wiring portion including a conductor pattern and an interlayer connection via,
A heat dissipating member disposed on one surface of the insulating substrate perpendicular to the thickness direction of the insulating substrate;
An electrical connection electrode including at least one circuit element, having a heat radiation electrode on one surface of the heat radiation member, and electrically connected to the wiring portion on at least one of the one surface and the back surface of the one surface A circuit chip embedded in the insulating base material and sealed with a thermoplastic resin of the insulating base material,
A heat dissipating connection via provided on the insulating substrate and thermally connecting the heat dissipating electrode of the circuit chip and the heat dissipating member;
It is connected to the circuit chip and the heat dissipation member via the heat dissipation connection via, and has a thermal conductivity higher than that of the insulating base material and thicker than the conductor pattern in the thickness direction. A flat plate-like member disposed between the circuit chip and the heat radiating member,
The circuit board characterized in that the flat plate member has a size larger than the circuit element formation region in a direction perpendicular to the thickness direction so as to face at least the entire circuit element formation region on one surface of the circuit chip. .   The circuit board according to claim 1, wherein the flat plate member has a linear expansion coefficient in the thickness direction smaller than a linear expansion coefficient in the thickness direction of the insulating base material. The one surface of the circuit chip is provided with the electrode for electrical connection together with the electrode for heat dissipation,
The conductor pattern as an external connection electrode is provided on the surface opposite to the heat dissipating member arrangement surface of the insulating base,
The circuit board according to claim 1, wherein the electrical connection electrode and the external connection electrode provided on one surface of the circuit chip are electrically connected by the wiring portion. The electrical connection electrode is provided in a peripheral region on one surface of the circuit chip, and the heat dissipation electrode is provided in a region surrounded by the electrical connection electrode,
The said flat member has a magnitude | size comparable as the said heat radiation electrode formation area in the direction perpendicular | vertical to the said thickness direction so as to oppose the heat radiation electrode formation area. Circuit board.   4. The flat plate member according to any one of claims 1 to 3, wherein the flat member has a size equal to or larger than the one surface in a direction perpendicular to the thickness direction so as to face the entire one surface of the circuit chip. Description circuit board.   The circuit board according to claim 2, wherein the electrical connection electrode and the heat dissipation electrode are provided in a region facing the flat plate member on one surface of the circuit chip.   The electrical connection electrode is also provided on the back surface of the circuit chip, and the electrical connection electrode and the external connection electrode provided on the back surface of the circuit chip are electrically connected by the wiring portion. The circuit board according to claim 2, wherein the circuit board is characterized in that:   The circuit board according to claim 1, wherein the flat plate member has a thermal conductivity equal to or higher than a thermal conductivity of the heat radiating connection via.   The circuit board according to any one of claims 1 to 8, wherein the flat plate member has a linear expansion coefficient in a direction perpendicular to the thickness direction equal to that of the circuit chip.

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