JP2005167159A - Laminated semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated semiconductor device, which can be manufactured at low cost, is small, and improves the heat dissipation efficiency of a logic IC even if the semiconductor device is formed by laminating a memory IC and the logic IC three-dimensionally. <P>SOLUTION: The laminated semiconductor device comprises memory-type semiconductor packages 101, 120, which have wiring boards 111, 121 on which memory ICs 115, 125 are mounted, a logic-type semiconductor package 130, which has a wiring board 135 on which a logic IC 135 is mounted, and a base board 101 on which the memory-type semiconductor packages 101, 120 and the logic-type semiconductor package 130 are mounted in a laminated arrangement. The logic-type semiconductor package 130 forms the top layer of the lamination to be farthest from the base board 101. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a stacked semiconductor device on which different types of semiconductor elements are mounted, and more particularly to a stacked semiconductor device in which a plurality of semiconductor packages are stacked.

  In recent years, portable devices such as mobile phones and digital cameras have been reduced in size, thickness, and weight, and accordingly, there has been an increasing demand for smaller and thinner electronic components and higher performance and more functions. In this trend, semiconductor products have been made smaller and lighter and have higher performance and more functions. Particularly in memory products, there are high demands for large recording capacity, small size, light weight, and low cost, and various memory IC package structures and mounting structures are considered.

  In general, a package mounting a memory IC includes a method in which a thin mold package such as TSOP is soldered to a base substrate, or a method in which a bare chip is directly connected to the base substrate by wire bonding, flip chip mounting, or the like. . However, since the capacity that can be mounted in the same area is determined by the chip size, in order to further increase the capacity, commercialization of a package having a mounting structure in which chips are three-dimensionally stacked has been promoted (for example, Patent Document 1).

  FIG. 45 is a cross-sectional view showing the structure of the stacked semiconductor device 10 having such a three-dimensional mounting structure. The stacked semiconductor device 10 includes a base substrate 11, four sets of semiconductor packages 20 stacked on the base substrate 11, an intermediate substrate 12 disposed between the semiconductor packages 20, and these are integrally sealed. An epoxy adhesive 13 and a top plate 14 are provided. Electrode members 11a are formed on the base substrate 11 by solder plating or the like, and connection lands 12a and 12b are formed on the intermediate substrate 12.

  The semiconductor package 20 includes a thin wiring board 21 formed of glass epoxy resin, a semiconductor element 22 connected by a flip chip method on a wiring pattern 21 a provided on the surface of the wiring board 21, and the semiconductor element 22. And an anisotropic conductive film 23 for fixing the wiring board 21 to each other. In FIG. 45, 24 indicates a gold bump.

  Connection lands 21b and 21c are provided on both sides of the wiring board 21, and these connection lands 21b and 21c are connected by a through hole 21d.

  The electrode land 11 a of the base substrate 11 is connected to the connection land 21 c of the lowermost semiconductor package 20.

  Such a stacked semiconductor device 10 is manufactured by the following process. That is, after the semiconductor elements 22 are mounted on the wiring substrate 21 by flip chip connection to form the semiconductor package 20, the connection land 21 c of the lowermost semiconductor package 20 is connected to the electrode member 11 a of the base substrate 11. At this time, for example, a resin containing a surface active component such as an adhesive or a flux is supplied to the electrode member 11a.

  Next, the semiconductor packages 20 and the intermediate substrate 12 are alternately stacked, and the connection lands 21b and 21c and the connection lands 12a and 12b are connected to each other. After the semiconductor package 20 is stacked in four stages, the connection is performed by thermocompression bonding or the like, and the adhesive 13 is cured to perform sealing.

  In memory products, the mounting structure as described above has been used to increase the recording capacity in one package. Currently, however, there is an increasing demand for a semiconductor package having a memory function and a logic function in one package. ing. In order to provide a memory function and a logic function in one package, a memory IC and a logic IC are developed as well as a method for developing a semiconductor element having both a memory function and a logic function, and a memory product having a large recording capacity. There is a method of realizing multi-functionality by stacking a package in which each is flip-chip mounted on a thin wiring substrate on a base substrate.

  However, semiconductor elements with a memory function and a logic function added to a single chip, like a memory product, have a capacity and a function that can be mounted on the same area, which are determined by the chip size. I have the problem of increasing size. In addition, the manufacturing cost of the semiconductor element in which the memory function and the logic function are mixedly mounted is high, and there is a problem that the development period becomes long.

  On the other hand, when a semiconductor package is provided with a memory function and a logic function by laminating a wiring board on which a memory IC and a logic IC are flip-chip mounted on a base substrate, the mounting structure is the same as the structure handled in the memory product. There is an advantage that it can be deployed.

In addition, since it has a structure in which a package in which a memory IC and a logic IC are individually mounted is laminated, it is possible to easily cope with differences in required functions among users by changing the type of semiconductor elements to be laminated. It has the advantage of a short package development period. For this reason, it is expected that the development of a semiconductor package in which a memory function and a logic function are mixed will be advanced in a structure in which semiconductor elements are stacked.
Japanese Patent Laid-Open No. 2003-209220

  The stacked semiconductor device described above has the following problems. That is, the memory package has been increased in capacity by a semiconductor package having a structure in which a plurality of semiconductor elements are stacked. However, in this package stacked structure, an intermediate member corresponding to the thickness of the semiconductor element is necessarily required. Moreover, since it is necessary to provide a through electrode on a thin wiring board for connection and conduction between semiconductor packages, there is a problem that the member cost is high. Further, since the external connection lands of the semiconductor package are three-dimensionally connected, it is difficult to secure the manufacturing yield.

  Furthermore, when a semiconductor package in which a memory function and a logic function are mixed is realized with the three-dimensional stacked structure that has been used in memory products so far, it is expected that the temperature of the semiconductor element will be increased by heat generated during the operation of the logic IC. However, the current structure has a problem that it is difficult to dissipate heat generated from the logic IC.

  Accordingly, the present invention provides a stacked semiconductor device that can be manufactured at a low cost even when a memory IC and a logic IC are three-dimensionally stacked, and is small in size and can improve the heat dissipation efficiency of the logic IC. The purpose is to do.

  In order to solve the above problems and achieve the object, the stacked semiconductor device of the present invention is configured as follows.

(1) A memory type semiconductor package having a wiring board on which a memory IC is mounted, a logic type semiconductor package having a logic wiring board on which a logic IC is mounted, and at least one of these memory type semiconductor package and logic type semiconductor package The logic type semiconductor package is disposed on a base substrate to be stacked and mounted, and at least on the uppermost layer farthest from the base substrate.

(2) In the stacked semiconductor device described in (1) above, a heat radiation member is attached to the logic IC of the uppermost logic type semiconductor package.

(3) In the stacked semiconductor device described in (1) above, a heat dissipation member is attached to the wiring substrate of the uppermost logic type semiconductor package, and heat conduction between both surfaces of the substrate is performed on the wiring substrate. A heat conducting member for performing is provided.

(4) In the stacked semiconductor device described in (1) above, a plurality of the memory type semiconductor packages are stacked, and a memory type semiconductor package with a small number of external electrodes is disposed on the base substrate side. It is characterized by that.

(5) In the stacked semiconductor device according to (1), a plurality of the memory type semiconductor packages are stacked, and a memory type semiconductor package having a small area of the wiring board is disposed on the base substrate side. It is characterized by that.

(6) A semiconductor package having a wiring board in which a semiconductor element is mounted on the center side and an external connection land is provided on at least one side on the outer peripheral side, and a base board on which a plurality of these semiconductor packages are stacked and mounted. And the base substrate connects the second semiconductor package with a first electrode portion having an electrode array for connecting an external connection land of the first semiconductor package among the plurality of semiconductor packages. A second electrode portion having a plurality of electrode rows, wherein the electrode row arrangement direction in the first electrode portion and the electrode arrangement direction of the second electrode portion intersect with each other. It is characterized by being.

(7) In the stacked semiconductor device according to (6), the plurality of semiconductor packages have at least one of a plurality of different varieties, and among the electrode portions provided on the wiring board The arrangement direction of the electrode rows of the electrode portions corresponding to the same type of semiconductor package is arranged in parallel.

(8) In the stacked semiconductor device described in (7) above, a part of the semiconductor parts connected to the same type of semiconductor package is electrically connected. Features.

(9) The stacked semiconductor device according to (6), wherein a semiconductor package having a small number of external electrodes among the plurality of semiconductor packages is arranged on the base substrate side.

(10) The stacked semiconductor device according to (6), wherein a semiconductor package having a small area of a wiring board among the plurality of semiconductor packages is arranged on the base substrate side.

  According to the present invention, even if a memory IC and a logic IC are stacked, they can be manufactured at a low cost, and the size can be reduced and the heat dissipation efficiency of the logic IC can be improved.

  FIG. 1 is a sectional view showing a stacked semiconductor device 100 according to the first embodiment of the present invention. The stacked semiconductor device 100 includes a base substrate 101. A first memory type semiconductor package 110, a second memory type semiconductor package 120, and a logic type semiconductor package 130 are sequentially stacked on the base substrate 101 from the base substrate 101 side. Further, a metal cap 150 is attached via an anisotropic conductive film 140.

  As shown in FIGS. 2 and 3, the first memory type semiconductor package 110 includes a wiring substrate 111 formed of glass epoxy or the like having a thickness of about 50 μm. On the main surface (lower surface in FIG. 1) 111a of the wiring substrate 111, a wiring pattern 112 such as copper having a thickness of about 18 μm and an external connection land 113 having a diameter of about 100 μm are formed. Note that a solder 114 such as tin having a thickness of about 5 μm is formed on the surface of the external connection land 113 by plating, for example.

  In addition, a memory IC 115 having flexibility by being formed to a thickness of about 60 μm is flip-chip mounted at a predetermined portion of the wiring pattern 112 via a bump 116 having a height of about 10 to 30 μm. .

  When the memory IC 115 is flip-chip connected, an anisotropic conductive film (ACF) 117 is interposed therebetween, for example, by thermocompression bonding at a temperature of 180.degree. Sealing is also performed.

  The external size of the first memory type semiconductor package 110 is 10 mm × 10 mm, the thickness is 50 μm, the number of external connection lands 113 is 40, and the memory IC 114 having a size of 6 mm × 7.5 mm is arranged in a staggered manner only outside one side. Arranged in two rows. The size of the wiring substrate 111 and the number of external connection lands 113 differ depending on the type of the memory IC 115 to be mounted.

  The second memory type semiconductor package 120 is formed in substantially the same manner as the first memory type semiconductor package 110 as shown in FIGS. That is, a wiring pattern 122 such as copper having a thickness of about 18 μm and an external connection land 123 having a diameter of about 100 μm are formed on the main surface (lower surface in FIG. 1) 121a of the wiring substrate 121. For example, a solder 124 such as tin having a thickness of about 5 μm is formed on the surface of the external connection land 123 by plating.

  Further, a memory IC 125 having flexibility by being formed to a thickness of about 60 μm is flip-chip mounted at a predetermined portion of the wiring pattern 122 via a bump 126 having a height of about 10 to 30 μm. .

  The second memory type semiconductor package 120 has an external size of 11 mm × 11 mm and 50 external connection lands 113, and is arranged in two rows in a staggered arrangement only outside one side of the memory IC 124 having a size of 9 mm × 10 mm. Yes.

  As shown in FIGS. 4 and 5, the logic type semiconductor package 130 includes a wiring substrate 131 made of glass epoxy having a thickness of about 50 μm. A wiring pattern 132 such as copper having a thickness of about 18 μm is formed on the main surface (upper surface in FIG. 1) 131a of the wiring substrate 131, and a diameter of about 100 μm is formed on the second main surface (lower surface in FIG. 1) 131b. An external connection land 133 is formed. Note that the wiring pattern 132 and the external connection land 133 are connected via a conduction part 131 d filled in a through hole 131 c provided in the wiring board 131. Further, on the surface of the external connection land 133, for example, a solder 134 such as tin having a thickness of about 5 μm is formed by plating.

  In addition, a logic IC 135 having flexibility by being formed to a thickness of about 60 μm is flip-chip mounted on a predetermined portion of the wiring pattern 132 via a bump 136 having a height of about 10 to 30 μm. .

  When flip-chip connection of the logic IC 135 is performed, an anisotropic conductive film 137 is interposed therebetween, for example, by thermocompression bonding at a temperature of 180 ° C., and at the same time, electrical connection is performed and resin sealing is also performed. Has been done.

  The external size of the logic type semiconductor package 130 is, for example, 14 mm × 14 mm, the thickness is 50 μm, and the number of external connection lands 133 is 40, and the size is, for example, 8.5 mm × 8.5 mm outside the two opposite sides of the logic IC 135. They are arranged in two rows each in a staggered arrangement.

  The adhesive member 140 is formed of an anisotropic conductive film, and the size thereof is, for example, 9.0 mm × 9.0 mm. The size of the anisotropic conductive film 140 may be the same as or smaller than that of the logic IC 135. The metal cap 150 is made of a metal material such as copper and has a bottomed cylindrical shape.

  As shown in FIG. 6, the base substrate 101 is provided with electrode portions 102 to 105 that are used for connection to external connection lands 113, 123, and 133. The electrode portions 102 to 105 are connected to connection terminals (not shown) to the outside of the stacked semiconductor device 100. Gold bumps 106 are attached to the electrode portions 102 to 105, respectively.

  7 to 18 are diagrams illustrating the manufacturing process of the stacked semiconductor device 100 described above. In these figures, T indicates a heating and pressing tool having an adsorption function. First, an anisotropic conductive film is temporarily attached by thermocompression bonding at 150 ° C. for 10 seconds so as to sufficiently cover the external connection land 113 of the first memory type semiconductor package 110. The memory type semiconductor package 110 is positioned so that the second main surface 111b side of the wiring substrate 111 is held by using the heating and pressing tool T, and the external connection land 113 is opposed to the electrode portion 102 of the base substrate 101. Mount together.

  Next, by applying a load of 1.0 N / bump from the second main surface 111b side of the wiring substrate 111 with the heating and pressing tool T and heating at 180 ° C. for 20 seconds, the first-layer memory type semiconductor package 110 is heated. And the base substrate 101 are connected.

  Next, the second memory type semiconductor package 120 is connected in the same manner as when the first memory type semiconductor package 110 is connected to the base substrate 101, and the logic type semiconductor package 130 is also connected in the same manner.

  Next, the metal cap 150 to which the anisotropic conductive film 140 is temporarily bonded is mounted after aligning the positions of the logic IC 135 and the anisotropic conductive film 140. Next, after temporarily pressing with a heating and pressing tool T at 120 ° C. under a load of 5N for 10 seconds, the resin is completely cured by being left in an oven at 125 ° C. for 1 hour.

  In the stacked semiconductor device 100 according to the first embodiment of the present invention, the first memory type semiconductor package 110 connected to the base substrate 101 is more externally connected than the second memory semiconductor package 120. Since the number of 113 and the small size of the wiring substrate 111 are selected, the mounting area of the base substrate 101 can be reduced, and therefore the size of the base substrate 101 can be reduced. As a result, the stacked semiconductor device 100 itself can be reduced in size.

  On the other hand, the external connection lands 113, 123, 133 are provided only on one side of the wiring substrates 111, 121, 131 of a single memory type semiconductor package laminated on the base substrate 101, and the member cost is reduced by not using an intermediate material. And it becomes possible to manufacture at low cost.

  Furthermore, by bonding a single logic type semiconductor package 130 and a metal cap 150 that is also used to protect the stacked type semiconductor device, a stacked type that can efficiently dissipate heat generated from the logic IC during the operation of the stacked type semiconductor device. A semiconductor device is realized.

  As described above, according to the stacked semiconductor device 100 according to the first embodiment of the present invention, even if a memory IC and a logic IC are stacked, they can be manufactured at a low cost, are small in size, It is possible to improve the heat dissipation efficiency of the IC.

  In the first embodiment described above, the locations of the external connection lands 113 and 123 are arranged only on the outer side of one side of the mounted memory ICs 115 and 125, but the present invention is not limited to this. The outside or the outside of the three sides may be used. Further, the external connection lands 113 do not need to be arranged in a staggered manner in two rows, and may be one or three rows, or may not be a staggered arrangement.

  In addition, in order to bond the first memory semiconductor package 110 in a region other than the electrode portion 102, the anisotropic conductive film supplied so as to sufficiently cover the external connection land is used as the wiring of the first memory type semiconductor package 110. You may make it supply to the main surface 111a whole surface of the board | substrate 111. FIG. Note that instead of the anisotropic conductive film, a sealing resin paste or a sealing resin film may be used.

  However, it is desirable that the sealing resin paste or the sealing resin film has the same curing property as that of the anisotropic conductive film, and the resin physical properties after the curing are also reliable in connection between the memory IC 115 and the wiring substrate 111. In order to ensure the properties, it is desirable that the anisotropic conductive film 117 is equivalent to at least the linear expansion coefficient or Young's modulus. However, the adhesive member is not limited to the above as long as the adhesive member satisfies the reliability required for the stacked semiconductor device 100. Furthermore, in order to ensure high thermal conductivity in the resin, a metal powder such as Ni of about 1 to 5 μm may be mixed in the resin.

  Instead of the anisotropic conductive film 140, a sealing resin paste such as an epoxy resin or a sealing resin film may be used. In this case, the conditions required for the sealing resin paste or the sealing resin film are the same as those described above.

  Furthermore, the anisotropic conductive film 140 may be temporarily press-bonded to the back surface of the logic IC 135. Further, an anisotropic conductive film of the same type as the anisotropic conductive film 140 is supplied onto the outer peripheral portion of the base substrate 101, the base substrate 101 and the metal cap 150 are bonded, and the stacked semiconductor device 100 is firmly fixed. It may be.

  For flip chip connection, a solder bonding method, a crimp connection method, or the like may be used in addition to thermocompression bonding.

  FIG. 19 is a longitudinal sectional view showing a stacked semiconductor device 200 according to the second embodiment of the present invention. 19, the same reference numerals are given to the same functional portions as those in FIG. 1, and detailed description thereof will be omitted.

  The difference between the stacked semiconductor device 200 and the stacked semiconductor device 100 described above is that the memory-type semiconductor packages 110 and 120 and the logic-type semiconductor package 130 are bonded with an anisotropic conductive film 201.

  According to the stacked semiconductor device 200 configured as described above, the same effect as that of the stacked semiconductor device 100 described above can be obtained, and heat generated from the logic IC 135 during the operation can be transferred to the anisotropic conductive film 201. It is possible to dissipate heat by transmitting to the metal cap 150 via.

  20 is a longitudinal sectional view showing a stacked semiconductor device 300 according to the third embodiment of the present invention, and FIG. 21 is a longitudinal sectional view showing a logic type semiconductor package 330 incorporated in the stacked semiconductor device 300. FIG. 22 is a plan view of the logic type semiconductor package 330. FIG. In these drawings, the same functional parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The stacked semiconductor device 300 is different from the stacked semiconductor device 100 described above in that a logic semiconductor package 330 is provided instead of the logic semiconductor package 130. As shown in FIG. 21, the logic type semiconductor package 330 includes a wiring board 331 formed of glass epoxy or the like having a thickness of about 50 μm. A wiring pattern 332 made of copper or the like having a thickness of about 18 μm and an external connection land 333 having a diameter of about 100 μm are formed on the main surface (lower surface in FIG. 21) 331a of the wiring substrate 331. A plurality of through holes 331c having a diameter of 100 μm, for example, filled with a heat conducting member 340 such as copper are disposed on the entire mounting surface of the logic IC 335 at a location where insulation from the external connection land 333 is obtained.

  Further, on the surface of the external connection land 333, for example, a solder 334 such as tin having a thickness of about 5 μm is formed by plating. The external connection lands 333 are staggered in two rows outside the four sides of the logic IC 335.

  Further, a logic IC 335 having flexibility by being formed to have a thickness of about 60 μm is flip-chip mounted on a predetermined portion of the wiring pattern 332 via a bump 336 having a height of about 10 to 30 μm. .

  When flip-chip connection of the logic IC 335 is performed, an anisotropic conductive film 337 is interposed therebetween, for example, by thermocompression bonding at a temperature of 180 ° C., and at the same time, electrical connection is performed and resin sealing is also performed. Has been done.

  According to the stacked semiconductor device 300 configured as described above, the same effects as those of the stacked semiconductor device 100 described above can be obtained, and the logic IC 335 is disposed on the opposite side of the metal cap 150 with respect to the wiring substrate 311. Even in the case where the heat is generated, the heat generated by the logic IC 334 is transferred to the anisotropic conductive film 140 and the metal cap 150 through the heat conductive member 340, so that sufficient heat dissipation can be performed.

  FIG. 23 is a longitudinal sectional view of a stacked semiconductor device 400 according to the fourth embodiment of the present invention, and FIG. 24 is a plan view. The stacked semiconductor device 400 includes a base substrate 401. On the base substrate 401, a memory type semiconductor package 410, a memory type semiconductor package 420, and a memory type semiconductor package 430 are sequentially stacked from the base substrate 401 side. Of the three semiconductor packages 410 to 430, for example, two are first memory type semiconductor packages of the same type, and the remaining one is a second memory type semiconductor package of a different type from the other two. is there.

  25 is a longitudinal sectional view showing the memory type semiconductor package 410 before being stacked, and FIG. 26 is a plan view. On the wiring substrate 411 having a substrate formed of a glass epoxy substrate having a thickness of about 50 μm and the main surface 411a (upper surface in FIG. 25), a wiring pattern 412 of copper, etc. having a thickness of about 18 μm and φ100 μm A degree of connection land 413 is formed. Note that a solder 414 such as tin having a thickness of about 5 μm is formed on the surface of the external connection land 413 by plating, for example. Further, a memory IC 415 having a supportability by being formed to a thickness of about 60 μm is mounted at a predetermined portion of the wiring pattern 412 by using bumps 416 having a height of about 10 to 30 μm. . For example, the size of the memory IC 415 mounted on the first memory type semiconductor package 410 is 6 mm × 7.5 mm.

  When flip-chip bonding the memory IC 415, electrical connection is established by interposing an anisotropic conductive film 417 in which conductive particles are dispersed in a resin, for example, by thermocompression bonding at a temperature of 180 ° C. At the same time, resin sealing is also performed.

  The external size of the first memory type semiconductor package 410 is 10 mm × 10 mm, and the number of external connection lands 413 provided on the wiring board 411 is 40, and they are arranged in two rows in a staggered arrangement only outside one side of the memory IC 415. ing.

  However, the location of the external connection land does not need to be arranged only outside one side of the mounted memory IC 415, and may be arranged outside the two sides or outside the three sides. Further, the connecting lands need not be arranged in a staggered manner in two rows, and may be one or three rows, and need not be in a staggered arrangement.

  The second memory type semiconductor package 420 has a structure similar to that of the first memory type semiconductor package 410. However, the size is different. For example, the size of the memory IC 425 mounted on the second memory type semiconductor package is 9 mm × 10 mm, the external size of the wiring board 421 is 11 mm × 11 mm, and the number of external connection lands 423 is 50. The external connection lands 423 are staggered in two rows only on the outer side of one side of the memory IC 424 mounted in the same manner as the first memory IC mounted semiconductor package 410.

  FIG. 27 is a plan view showing the base substrate 401. The base substrate 401 includes an electrode portion 402 for connection to the first first memory type semiconductor package 410, an electrode portion 403 for connection to the second first memory type semiconductor package 420, a second Electrode portions 404 for connection to the memory type semiconductor package 430 are disposed, and bumps 405 are disposed on each external connection land with gold or the like.

  The electrode parts 402 and 403 are arranged with an interval of 1.5 mm in parallel with the arrangement direction of the electrode parts, and some of them make the characteristics of the first memory type semiconductor packages 410 and 420 sufficiently function. , And is electrically short-circuited via a short circuit 409. The electrode unit 404 is provided in a direction rotated by, for example, 90 ° with respect to the arrangement direction of the electrode units 402 and 403. However, the arrangement direction of the electrode portions 404 provided on the base substrate 401 may be provided in a direction rotated by an arbitrary angle with respect to the arrangement direction of the electrode portions 402 and 403.

  28 to 37 are views showing manufacturing steps of the stacked semiconductor device 400 described above. In these figures, T indicates a heating and pressing tool having an adsorption function. First, an anisotropic conductive film is temporarily attached by thermocompression bonding at 150 ° C. for 10 seconds so as to sufficiently cover the external connection land 413 of the first memory type semiconductor package 410. The memory type semiconductor package 410 is positioned so that the second main surface 411b side of the wiring substrate 411 is held by using the heating and pressing tool T, and the external connection land 413 is opposed to the electrode portion 402 of the base substrate 401. Mount together.

  Next, by applying a load of 0.5 N / bump from the second main surface 411b side of the wiring substrate 411 with the heating and pressing tool T and heating at 180 ° C. for 20 seconds, the first memory type semiconductor package 410 and A base substrate 401 is connected.

  Next, the memory type semiconductor package 420 is connected in the same manner as when the memory type semiconductor package 410 is connected to the base substrate 401, and the memory type semiconductor package 430 is also connected in the same manner.

  Furthermore, in order to protect these semiconductor packages 410 to 430 from external impacts, they may be protected with a metal cap similar to that shown in FIG. 1 or may be molded entirely with a sealing resin.

  In such a stacked semiconductor device 400 according to the fourth embodiment of the present invention, the first-layer memory type semiconductor package 410 connected to the base substrate 401 is more external than the second-layer memory semiconductor package 420. Since a small number of connection lands 413 and a small size of the wiring substrate 411 are selected, the mounting area of the base substrate 401 can be reduced, and therefore the size of the base substrate 401 can be reduced. As a result, the stacked semiconductor device 400 itself can be reduced in size.

  On the other hand, the external connection lands 413, 423, and 433 are provided only on one side of the wiring substrates 411, 421, and 431 of a single memory type semiconductor package laminated on the base substrate 401, and the member cost is reduced by not using an intermediate material. And it becomes possible to manufacture at low cost.

  Further, when a plurality of memory type semiconductor packages of the same type are connected, the electrode portions 402 and 403 are provided adjacent to each other in order to sufficiently function the characteristics, and when semiconductor packages of different types are stacked, The wiring direction of the base substrate 401 is routed by rotating the alignment direction of the electrode portion 404 for the semiconductor package to be connected next to the alignment direction of the external connection land for the semiconductor package connected to the base substrate. Can be made easier.

  As described above, the stacked semiconductor device 400 according to the fourth embodiment of the present invention realizes cost reduction and downsizing in a stacked semiconductor device in which other types and types of semiconductor packages are mixedly mounted. The base substrate wiring can be easily routed.

  In the fourth embodiment described above, the locations of the external connection lands 413 and 423 are arranged only on the outer side of one side of the mounted memory ICs 415 and 425. However, the present invention is not limited to this. The outside or the outside of the three sides may be used. Further, the external connection lands 413 need not be staggered in two rows, and may be one or three rows, or may not be in a staggered arrangement.

  Further, in order to bond the memory type semiconductor package 410 in a region other than the electrode portion 402, an anisotropic conductive film supplied so as to sufficiently cover the external connection land 413 is used as the main wiring board 411 of the memory type semiconductor package 410. The entire surface 411a may be supplied. Note that instead of the anisotropic conductive film, a sealing resin paste or a sealing resin film may be used.

  However, it is desirable that the sealing resin paste or the sealing resin film has the same curing property as that of the anisotropic conductive film, and the resin property after the curing is also reliable in connection between the memory IC 415 and the wiring substrate 411. In order to secure the properties, it is desirable that the anisotropic conductive film 417 is equivalent to at least the linear expansion coefficient or Young's modulus. However, the adhesive member is not limited to the above as long as it satisfies the reliability required for the stacked semiconductor device 400. Furthermore, in order to ensure high thermal conductivity in the resin, a metal powder such as Ni of about 1 to 5 μm may be mixed in the resin.

  Note that a sealing resin paste such as an epoxy resin or a sealing resin film may be used instead of the anisotropic conductive film 440. In this case, the conditions required for the sealing resin paste or the sealing resin film are the same as those described above.

  Furthermore, although the stacked semiconductor device 400 has been described with a memory IC mounted thereon, the stacked semiconductor device 400 may be applied to a stacked semiconductor device in which semiconductor elements having different functions such as a combination of a memory IC and a logic IC are mixedly mounted.

  For flip chip connection, a solder bonding method, a crimp connection method, or the like may be used in addition to thermocompression bonding.

  FIG. 37 is a longitudinal sectional view showing a stacked semiconductor device 500 according to the fifth embodiment of the present invention, and FIG. 38 is a plan view. In these drawings, the same functional parts as those in FIGS. 23 and 24 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the stacked semiconductor device 500, the alignment direction of the electrode portion 502 for the memory type semiconductor package 410 disposed on the base substrate 401 and the alignment direction of the electrode portion 503 for the memory type semiconductor package 420 constitute the memory ICs 415 and 425. It is arranged in parallel with sandwiching (rotating 180 °).

  Also in the stacked semiconductor device 500 configured as described above, the same effect as that of the above-described stacked semiconductor device 400 can be obtained.

  FIG. 39 is a longitudinal sectional view showing a stacked semiconductor device 600 according to the sixth embodiment of the present invention, and FIG. 40 is a plan view. In these drawings, the same functional parts as those in FIGS. 23 and 24 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the stacked semiconductor device 600, the alignment direction of the electrode portion 602 for the memory type semiconductor package 410 disposed on the base substrate 401 and the alignment direction of the electrode portion 603 of the memory type semiconductor package 420 form an angle of 135 °. .

  Also in the stacked semiconductor device 600 configured as described above, the same effect as that of the above-described stacked semiconductor device 400 can be obtained.

  41 is a longitudinal sectional view showing a stacked semiconductor device 700 according to the seventh embodiment of the present invention, and FIG. 42 is a plan view. In these drawings, the same functional parts as those in FIGS. 23 and 24 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the stacked semiconductor device 700, the external connection land 413 is provided on two sides opposite to the memory type semiconductor package 410, and the external connection land 423 is provided on two sides opposite to the memory type semiconductor package 420.

  The alignment direction of the electrode portions 702 and 703 for the memory type semiconductor package 410 arranged on the base substrate 401 and the alignment direction of the electrode portions 704 and 705 of the memory type semiconductor package 420 form an angle of 90 °.

  Also in the stacked semiconductor device 700 configured as described above, the same effects as those of the above-described stacked semiconductor device 400 can be obtained.

  FIG. 43 is a longitudinal sectional view showing a stacked semiconductor device 800 according to the eighth embodiment of the present invention, and FIG. 44 is a plan view. In these drawings, the same functional parts as those in FIGS. 23 and 24 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the stacked semiconductor device 800, the external connection lands 413 are provided on two sides adjacent to the memory type semiconductor package 410, and the external connection lands 423 are provided on two sides adjacent to the memory type semiconductor package 420.

  The base substrate 401 is provided with electrode portions 802 and 803 for the memory type semiconductor package 410 and electrode portions 804 and 805 of the memory type semiconductor package 420. The alignment direction of the electrode portion 802 and the alignment direction of the electrode portion 804 are provided. In parallel, the alignment direction of the electrode portion 803 and the alignment direction of the electrode portion 804 form an angle of 90 °.

  Also in the stacked semiconductor device 800 configured as described above, the same effect as that of the above-described stacked semiconductor device 400 can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  According to the present invention, even if a memory IC and a logic IC are three-dimensionally stacked, a stacked semiconductor device that can be manufactured at a low cost, is small, and can improve the heat dissipation efficiency of the logic IC. can get.

1 is a longitudinal sectional view showing a stacked semiconductor device according to a first embodiment of the present invention. The longitudinal cross-sectional view which shows the memory type semiconductor package before the assembly incorporated in the same laminated semiconductor device. The top view which shows the memory type semiconductor package. The longitudinal cross-sectional view which shows the logic type semiconductor package before the assembly integrated in the same laminated semiconductor device. The top view which shows the logic type semiconductor package. The top view which shows the base substrate before the assembly integrated in the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. FIG. 6 is a longitudinal sectional view of a stacked semiconductor device according to a second embodiment of the present invention. FIG. 6 is a longitudinal sectional view of a stacked semiconductor device according to a third embodiment of the present invention. The longitudinal cross-sectional view which shows the logic type semiconductor package before the assembly integrated in the same laminated semiconductor device. The top view which shows the logic type semiconductor package before the assembly integrated in the same laminated semiconductor device. FIG. 9 is a longitudinal sectional view of a stacked semiconductor device according to a fourth embodiment of the invention. FIG. 3 is a plan view of the stacked semiconductor device. The longitudinal cross-sectional view which shows the memory type semiconductor package before the assembly incorporated in the same laminated semiconductor device. The top view which shows the memory type semiconductor package before the assembly assembled in the same laminated semiconductor device. The top view which shows the base substrate before the assembly integrated in the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the manufacturing process of the same laminated semiconductor device. The top view which shows the manufacturing process of the same laminated semiconductor device. Sectional drawing which shows the laminated semiconductor device which concerns on the 5th Embodiment of this invention. The top view which shows the same laminated semiconductor device. Sectional drawing which shows the laminated semiconductor device which concerns on the 6th Embodiment of this invention. The top view which shows the same laminated semiconductor device. Sectional drawing which shows the laminated semiconductor device which concerns on the 7th Embodiment of this invention. The top view which shows the same laminated semiconductor device. Sectional drawing which shows the laminated semiconductor device which concerns on the 8th Embodiment of this invention. The top view which shows the same laminated semiconductor device. Sectional drawing which shows an example of the conventional laminated semiconductor device.

Explanation of symbols

  100, 200, 300, 400, 500, 600, 700, 800 ... stacked semiconductor device, 101, 401 ... wiring board, 110, 120, 410, 420, 430 ... memory type semiconductor package, 130 ... logic type semiconductor package, 140: anisotropic conductive film, 150: metal cap.

Claims (10)

A memory type semiconductor package having a wiring substrate on which a memory IC is mounted;
A logic type semiconductor package having a logic wiring board on which a logic IC is mounted;
A base substrate on which at least one of these memory type semiconductor package and logic type semiconductor package is stacked and mounted; and
The stacked semiconductor device, wherein the logic type semiconductor package is disposed at least on the uppermost layer farthest from the base substrate.   A stacked semiconductor device, wherein a heat radiating member is attached to the logic IC of the uppermost logic type semiconductor package. A heat dissipating member is attached to the wiring substrate of the uppermost logic type semiconductor package,
2. The stacked semiconductor device according to claim 1, wherein the wiring board is provided with a heat conducting member for conducting heat conduction between both sides of the board.   2. The stacked semiconductor device according to claim 1, wherein a plurality of the memory type semiconductor packages are stacked, and a memory type semiconductor package having a small number of external electrodes is disposed on the base substrate side.   2. The stacked semiconductor device according to claim 1, wherein a plurality of the memory type semiconductor packages are stacked, and a memory type semiconductor package having a small area of the wiring substrate is disposed on the base substrate side. A semiconductor package having a wiring board in which a semiconductor element is mounted on the center side and an external connection land is provided on at least one side on the outer peripheral side;
A base substrate on which a plurality of these semiconductor packages are stacked and mounted;
The base substrate includes: a first electrode portion having an electrode row for connecting an external connection land of the first semiconductor package among the plurality of semiconductor packages;
A second electrode portion having an electrode array for connecting the second semiconductor package,
A stacked semiconductor device, wherein the arrangement direction of the electrode rows in the first electrode portion and the arrangement direction of the electrode rows in the second electrode portion intersect with each other. The plurality of semiconductor packages have at least one of a plurality of different varieties,
7. The stacked type according to claim 6, wherein among the electrode portions provided on the wiring board, the electrode rows of the electrode portions corresponding to the same type of semiconductor package are arranged in parallel. Semiconductor device.   8. The stacked semiconductor device according to claim 7, wherein a part of the electrode parts to which semiconductor packages of the same kind among the semiconductor packages are connected are electrically connected.   7. The stacked semiconductor device according to claim 6, wherein a semiconductor package having a small number of external electrodes among the plurality of semiconductor packages is disposed on the base substrate side.   7. The stacked semiconductor device according to claim 6, wherein a semiconductor package having a small area of a wiring board among the plurality of semiconductor packages is arranged on the base substrate side.

Images