JP2008305909A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure capable of both expanding a region capable of arranging a wiring of a wiring board, and maintaining a mechanical stability of a semiconductor chip. <P>SOLUTION: A semiconductor device 1 comprises a wiring board 10, a spacer 20, and the semiconductor chip 30. The spacer 20 is provided on the wiring board 10. The semiconductor chip 30 is provided on the spacer 20. Assuming an angle between the side of the spacer 20 and the side of the semiconductor chip 30 is θ in planar view, the inequality expression 0<θ<90° consists. Further, a center of the spacer 20 unnecessarily corresponds to a center of the semiconductor chip 30. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  FIG. 12 is a cross-sectional view showing a conventional semiconductor device. In the semiconductor device 100, the semiconductor chip 104 is mounted on the wiring substrate 102. The semiconductor chip 104 is fixed to the wiring substrate 102 by a paste-like adhesive material 106. Part of the adhesive 106 protrudes from between the wiring substrate 102 and the semiconductor chip 104 to form a fillet 106a. The semiconductor chip 104 is electrically connected to the wiring board 102 via bonding wires 108. One end of the bonding wire 108 is connected to the stitch 110 of the wiring substrate 102, and the other end is connected to an electrode (not shown) of the semiconductor chip 104.

  A sealing resin 112 is formed on the wiring substrate 102 so as to cover the semiconductor chip 104 and the bonding wires 108. Further, bumps 114 are connected to the lower surface of the wiring board 102. The bump 114 functions as an external electrode terminal of the semiconductor device 100.

In addition, patent documents 1-4 are mentioned as a prior art document relevant to this invention.
JP-A-4-38859 JP 2005-136332 A JP 2006-86149 A JP 2003-234451 A

  By the way, in the semiconductor device 100, it is preferable not to provide the wiring of the wiring board 102 in a region located under the semiconductor chip 104. This is because stress tends to concentrate on the wiring in this region (particularly, the region located immediately below the outer periphery of the semiconductor chip 104). Concentration of stress on the wiring leads to wiring cracks (disconnection). Therefore, it is preferable to arrange the wiring of the wiring substrate 102 so as to avoid the above-described region in order to realize a highly reliable semiconductor device 100. However, in that case, an area on the wiring board 102 where wiring can be arranged becomes narrow. Therefore, in order to secure a sufficient area for wiring, the wiring board 102 must be enlarged.

  Therefore, in order to prevent the wiring board 102 and the semiconductor chip 104 from coming into direct contact, it is conceivable to interpose a spacer between them. When introducing the spacers, it is important to maintain the mechanical stability of the semiconductor chip 104 during the manufacture of the semiconductor device 100 in addition to widening the region where the wiring of the wiring substrate 102 can be arranged. For example, if the spacer is too small, the mechanical stability of the semiconductor chip 104 disposed thereon is hindered. On the other hand, if the spacer is too large, expansion of the region where the wiring can be arranged is hindered. This is because stress is easily concentrated on the wiring also in the region located under the spacer.

  A semiconductor device according to the present invention includes a wiring board, a spacer provided on the wiring board, and a semiconductor chip provided on the spacer, and the side of the spacer and the side of the semiconductor chip in plan view. 0 <θ <90 °, where θ is the angle formed by.

  In this semiconductor device, the side of the spacer and the side of the semiconductor chip form an angle θ (0 <θ <90 °). In other words, the spacer is arranged at an angle with respect to the semiconductor chip. As a result, even if a spacer having a certain size is used, a space can be secured between the semiconductor chip and the wiring board. Even if the wiring of the wiring board is arranged in a region located below the space, concentration of stress on the wiring can be avoided. Therefore, a semiconductor device having a structure suitable for coexistence of expansion of a region where wirings can be arranged and maintenance of mechanical stability of the semiconductor chip is realized.

  According to the present invention, a semiconductor device having a structure suitable for coexistence of expansion of an area in which wiring of a wiring board can be arranged and maintenance of mechanical stability of a semiconductor chip is realized.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.
(First embodiment)

  FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a wiring substrate 10, a spacer 20, and a semiconductor chip 30. In the present embodiment, the wiring board 10 is a multilayer wiring board.

  Spacers 20 are provided on the wiring board 10. The spacer 20 is provided on the wiring board 10 via an adhesive 42. The spacer 20 is fixed to the wiring board 10 by the adhesive 42. The adhesive 42 may be a paste-like adhesive or a film-like adhesive. As the adhesive 42, for example, a silver paste can be used. The material of the spacer 20 is, for example, silicon or resin. In the present embodiment, the spacer 20 is not formed with a semiconductor element such as a transistor.

  A semiconductor chip 30 is provided on the spacer 20. The semiconductor chip 30 is provided on the spacer 20 via an adhesive material 44. The semiconductor chip 30 is fixed to the spacer 20 by the adhesive material 44. In the present embodiment, the adhesive material 44 is a paste-like adhesive material. However, the adhesive material 44 may be a film-like adhesive material. As the adhesive 44, for example, a silver paste can be used. A part of the adhesive 44 protrudes from between the spacer 20 and the semiconductor chip 30 to form a fillet 44a. In the present embodiment, the semiconductor chip 30 includes a silicon substrate.

  The semiconductor chip 30 is electrically connected to the wiring board 10 via bonding wires 46. The bonding wire 46 has one end connected to the stitch 12 of the wiring substrate 10 and the other end connected to an electrode (not shown) of the semiconductor chip 30.

  A sealing resin 50 is formed on the wiring substrate 10 so as to cover the spacer 20, the semiconductor chip 30 and the bonding wire 46. A bump 60 is connected to the lower surface of the wiring board 10. The bump 60 functions as an external electrode terminal of the semiconductor device 1.

  FIG. 2 is a plan view showing the wiring board 10, the spacer 20, and the semiconductor chip 30 in FIG. A cross section taken along line II in FIG. 2 corresponds to the cross section in FIG. FIG. 2 shows the uppermost wiring 14 in the wiring board 10. As can be seen from FIG. 2, the spacer 20 and the semiconductor chip 30 are both rectangular in plan view.

  Further, when the angle formed by the side of the spacer 20 and the side of the semiconductor chip 30 in a plan view is θ, 0 <θ <90 °. In this embodiment, θ is equal to 45 °. Thereby, the spacer 20 does not overlap the corner of the semiconductor chip 30. On the other hand, the spacer 20 overlaps the side of the semiconductor chip 30. The spacer 20 overlaps the center C1 of the semiconductor chip 30. Furthermore, the center of the spacer coincides with the center C1 of the semiconductor chip 30. In the present embodiment, the area of the spacer 20 is equal to or smaller than the area of the semiconductor chip 30. The entire spacer 20 overlaps the semiconductor chip 30.

  The uppermost wiring 14 of the wiring board 10 exists in a region located under the semiconductor chip 30. On the other hand, the wiring 14 does not exist in a region located under the spacer 20.

  The effect of this embodiment will be described. In the semiconductor device 1, the side of the spacer 20 and the side of the semiconductor chip 30 form an angle θ (0 <θ <90 °). That is, the spacer 20 is arranged with an angle shifted with respect to the semiconductor chip 30. Thereby, even if the spacer 20 having a certain size is used, a space can be secured between the semiconductor chip 30 and the wiring substrate 10. From the viewpoint of sufficiently securing the space, θ preferably satisfies 5 ° <θ <85 °. Even if the wiring 14 of the wiring board 10 is arranged in a region located under the space, concentration of stress on the wiring 14 can be avoided. Therefore, the semiconductor device 1 having a structure suitable for coexistence of expansion of a region where the wiring 14 can be arranged and maintenance of the mechanical stability of the semiconductor chip 30 is realized.

  As a result, the degree of freedom in designing the wiring 14 is improved, so that it is possible to ensure a sufficient area in which the wiring 14 is disposed without increasing the size of the wiring substrate 10. Further, if the mechanical stability of the semiconductor chip 30 is high, the load in the assembly process is reduced, and the mass productivity of the semiconductor device 1 is improved. For example, fluctuation in the Z direction (direction perpendicular to the wiring substrate 10) of the semiconductor chip 30 that impairs mass productivity in the bonding process can be suppressed.

  A spacer 20 is interposed between the wiring substrate 10 and the semiconductor chip 30. Thereby, the semiconductor device 1 having high bending strength is realized. This is because even when the wiring substrate 10 is bent by an external force, the influence of the semiconductor chip 30 on the wiring substrate 10 is mitigated by the spacer 20. Even if the spacer 20 is damaged, such as a crack, if the semiconductor chip 30 is not damaged, the normal operation of the semiconductor device 1 can be maintained.

  The spacer 20 overlaps the side of the semiconductor chip 30. Thereby, the mechanical stability of the semiconductor chip 30 can be further improved.

  The area of the spacer 20 is equal to or smaller than the area of the semiconductor chip 30. As a result, a wide space can be secured between the wiring substrate 10 and the semiconductor chip 30, so that the degree of freedom in designing the wiring 14 is further increased.

  When the material of the spacer 20 is silicon, the spacer 20 can be manufactured at low cost by using equipment common to the semiconductor chip 30. In addition, the spacer 20 can be easily handled when the semiconductor device 1 is manufactured. Furthermore, since the difference in thermal expansion coefficient with the semiconductor chip 30 is reduced, the stress generated between the spacer 20 and the semiconductor chip 30 can be suppressed to a low level.

  By the way, Patent Document 1 discloses providing a spacer between a tab and a pellet. However, in this document, the spacer is provided only at the edge of the pellet. For this reason, a plurality of spacers are required to support the pellet. Therefore, there is a problem that the manufacturing cost of the semiconductor device increases.

  On the other hand, in this embodiment, the spacer 20 overlaps the center C1 (see FIG. 2) of the semiconductor chip 30. As a result, the semiconductor chip 30 can be stably supported by the single spacer 20. Therefore, the manufacturing cost of the semiconductor device 1 can be kept low.

  In the semiconductor device 100 shown in FIG. 12, in order to prevent the fillet 106 a from coming into contact with the stitch 110, the outer periphery of the semiconductor chip 104 is taken into consideration in consideration of the amount of protrusion (excess) of the adhesive 106 and the mounting error. To the stitch 110 needs to be set. Here, the mounting error is a positional deviation amount of the semiconductor chip 104 with respect to the wiring substrate 102. Therefore, in the semiconductor device 100, the distance from the outer periphery of the semiconductor chip 104 to the stitch 110 is increased. This leads to an increase in the size of the wiring board 102.

On the other hand, in the present embodiment, the fillet 44a is housed in the space between the wiring substrate 10 and the semiconductor chip 30, and therefore the distance from the outer periphery of the semiconductor chip 30 to the stitch 12 can be shortened. This also contributes to miniaturization of the wiring board 10 and thus the semiconductor device 1. In addition, it is not necessary to strictly control the amount of the adhesive 44 that leaks out to prevent the fillet 44a from contacting the stitch 12. For this reason, the mass productivity of the semiconductor device 1 is further improved.
(Second Embodiment)

  FIG. 3 is a sectional view showing a second embodiment of the semiconductor device according to the present invention. 4 is a plan view showing the wiring substrate 10, the spacer 20, and the semiconductor chip 30 in FIG. A cross section taken along line III-III in FIG. 4 corresponds to the cross section in FIG. In the semiconductor device 2, the passive component 70 is disposed in the space between the wiring substrate 10 and the semiconductor chip 30. The passive component 70 is, for example, a capacitive element or a resistive element. Other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1.

In the present embodiment, the passive component 70 is disposed in the space between the wiring board 10 and the semiconductor chip 30. Thereby, compared with the case where the passive component 70 is arrange | positioned out of the said space, size reduction of the wiring board 10 can be achieved. Further, by disposing the passive component 70 so as to be hidden under the wiring board 10 in this way, it is possible to reduce high frequency noise. Other effects of the present embodiment are the same as those of the first embodiment.
(Third embodiment)

  FIG. 5 is a sectional view showing a third embodiment of the semiconductor device according to the present invention. FIG. 6 is a plan view showing the wiring substrate 10, the spacer 20, and the semiconductor chip 30 in FIG. A cross section taken along line VV in FIG. 6 corresponds to the cross section in FIG. In the semiconductor device 3, a groove 22 is formed on the upper surface of the spacer 20 (the surface on the semiconductor chip 30 side). The groove 22 is formed along the entire outer periphery of the spacer 20. Other configurations of the semiconductor device 3 are the same as those of the semiconductor device 1.

  In the present embodiment, a groove 22 is formed in the spacer 20. The groove 22 can prevent the adhesive 44 from protruding from between the spacer 20 and the semiconductor chip 30. Thereby, the distance from the outer periphery of the semiconductor chip 30 to the stitch 12 can be further shortened. Other effects of the present embodiment are the same as those of the first embodiment.

  In the present embodiment, the grooves 22 may be formed only at the corners of the spacer 20, as shown in FIG. Since the corner portion of the spacer 20 is located near the outer periphery of the semiconductor chip 30, preventing the adhesive from protruding from this portion increases the distance from the outer periphery of the semiconductor chip 30 to the stitch 12 (see FIG. 5). It is particularly effective in shortening. In the present embodiment, passive components may be arranged in the space between the wiring board 10 and the semiconductor chip 30 as in the second embodiment.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, an example in which the spacer 20 overlaps the side of the semiconductor chip 30 has been described. However, as shown in FIG. 8, the spacer 20 may not overlap the side of the semiconductor chip 30. Moreover, in the said embodiment, the example in which the center of the spacer 20 corresponds with the center of the semiconductor chip 30 was shown. However, as shown in FIG. 9, the center of the spacer 20 may not coincide with the center of the semiconductor chip 30.

  Moreover, in the said embodiment, the example in which the whole spacer 20 overlapped with the semiconductor chip 30 was shown. However, as shown in FIGS. 10 and 11, only a part of the spacer 20 may overlap the semiconductor chip 30. Moreover, in the said embodiment, the example whose area of the spacer 20 is less than that of the semiconductor chip 30 was shown. However, as long as a space exists between the wiring substrate 10 and the semiconductor chip 30, the area of the spacer 20 may be larger than that of the semiconductor chip 30.

  Moreover, in the said embodiment, the BGA (Ball Grid Array) type semiconductor device was illustrated. However, the semiconductor device according to the present invention may be an LGA (Land Grid Array) type semiconductor device.

1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. It is a top view which shows the wiring board in FIG. 1, a spacer, and a semiconductor chip. It is sectional drawing which shows 2nd Embodiment of the semiconductor device by this invention. FIG. 4 is a plan view showing a wiring board, a spacer, and a semiconductor chip in FIG. 3. It is sectional drawing which shows 3rd Embodiment of the semiconductor device by this invention. It is a top view which shows the wiring board in FIG. 5, a spacer, and a semiconductor chip. It is a top view for demonstrating the modification of embodiment. It is a top view for demonstrating the modification of embodiment. It is a top view for demonstrating the modification of embodiment. It is a top view for demonstrating the modification of embodiment. It is a top view for demonstrating the modification of embodiment. It is sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor device 3 Semiconductor device 10 Wiring board 12 Stitch 14 Wiring 20 Spacer 22 Groove 30 Semiconductor chip 42 Adhesive material 44 Adhesive material 44a Fillet 46 Bonding wire 50 Sealing resin 60 Bump 70 Passive component 100 Semiconductor device 102 Wiring board 104 Semiconductor chip 106 Adhesive 106a Fillet 108 Bonding wire 110 Stitch 112 Sealing resin 114 Bump C1 Center of semiconductor chip

Claims (22)

A wiring board;
A spacer provided on the wiring board;
A semiconductor chip provided on the spacer,
A semiconductor device wherein 0 <θ <90 °, where θ is an angle formed by a side of the spacer and a side of the semiconductor chip in a plan view. The semiconductor device according to claim 1,
The spacer and the semiconductor chip are both semiconductor devices having a rectangular shape in plan view. The semiconductor device according to claim 1 or 2,
The spacer is a semiconductor device in which the spacer does not overlap a corner of the semiconductor chip. The semiconductor device according to claim 1,
The spacer is a semiconductor device overlapping the center of the semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device, wherein the spacer overlaps a side of the semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device wherein an area of the spacer is equal to or less than an area of the semiconductor chip. The semiconductor device according to claim 1,
The area of the spacer is larger than the area of the semiconductor chip,
A semiconductor device in which a space exists between the wiring board and the semiconductor chip. The semiconductor device according to claim 1,
Θ is a semiconductor device satisfying 5 ° <θ <85 °. The semiconductor device according to claim 8,
The θ is a semiconductor device equal to 45 °. The semiconductor device according to claim 1,
A semiconductor device in which the entire spacer overlaps the semiconductor chip. The semiconductor device according to claim 1,
A semiconductor device in which a part of the spacer overlaps the semiconductor chip. The semiconductor device according to claim 1,
A semiconductor device further comprising a passive component disposed in a space between the wiring board and the semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device is a semiconductor device provided on the spacer via an adhesive. The semiconductor device according to claim 13,
The semiconductor device in which the adhesive protrudes from between the spacer and the semiconductor chip. The semiconductor device according to claim 1,
A semiconductor device in which a groove is formed on a surface of the spacer on the semiconductor chip side. The semiconductor device according to claim 15,
The groove is a semiconductor device formed along the entire outer periphery of the spacer. The semiconductor device according to claim 15,
The groove is a semiconductor device formed at a corner of the spacer. The semiconductor device according to claim 1,
The wiring of the said wiring board is a semiconductor device which exists in the area | region located under the said semiconductor chip. The semiconductor device according to claim 1,
A semiconductor device in which the wiring of the wiring board does not exist in a region located under the spacer. The semiconductor device according to claim 1,
A semiconductor device in which a center of the spacer coincides with a center of the semiconductor chip in a plan view. 21. The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the semiconductor chip is electrically connected to the wiring board via a bonding wire. The semiconductor device according to any one of claims 1 to 21,
A semiconductor device in which a semiconductor element is not formed in the spacer.

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